1*4882a593Smuzhiyun/* 2*4882a593Smuzhiyun * Copyright 2017 Gateworks Corporation 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * This file is dual-licensed: you can use it either under the terms 5*4882a593Smuzhiyun * of the GPL or the X11 license, at your option. Note that this dual 6*4882a593Smuzhiyun * licensing only applies to this file, and not this project as a 7*4882a593Smuzhiyun * whole. 8*4882a593Smuzhiyun * 9*4882a593Smuzhiyun * a) This file is free software; you can redistribute it and/or 10*4882a593Smuzhiyun * modify it under the terms of the GNU General Public License as 11*4882a593Smuzhiyun * published by the Free Software Foundation; either version 2 of 12*4882a593Smuzhiyun * the License, or (at your option) any later version. 13*4882a593Smuzhiyun * 14*4882a593Smuzhiyun * This file is distributed in the hope that it will be useful, 15*4882a593Smuzhiyun * but WITHOUT ANY WARRANTY; without even the implied warranty of 16*4882a593Smuzhiyun * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17*4882a593Smuzhiyun * GNU General Public License for more details. 18*4882a593Smuzhiyun * 19*4882a593Smuzhiyun * You should have received a copy of the GNU General Public 20*4882a593Smuzhiyun * License along with this file; if not, write to the Free 21*4882a593Smuzhiyun * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, 22*4882a593Smuzhiyun * MA 02110-1301 USA 23*4882a593Smuzhiyun * 24*4882a593Smuzhiyun * Or, alternatively, 25*4882a593Smuzhiyun * 26*4882a593Smuzhiyun * b) Permission is hereby granted, free of charge, to any person 27*4882a593Smuzhiyun * obtaining a copy of this software and associated documentation 28*4882a593Smuzhiyun * files (the "Software"), to deal in the Software without 29*4882a593Smuzhiyun * restriction, including without limitation the rights to use, 30*4882a593Smuzhiyun * copy, modify, merge, publish, distribute, sublicense, and/or 31*4882a593Smuzhiyun * sell copies of the Software, and to permit persons to whom the 32*4882a593Smuzhiyun * Software is furnished to do so, subject to the following 33*4882a593Smuzhiyun * conditions: 34*4882a593Smuzhiyun * 35*4882a593Smuzhiyun * The above copyright notice and this permission notice shall be 36*4882a593Smuzhiyun * included in all copies or substantial portions of the Software. 37*4882a593Smuzhiyun * 38*4882a593Smuzhiyun * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 39*4882a593Smuzhiyun * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES 40*4882a593Smuzhiyun * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 41*4882a593Smuzhiyun * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT 42*4882a593Smuzhiyun * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, 43*4882a593Smuzhiyun * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 44*4882a593Smuzhiyun * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 45*4882a593Smuzhiyun * OTHER DEALINGS IN THE SOFTWARE. 46*4882a593Smuzhiyun */ 47*4882a593Smuzhiyun 48*4882a593Smuzhiyun#include <dt-bindings/gpio/gpio.h> 49*4882a593Smuzhiyun#include <dt-bindings/input/linux-event-codes.h> 50*4882a593Smuzhiyun#include <dt-bindings/interrupt-controller/irq.h> 51*4882a593Smuzhiyun 52*4882a593Smuzhiyun/ { 53*4882a593Smuzhiyun /* these are used by bootloader for disabling nodes */ 54*4882a593Smuzhiyun aliases { 55*4882a593Smuzhiyun led0 = &led0; 56*4882a593Smuzhiyun led1 = &led1; 57*4882a593Smuzhiyun led2 = &led2; 58*4882a593Smuzhiyun usb0 = &usbh1; 59*4882a593Smuzhiyun usb1 = &usbotg; 60*4882a593Smuzhiyun }; 61*4882a593Smuzhiyun 62*4882a593Smuzhiyun chosen { 63*4882a593Smuzhiyun stdout-path = &uart2; 64*4882a593Smuzhiyun }; 65*4882a593Smuzhiyun 66*4882a593Smuzhiyun backlight { 67*4882a593Smuzhiyun compatible = "pwm-backlight"; 68*4882a593Smuzhiyun pwms = <&pwm4 0 5000000>; 69*4882a593Smuzhiyun brightness-levels = <0 4 8 16 32 64 128 255>; 70*4882a593Smuzhiyun default-brightness-level = <7>; 71*4882a593Smuzhiyun }; 72*4882a593Smuzhiyun 73*4882a593Smuzhiyun gpio-keys { 74*4882a593Smuzhiyun compatible = "gpio-keys"; 75*4882a593Smuzhiyun #address-cells = <1>; 76*4882a593Smuzhiyun #size-cells = <0>; 77*4882a593Smuzhiyun 78*4882a593Smuzhiyun user-pb { 79*4882a593Smuzhiyun label = "user_pb"; 80*4882a593Smuzhiyun gpios = <&gsc_gpio 0 GPIO_ACTIVE_LOW>; 81*4882a593Smuzhiyun linux,code = <BTN_0>; 82*4882a593Smuzhiyun }; 83*4882a593Smuzhiyun 84*4882a593Smuzhiyun user-pb1x { 85*4882a593Smuzhiyun label = "user_pb1x"; 86*4882a593Smuzhiyun linux,code = <BTN_1>; 87*4882a593Smuzhiyun interrupt-parent = <&gsc>; 88*4882a593Smuzhiyun interrupts = <0>; 89*4882a593Smuzhiyun }; 90*4882a593Smuzhiyun 91*4882a593Smuzhiyun key-erased { 92*4882a593Smuzhiyun label = "key-erased"; 93*4882a593Smuzhiyun linux,code = <BTN_2>; 94*4882a593Smuzhiyun interrupt-parent = <&gsc>; 95*4882a593Smuzhiyun interrupts = <1>; 96*4882a593Smuzhiyun }; 97*4882a593Smuzhiyun 98*4882a593Smuzhiyun eeprom-wp { 99*4882a593Smuzhiyun label = "eeprom_wp"; 100*4882a593Smuzhiyun linux,code = <BTN_3>; 101*4882a593Smuzhiyun interrupt-parent = <&gsc>; 102*4882a593Smuzhiyun interrupts = <2>; 103*4882a593Smuzhiyun }; 104*4882a593Smuzhiyun 105*4882a593Smuzhiyun tamper { 106*4882a593Smuzhiyun label = "tamper"; 107*4882a593Smuzhiyun linux,code = <BTN_4>; 108*4882a593Smuzhiyun interrupt-parent = <&gsc>; 109*4882a593Smuzhiyun interrupts = <5>; 110*4882a593Smuzhiyun }; 111*4882a593Smuzhiyun 112*4882a593Smuzhiyun switch-hold { 113*4882a593Smuzhiyun label = "switch_hold"; 114*4882a593Smuzhiyun linux,code = <BTN_5>; 115*4882a593Smuzhiyun interrupt-parent = <&gsc>; 116*4882a593Smuzhiyun interrupts = <7>; 117*4882a593Smuzhiyun }; 118*4882a593Smuzhiyun }; 119*4882a593Smuzhiyun 120*4882a593Smuzhiyun leds { 121*4882a593Smuzhiyun compatible = "gpio-leds"; 122*4882a593Smuzhiyun pinctrl-names = "default"; 123*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_gpio_leds>; 124*4882a593Smuzhiyun 125*4882a593Smuzhiyun led0: user1 { 126*4882a593Smuzhiyun label = "user1"; 127*4882a593Smuzhiyun gpios = <&gpio4 6 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDG */ 128*4882a593Smuzhiyun default-state = "on"; 129*4882a593Smuzhiyun linux,default-trigger = "heartbeat"; 130*4882a593Smuzhiyun }; 131*4882a593Smuzhiyun 132*4882a593Smuzhiyun led1: user2 { 133*4882a593Smuzhiyun label = "user2"; 134*4882a593Smuzhiyun gpios = <&gpio4 7 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDR */ 135*4882a593Smuzhiyun default-state = "off"; 136*4882a593Smuzhiyun }; 137*4882a593Smuzhiyun 138*4882a593Smuzhiyun led2: user3 { 139*4882a593Smuzhiyun label = "user3"; 140*4882a593Smuzhiyun gpios = <&gpio4 15 GPIO_ACTIVE_LOW>; /* MX6_LOCLED# */ 141*4882a593Smuzhiyun default-state = "off"; 142*4882a593Smuzhiyun }; 143*4882a593Smuzhiyun }; 144*4882a593Smuzhiyun 145*4882a593Smuzhiyun memory@10000000 { 146*4882a593Smuzhiyun device_type = "memory"; 147*4882a593Smuzhiyun reg = <0x10000000 0x40000000>; 148*4882a593Smuzhiyun }; 149*4882a593Smuzhiyun 150*4882a593Smuzhiyun pps { 151*4882a593Smuzhiyun compatible = "pps-gpio"; 152*4882a593Smuzhiyun pinctrl-names = "default"; 153*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_pps>; 154*4882a593Smuzhiyun gpios = <&gpio1 26 GPIO_ACTIVE_HIGH>; 155*4882a593Smuzhiyun }; 156*4882a593Smuzhiyun 157*4882a593Smuzhiyun reg_1p0v: regulator-1p0v { 158*4882a593Smuzhiyun compatible = "regulator-fixed"; 159*4882a593Smuzhiyun regulator-name = "1P0V"; 160*4882a593Smuzhiyun regulator-min-microvolt = <1000000>; 161*4882a593Smuzhiyun regulator-max-microvolt = <1000000>; 162*4882a593Smuzhiyun regulator-always-on; 163*4882a593Smuzhiyun }; 164*4882a593Smuzhiyun 165*4882a593Smuzhiyun reg_3p3v: regulator-3p3v { 166*4882a593Smuzhiyun compatible = "regulator-fixed"; 167*4882a593Smuzhiyun regulator-name = "3P3V"; 168*4882a593Smuzhiyun regulator-min-microvolt = <3300000>; 169*4882a593Smuzhiyun regulator-max-microvolt = <3300000>; 170*4882a593Smuzhiyun regulator-always-on; 171*4882a593Smuzhiyun }; 172*4882a593Smuzhiyun 173*4882a593Smuzhiyun reg_usb_h1_vbus: regulator-usb-h1-vbus { 174*4882a593Smuzhiyun compatible = "regulator-fixed"; 175*4882a593Smuzhiyun regulator-name = "usb_h1_vbus"; 176*4882a593Smuzhiyun regulator-min-microvolt = <5000000>; 177*4882a593Smuzhiyun regulator-max-microvolt = <5000000>; 178*4882a593Smuzhiyun regulator-always-on; 179*4882a593Smuzhiyun }; 180*4882a593Smuzhiyun 181*4882a593Smuzhiyun reg_usb_otg_vbus: regulator-usb-otg-vbus { 182*4882a593Smuzhiyun compatible = "regulator-fixed"; 183*4882a593Smuzhiyun regulator-name = "usb_otg_vbus"; 184*4882a593Smuzhiyun regulator-min-microvolt = <5000000>; 185*4882a593Smuzhiyun regulator-max-microvolt = <5000000>; 186*4882a593Smuzhiyun gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>; 187*4882a593Smuzhiyun enable-active-high; 188*4882a593Smuzhiyun }; 189*4882a593Smuzhiyun}; 190*4882a593Smuzhiyun 191*4882a593Smuzhiyun&clks { 192*4882a593Smuzhiyun assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>, 193*4882a593Smuzhiyun <&clks IMX6QDL_CLK_LDB_DI1_SEL>; 194*4882a593Smuzhiyun assigned-clock-parents = <&clks IMX6QDL_CLK_PLL3_USB_OTG>, 195*4882a593Smuzhiyun <&clks IMX6QDL_CLK_PLL3_USB_OTG>; 196*4882a593Smuzhiyun}; 197*4882a593Smuzhiyun 198*4882a593Smuzhiyun&fec { 199*4882a593Smuzhiyun pinctrl-names = "default"; 200*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_enet>; 201*4882a593Smuzhiyun phy-mode = "rgmii-id"; 202*4882a593Smuzhiyun status = "okay"; 203*4882a593Smuzhiyun 204*4882a593Smuzhiyun fixed-link { 205*4882a593Smuzhiyun speed = <1000>; 206*4882a593Smuzhiyun full-duplex; 207*4882a593Smuzhiyun }; 208*4882a593Smuzhiyun 209*4882a593Smuzhiyun mdio { 210*4882a593Smuzhiyun #address-cells = <1>; 211*4882a593Smuzhiyun #size-cells = <0>; 212*4882a593Smuzhiyun 213*4882a593Smuzhiyun switch@0 { 214*4882a593Smuzhiyun compatible = "marvell,mv88e6085"; 215*4882a593Smuzhiyun reg = <0>; 216*4882a593Smuzhiyun 217*4882a593Smuzhiyun ports { 218*4882a593Smuzhiyun #address-cells = <1>; 219*4882a593Smuzhiyun #size-cells = <0>; 220*4882a593Smuzhiyun 221*4882a593Smuzhiyun port@0 { 222*4882a593Smuzhiyun reg = <0>; 223*4882a593Smuzhiyun label = "lan4"; 224*4882a593Smuzhiyun }; 225*4882a593Smuzhiyun 226*4882a593Smuzhiyun port@1 { 227*4882a593Smuzhiyun reg = <1>; 228*4882a593Smuzhiyun label = "lan3"; 229*4882a593Smuzhiyun }; 230*4882a593Smuzhiyun 231*4882a593Smuzhiyun port@2 { 232*4882a593Smuzhiyun reg = <2>; 233*4882a593Smuzhiyun label = "lan2"; 234*4882a593Smuzhiyun }; 235*4882a593Smuzhiyun 236*4882a593Smuzhiyun port@3 { 237*4882a593Smuzhiyun reg = <3>; 238*4882a593Smuzhiyun label = "lan1"; 239*4882a593Smuzhiyun }; 240*4882a593Smuzhiyun 241*4882a593Smuzhiyun port@5 { 242*4882a593Smuzhiyun reg = <5>; 243*4882a593Smuzhiyun label = "cpu"; 244*4882a593Smuzhiyun ethernet = <&fec>; 245*4882a593Smuzhiyun }; 246*4882a593Smuzhiyun }; 247*4882a593Smuzhiyun }; 248*4882a593Smuzhiyun }; 249*4882a593Smuzhiyun}; 250*4882a593Smuzhiyun 251*4882a593Smuzhiyun&i2c1 { 252*4882a593Smuzhiyun clock-frequency = <100000>; 253*4882a593Smuzhiyun pinctrl-names = "default"; 254*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_i2c1>; 255*4882a593Smuzhiyun status = "okay"; 256*4882a593Smuzhiyun 257*4882a593Smuzhiyun gsc: gsc@20 { 258*4882a593Smuzhiyun compatible = "gw,gsc"; 259*4882a593Smuzhiyun reg = <0x20>; 260*4882a593Smuzhiyun interrupt-parent = <&gpio1>; 261*4882a593Smuzhiyun interrupts = <4 IRQ_TYPE_LEVEL_LOW>; 262*4882a593Smuzhiyun interrupt-controller; 263*4882a593Smuzhiyun #interrupt-cells = <1>; 264*4882a593Smuzhiyun #size-cells = <0>; 265*4882a593Smuzhiyun 266*4882a593Smuzhiyun adc { 267*4882a593Smuzhiyun compatible = "gw,gsc-adc"; 268*4882a593Smuzhiyun #address-cells = <1>; 269*4882a593Smuzhiyun #size-cells = <0>; 270*4882a593Smuzhiyun 271*4882a593Smuzhiyun channel@0 { 272*4882a593Smuzhiyun gw,mode = <0>; 273*4882a593Smuzhiyun reg = <0x00>; 274*4882a593Smuzhiyun label = "temp"; 275*4882a593Smuzhiyun }; 276*4882a593Smuzhiyun 277*4882a593Smuzhiyun channel@2 { 278*4882a593Smuzhiyun gw,mode = <1>; 279*4882a593Smuzhiyun reg = <0x02>; 280*4882a593Smuzhiyun label = "vdd_vin"; 281*4882a593Smuzhiyun }; 282*4882a593Smuzhiyun 283*4882a593Smuzhiyun channel@5 { 284*4882a593Smuzhiyun gw,mode = <1>; 285*4882a593Smuzhiyun reg = <0x05>; 286*4882a593Smuzhiyun label = "vdd_3p3"; 287*4882a593Smuzhiyun }; 288*4882a593Smuzhiyun 289*4882a593Smuzhiyun channel@8 { 290*4882a593Smuzhiyun gw,mode = <1>; 291*4882a593Smuzhiyun reg = <0x08>; 292*4882a593Smuzhiyun label = "vdd_bat"; 293*4882a593Smuzhiyun }; 294*4882a593Smuzhiyun 295*4882a593Smuzhiyun channel@b { 296*4882a593Smuzhiyun gw,mode = <1>; 297*4882a593Smuzhiyun reg = <0x0b>; 298*4882a593Smuzhiyun label = "vdd_5p0"; 299*4882a593Smuzhiyun }; 300*4882a593Smuzhiyun 301*4882a593Smuzhiyun channel@e { 302*4882a593Smuzhiyun gw,mode = <1>; 303*4882a593Smuzhiyun reg = <0xe>; 304*4882a593Smuzhiyun label = "vdd_arm"; 305*4882a593Smuzhiyun }; 306*4882a593Smuzhiyun 307*4882a593Smuzhiyun channel@11 { 308*4882a593Smuzhiyun gw,mode = <1>; 309*4882a593Smuzhiyun reg = <0x11>; 310*4882a593Smuzhiyun label = "vdd_soc"; 311*4882a593Smuzhiyun }; 312*4882a593Smuzhiyun 313*4882a593Smuzhiyun channel@14 { 314*4882a593Smuzhiyun gw,mode = <1>; 315*4882a593Smuzhiyun reg = <0x14>; 316*4882a593Smuzhiyun label = "vdd_3p0"; 317*4882a593Smuzhiyun }; 318*4882a593Smuzhiyun 319*4882a593Smuzhiyun channel@17 { 320*4882a593Smuzhiyun gw,mode = <1>; 321*4882a593Smuzhiyun reg = <0x17>; 322*4882a593Smuzhiyun label = "vdd_1p5"; 323*4882a593Smuzhiyun }; 324*4882a593Smuzhiyun 325*4882a593Smuzhiyun channel@1d { 326*4882a593Smuzhiyun gw,mode = <1>; 327*4882a593Smuzhiyun reg = <0x1d>; 328*4882a593Smuzhiyun label = "vdd_1p8"; 329*4882a593Smuzhiyun }; 330*4882a593Smuzhiyun 331*4882a593Smuzhiyun channel@20 { 332*4882a593Smuzhiyun gw,mode = <1>; 333*4882a593Smuzhiyun reg = <0x20>; 334*4882a593Smuzhiyun label = "vdd_an1"; 335*4882a593Smuzhiyun }; 336*4882a593Smuzhiyun 337*4882a593Smuzhiyun channel@23 { 338*4882a593Smuzhiyun gw,mode = <1>; 339*4882a593Smuzhiyun reg = <0x23>; 340*4882a593Smuzhiyun label = "vdd_2p5"; 341*4882a593Smuzhiyun }; 342*4882a593Smuzhiyun }; 343*4882a593Smuzhiyun }; 344*4882a593Smuzhiyun 345*4882a593Smuzhiyun gsc_gpio: gpio@23 { 346*4882a593Smuzhiyun compatible = "nxp,pca9555"; 347*4882a593Smuzhiyun reg = <0x23>; 348*4882a593Smuzhiyun gpio-controller; 349*4882a593Smuzhiyun #gpio-cells = <2>; 350*4882a593Smuzhiyun interrupt-parent = <&gsc>; 351*4882a593Smuzhiyun interrupts = <4>; 352*4882a593Smuzhiyun }; 353*4882a593Smuzhiyun 354*4882a593Smuzhiyun eeprom1: eeprom@50 { 355*4882a593Smuzhiyun compatible = "atmel,24c02"; 356*4882a593Smuzhiyun reg = <0x50>; 357*4882a593Smuzhiyun pagesize = <16>; 358*4882a593Smuzhiyun }; 359*4882a593Smuzhiyun 360*4882a593Smuzhiyun eeprom2: eeprom@51 { 361*4882a593Smuzhiyun compatible = "atmel,24c02"; 362*4882a593Smuzhiyun reg = <0x51>; 363*4882a593Smuzhiyun pagesize = <16>; 364*4882a593Smuzhiyun }; 365*4882a593Smuzhiyun 366*4882a593Smuzhiyun eeprom3: eeprom@52 { 367*4882a593Smuzhiyun compatible = "atmel,24c02"; 368*4882a593Smuzhiyun reg = <0x52>; 369*4882a593Smuzhiyun pagesize = <16>; 370*4882a593Smuzhiyun }; 371*4882a593Smuzhiyun 372*4882a593Smuzhiyun eeprom4: eeprom@53 { 373*4882a593Smuzhiyun compatible = "atmel,24c02"; 374*4882a593Smuzhiyun reg = <0x53>; 375*4882a593Smuzhiyun pagesize = <16>; 376*4882a593Smuzhiyun }; 377*4882a593Smuzhiyun 378*4882a593Smuzhiyun dts1672: rtc@68 { 379*4882a593Smuzhiyun compatible = "dallas,ds1672"; 380*4882a593Smuzhiyun reg = <0x68>; 381*4882a593Smuzhiyun }; 382*4882a593Smuzhiyun}; 383*4882a593Smuzhiyun 384*4882a593Smuzhiyun&i2c2 { 385*4882a593Smuzhiyun clock-frequency = <100000>; 386*4882a593Smuzhiyun pinctrl-names = "default"; 387*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_i2c2>; 388*4882a593Smuzhiyun status = "okay"; 389*4882a593Smuzhiyun 390*4882a593Smuzhiyun magn@1c { 391*4882a593Smuzhiyun compatible = "st,lsm9ds1-magn"; 392*4882a593Smuzhiyun reg = <0x1c>; 393*4882a593Smuzhiyun pinctrl-names = "default"; 394*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_mag>; 395*4882a593Smuzhiyun interrupt-parent = <&gpio5>; 396*4882a593Smuzhiyun interrupts = <17 IRQ_TYPE_EDGE_RISING>; 397*4882a593Smuzhiyun }; 398*4882a593Smuzhiyun 399*4882a593Smuzhiyun ltc3676: pmic@3c { 400*4882a593Smuzhiyun compatible = "lltc,ltc3676"; 401*4882a593Smuzhiyun reg = <0x3c>; 402*4882a593Smuzhiyun interrupt-parent = <&gpio1>; 403*4882a593Smuzhiyun interrupts = <8 IRQ_TYPE_EDGE_FALLING>; 404*4882a593Smuzhiyun 405*4882a593Smuzhiyun regulators { 406*4882a593Smuzhiyun /* VDD_SOC (1+R1/R2 = 1.635) */ 407*4882a593Smuzhiyun reg_vdd_soc: sw1 { 408*4882a593Smuzhiyun regulator-name = "vddsoc"; 409*4882a593Smuzhiyun regulator-min-microvolt = <674400>; 410*4882a593Smuzhiyun regulator-max-microvolt = <1308000>; 411*4882a593Smuzhiyun lltc,fb-voltage-divider = <127000 200000>; 412*4882a593Smuzhiyun regulator-ramp-delay = <7000>; 413*4882a593Smuzhiyun regulator-boot-on; 414*4882a593Smuzhiyun regulator-always-on; 415*4882a593Smuzhiyun }; 416*4882a593Smuzhiyun 417*4882a593Smuzhiyun /* VDD_1P8 (1+R1/R2 = 2.505): GbE switch */ 418*4882a593Smuzhiyun reg_1p8v: sw2 { 419*4882a593Smuzhiyun regulator-name = "vdd1p8"; 420*4882a593Smuzhiyun regulator-min-microvolt = <1033310>; 421*4882a593Smuzhiyun regulator-max-microvolt = <2004000>; 422*4882a593Smuzhiyun lltc,fb-voltage-divider = <301000 200000>; 423*4882a593Smuzhiyun regulator-ramp-delay = <7000>; 424*4882a593Smuzhiyun regulator-boot-on; 425*4882a593Smuzhiyun regulator-always-on; 426*4882a593Smuzhiyun }; 427*4882a593Smuzhiyun 428*4882a593Smuzhiyun /* VDD_ARM (1+R1/R2 = 1.635) */ 429*4882a593Smuzhiyun reg_vdd_arm: sw3 { 430*4882a593Smuzhiyun regulator-name = "vddarm"; 431*4882a593Smuzhiyun regulator-min-microvolt = <674400>; 432*4882a593Smuzhiyun regulator-max-microvolt = <1308000>; 433*4882a593Smuzhiyun lltc,fb-voltage-divider = <127000 200000>; 434*4882a593Smuzhiyun regulator-ramp-delay = <7000>; 435*4882a593Smuzhiyun regulator-boot-on; 436*4882a593Smuzhiyun regulator-always-on; 437*4882a593Smuzhiyun }; 438*4882a593Smuzhiyun 439*4882a593Smuzhiyun /* VDD_DDR (1+R1/R2 = 2.105) */ 440*4882a593Smuzhiyun reg_vdd_ddr: sw4 { 441*4882a593Smuzhiyun regulator-name = "vddddr"; 442*4882a593Smuzhiyun regulator-min-microvolt = <868310>; 443*4882a593Smuzhiyun regulator-max-microvolt = <1684000>; 444*4882a593Smuzhiyun lltc,fb-voltage-divider = <221000 200000>; 445*4882a593Smuzhiyun regulator-ramp-delay = <7000>; 446*4882a593Smuzhiyun regulator-boot-on; 447*4882a593Smuzhiyun regulator-always-on; 448*4882a593Smuzhiyun }; 449*4882a593Smuzhiyun 450*4882a593Smuzhiyun /* VDD_2P5 (1+R1/R2 = 3.435): PCIe/ENET-PHY */ 451*4882a593Smuzhiyun reg_2p5v: ldo2 { 452*4882a593Smuzhiyun regulator-name = "vdd2p5"; 453*4882a593Smuzhiyun regulator-min-microvolt = <2490375>; 454*4882a593Smuzhiyun regulator-max-microvolt = <2490375>; 455*4882a593Smuzhiyun lltc,fb-voltage-divider = <487000 200000>; 456*4882a593Smuzhiyun regulator-boot-on; 457*4882a593Smuzhiyun regulator-always-on; 458*4882a593Smuzhiyun }; 459*4882a593Smuzhiyun 460*4882a593Smuzhiyun /* VDD_HIGH (1+R1/R2 = 4.17) */ 461*4882a593Smuzhiyun reg_3p0v: ldo4 { 462*4882a593Smuzhiyun regulator-name = "vdd3p0"; 463*4882a593Smuzhiyun regulator-min-microvolt = <3023250>; 464*4882a593Smuzhiyun regulator-max-microvolt = <3023250>; 465*4882a593Smuzhiyun lltc,fb-voltage-divider = <634000 200000>; 466*4882a593Smuzhiyun regulator-boot-on; 467*4882a593Smuzhiyun regulator-always-on; 468*4882a593Smuzhiyun }; 469*4882a593Smuzhiyun }; 470*4882a593Smuzhiyun }; 471*4882a593Smuzhiyun 472*4882a593Smuzhiyun imu@6a { 473*4882a593Smuzhiyun compatible = "st,lsm9ds1-imu"; 474*4882a593Smuzhiyun reg = <0x6a>; 475*4882a593Smuzhiyun st,drdy-int-pin = <1>; 476*4882a593Smuzhiyun pinctrl-names = "default"; 477*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_imu>; 478*4882a593Smuzhiyun interrupt-parent = <&gpio4>; 479*4882a593Smuzhiyun interrupts = <18 IRQ_TYPE_LEVEL_HIGH>; 480*4882a593Smuzhiyun }; 481*4882a593Smuzhiyun}; 482*4882a593Smuzhiyun 483*4882a593Smuzhiyun&i2c3 { 484*4882a593Smuzhiyun clock-frequency = <100000>; 485*4882a593Smuzhiyun pinctrl-names = "default"; 486*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_i2c3>; 487*4882a593Smuzhiyun status = "okay"; 488*4882a593Smuzhiyun 489*4882a593Smuzhiyun egalax_ts: touchscreen@4 { 490*4882a593Smuzhiyun compatible = "eeti,egalax_ts"; 491*4882a593Smuzhiyun reg = <0x04>; 492*4882a593Smuzhiyun interrupt-parent = <&gpio1>; 493*4882a593Smuzhiyun interrupts = <11 IRQ_TYPE_EDGE_FALLING>; 494*4882a593Smuzhiyun wakeup-gpios = <&gpio1 11 GPIO_ACTIVE_LOW>; 495*4882a593Smuzhiyun }; 496*4882a593Smuzhiyun}; 497*4882a593Smuzhiyun 498*4882a593Smuzhiyun&ldb { 499*4882a593Smuzhiyun status = "okay"; 500*4882a593Smuzhiyun 501*4882a593Smuzhiyun lvds-channel@0 { 502*4882a593Smuzhiyun fsl,data-mapping = "spwg"; 503*4882a593Smuzhiyun fsl,data-width = <18>; 504*4882a593Smuzhiyun status = "okay"; 505*4882a593Smuzhiyun 506*4882a593Smuzhiyun display-timings { 507*4882a593Smuzhiyun native-mode = <&timing0>; 508*4882a593Smuzhiyun timing0: hsd100pxn1 { 509*4882a593Smuzhiyun clock-frequency = <65000000>; 510*4882a593Smuzhiyun hactive = <1024>; 511*4882a593Smuzhiyun vactive = <768>; 512*4882a593Smuzhiyun hback-porch = <220>; 513*4882a593Smuzhiyun hfront-porch = <40>; 514*4882a593Smuzhiyun vback-porch = <21>; 515*4882a593Smuzhiyun vfront-porch = <7>; 516*4882a593Smuzhiyun hsync-len = <60>; 517*4882a593Smuzhiyun vsync-len = <10>; 518*4882a593Smuzhiyun }; 519*4882a593Smuzhiyun }; 520*4882a593Smuzhiyun }; 521*4882a593Smuzhiyun}; 522*4882a593Smuzhiyun 523*4882a593Smuzhiyun&pcie { 524*4882a593Smuzhiyun pinctrl-names = "default"; 525*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_pcie>; 526*4882a593Smuzhiyun reset-gpio = <&gpio1 0 GPIO_ACTIVE_LOW>; 527*4882a593Smuzhiyun status = "okay"; 528*4882a593Smuzhiyun}; 529*4882a593Smuzhiyun 530*4882a593Smuzhiyun&pwm2 { 531*4882a593Smuzhiyun pinctrl-names = "default"; 532*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_pwm2>; /* MX6_DIO1 */ 533*4882a593Smuzhiyun status = "disabled"; 534*4882a593Smuzhiyun}; 535*4882a593Smuzhiyun 536*4882a593Smuzhiyun&pwm3 { 537*4882a593Smuzhiyun pinctrl-names = "default"; 538*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_pwm3>; /* MX6_DIO2 */ 539*4882a593Smuzhiyun status = "disabled"; 540*4882a593Smuzhiyun}; 541*4882a593Smuzhiyun 542*4882a593Smuzhiyun&pwm4 { 543*4882a593Smuzhiyun #pwm-cells = <2>; 544*4882a593Smuzhiyun pinctrl-names = "default"; 545*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_pwm4>; 546*4882a593Smuzhiyun status = "okay"; 547*4882a593Smuzhiyun}; 548*4882a593Smuzhiyun 549*4882a593Smuzhiyun&uart1 { 550*4882a593Smuzhiyun pinctrl-names = "default"; 551*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_uart1>; 552*4882a593Smuzhiyun status = "okay"; 553*4882a593Smuzhiyun}; 554*4882a593Smuzhiyun 555*4882a593Smuzhiyun&uart2 { 556*4882a593Smuzhiyun pinctrl-names = "default"; 557*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_uart2>; 558*4882a593Smuzhiyun status = "okay"; 559*4882a593Smuzhiyun}; 560*4882a593Smuzhiyun 561*4882a593Smuzhiyun&uart3 { 562*4882a593Smuzhiyun pinctrl-names = "default"; 563*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_uart3>; 564*4882a593Smuzhiyun uart-has-rtscts; 565*4882a593Smuzhiyun status = "okay"; 566*4882a593Smuzhiyun}; 567*4882a593Smuzhiyun 568*4882a593Smuzhiyun&uart4 { 569*4882a593Smuzhiyun pinctrl-names = "default"; 570*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_uart4>; 571*4882a593Smuzhiyun uart-has-rtscts; 572*4882a593Smuzhiyun status = "okay"; 573*4882a593Smuzhiyun}; 574*4882a593Smuzhiyun 575*4882a593Smuzhiyun&uart5 { 576*4882a593Smuzhiyun pinctrl-names = "default"; 577*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_uart5>; 578*4882a593Smuzhiyun status = "okay"; 579*4882a593Smuzhiyun}; 580*4882a593Smuzhiyun 581*4882a593Smuzhiyun&usbotg { 582*4882a593Smuzhiyun vbus-supply = <®_usb_otg_vbus>; 583*4882a593Smuzhiyun pinctrl-names = "default"; 584*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_usbotg>; 585*4882a593Smuzhiyun disable-over-current; 586*4882a593Smuzhiyun status = "okay"; 587*4882a593Smuzhiyun}; 588*4882a593Smuzhiyun 589*4882a593Smuzhiyun&usbh1 { 590*4882a593Smuzhiyun vbus-supply = <®_usb_h1_vbus>; 591*4882a593Smuzhiyun status = "okay"; 592*4882a593Smuzhiyun}; 593*4882a593Smuzhiyun 594*4882a593Smuzhiyun&usdhc3 { 595*4882a593Smuzhiyun pinctrl-names = "default", "state_100mhz", "state_200mhz"; 596*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_usdhc3>; 597*4882a593Smuzhiyun pinctrl-1 = <&pinctrl_usdhc3_100mhz>; 598*4882a593Smuzhiyun pinctrl-2 = <&pinctrl_usdhc3_200mhz>; 599*4882a593Smuzhiyun non-removable; 600*4882a593Smuzhiyun vmmc-supply = <®_3p3v>; 601*4882a593Smuzhiyun keep-power-in-suspend; 602*4882a593Smuzhiyun status = "okay"; 603*4882a593Smuzhiyun}; 604*4882a593Smuzhiyun 605*4882a593Smuzhiyun&wdog1 { 606*4882a593Smuzhiyun pinctrl-names = "default"; 607*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_wdog>; 608*4882a593Smuzhiyun fsl,ext-reset-output; 609*4882a593Smuzhiyun}; 610*4882a593Smuzhiyun 611*4882a593Smuzhiyun&iomuxc { 612*4882a593Smuzhiyun pinctrl_enet: enetgrp { 613*4882a593Smuzhiyun fsl,pins = < 614*4882a593Smuzhiyun MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030 615*4882a593Smuzhiyun MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030 616*4882a593Smuzhiyun MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030 617*4882a593Smuzhiyun MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030 618*4882a593Smuzhiyun MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030 619*4882a593Smuzhiyun MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030 620*4882a593Smuzhiyun MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030 621*4882a593Smuzhiyun MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030 622*4882a593Smuzhiyun MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030 623*4882a593Smuzhiyun MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030 624*4882a593Smuzhiyun MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030 625*4882a593Smuzhiyun MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030 626*4882a593Smuzhiyun MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 627*4882a593Smuzhiyun MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 628*4882a593Smuzhiyun MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 629*4882a593Smuzhiyun MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8 630*4882a593Smuzhiyun MX6QDL_PAD_ENET_TXD0__GPIO1_IO30 0x4001b0b0 /* PHY_RST# */ 631*4882a593Smuzhiyun >; 632*4882a593Smuzhiyun }; 633*4882a593Smuzhiyun 634*4882a593Smuzhiyun pinctrl_gpio_leds: gpioledsgrp { 635*4882a593Smuzhiyun fsl,pins = < 636*4882a593Smuzhiyun MX6QDL_PAD_KEY_COL0__GPIO4_IO06 0x1b0b0 637*4882a593Smuzhiyun MX6QDL_PAD_KEY_ROW0__GPIO4_IO07 0x1b0b0 638*4882a593Smuzhiyun MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x1b0b0 639*4882a593Smuzhiyun >; 640*4882a593Smuzhiyun }; 641*4882a593Smuzhiyun 642*4882a593Smuzhiyun pinctrl_i2c1: i2c1grp { 643*4882a593Smuzhiyun fsl,pins = < 644*4882a593Smuzhiyun MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1 645*4882a593Smuzhiyun MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1 646*4882a593Smuzhiyun MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x0001b0b0 /* GSC_IRQ# */ 647*4882a593Smuzhiyun >; 648*4882a593Smuzhiyun }; 649*4882a593Smuzhiyun 650*4882a593Smuzhiyun pinctrl_i2c2: i2c2grp { 651*4882a593Smuzhiyun fsl,pins = < 652*4882a593Smuzhiyun MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 653*4882a593Smuzhiyun MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 654*4882a593Smuzhiyun >; 655*4882a593Smuzhiyun }; 656*4882a593Smuzhiyun 657*4882a593Smuzhiyun pinctrl_i2c3: i2c3grp { 658*4882a593Smuzhiyun fsl,pins = < 659*4882a593Smuzhiyun MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1 660*4882a593Smuzhiyun MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1 661*4882a593Smuzhiyun >; 662*4882a593Smuzhiyun }; 663*4882a593Smuzhiyun 664*4882a593Smuzhiyun pinctrl_imu: imugrp { 665*4882a593Smuzhiyun fsl,pins = < 666*4882a593Smuzhiyun MX6QDL_PAD_DI0_PIN2__GPIO4_IO18 0x1b0b0 667*4882a593Smuzhiyun >; 668*4882a593Smuzhiyun }; 669*4882a593Smuzhiyun 670*4882a593Smuzhiyun pinctrl_mag: maggrp { 671*4882a593Smuzhiyun fsl,pins = < 672*4882a593Smuzhiyun MX6QDL_PAD_DISP0_DAT23__GPIO5_IO17 0x1b0b0 673*4882a593Smuzhiyun >; 674*4882a593Smuzhiyun }; 675*4882a593Smuzhiyun 676*4882a593Smuzhiyun pinctrl_pcie: pciegrp { 677*4882a593Smuzhiyun fsl,pins = < 678*4882a593Smuzhiyun MX6QDL_PAD_GPIO_0__GPIO1_IO00 0x1b0b0 /* PCIE RST */ 679*4882a593Smuzhiyun >; 680*4882a593Smuzhiyun }; 681*4882a593Smuzhiyun 682*4882a593Smuzhiyun pinctrl_pmic: pmicgrp { 683*4882a593Smuzhiyun fsl,pins = < 684*4882a593Smuzhiyun MX6QDL_PAD_GPIO_8__GPIO1_IO08 0x1b0b0 /* PMIC_IRQ# */ 685*4882a593Smuzhiyun >; 686*4882a593Smuzhiyun }; 687*4882a593Smuzhiyun 688*4882a593Smuzhiyun pinctrl_pps: ppsgrp { 689*4882a593Smuzhiyun fsl,pins = < 690*4882a593Smuzhiyun MX6QDL_PAD_ENET_RXD1__GPIO1_IO26 0x1b0b1 691*4882a593Smuzhiyun >; 692*4882a593Smuzhiyun }; 693*4882a593Smuzhiyun 694*4882a593Smuzhiyun pinctrl_pwm2: pwm2grp { 695*4882a593Smuzhiyun fsl,pins = < 696*4882a593Smuzhiyun MX6QDL_PAD_SD1_DAT2__PWM2_OUT 0x1b0b1 697*4882a593Smuzhiyun >; 698*4882a593Smuzhiyun }; 699*4882a593Smuzhiyun 700*4882a593Smuzhiyun pinctrl_pwm3: pwm3grp { 701*4882a593Smuzhiyun fsl,pins = < 702*4882a593Smuzhiyun MX6QDL_PAD_SD1_DAT1__PWM3_OUT 0x1b0b1 703*4882a593Smuzhiyun >; 704*4882a593Smuzhiyun }; 705*4882a593Smuzhiyun 706*4882a593Smuzhiyun pinctrl_pwm4: pwm4grp { 707*4882a593Smuzhiyun fsl,pins = < 708*4882a593Smuzhiyun MX6QDL_PAD_SD1_CMD__PWM4_OUT 0x1b0b1 709*4882a593Smuzhiyun >; 710*4882a593Smuzhiyun }; 711*4882a593Smuzhiyun 712*4882a593Smuzhiyun pinctrl_uart1: uart1grp { 713*4882a593Smuzhiyun fsl,pins = < 714*4882a593Smuzhiyun MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1 715*4882a593Smuzhiyun MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1 716*4882a593Smuzhiyun >; 717*4882a593Smuzhiyun }; 718*4882a593Smuzhiyun 719*4882a593Smuzhiyun pinctrl_uart2: uart2grp { 720*4882a593Smuzhiyun fsl,pins = < 721*4882a593Smuzhiyun MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b1 722*4882a593Smuzhiyun MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b1 723*4882a593Smuzhiyun >; 724*4882a593Smuzhiyun }; 725*4882a593Smuzhiyun 726*4882a593Smuzhiyun pinctrl_uart3: uart3grp { 727*4882a593Smuzhiyun fsl,pins = < 728*4882a593Smuzhiyun MX6QDL_PAD_EIM_D23__UART3_CTS_B 0x1b0b1 729*4882a593Smuzhiyun MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1 730*4882a593Smuzhiyun MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1 731*4882a593Smuzhiyun MX6QDL_PAD_EIM_D31__UART3_RTS_B 0x1b0b1 732*4882a593Smuzhiyun >; 733*4882a593Smuzhiyun }; 734*4882a593Smuzhiyun 735*4882a593Smuzhiyun pinctrl_uart4: uart4grp { 736*4882a593Smuzhiyun fsl,pins = < 737*4882a593Smuzhiyun MX6QDL_PAD_CSI0_DAT12__UART4_TX_DATA 0x1b0b1 738*4882a593Smuzhiyun MX6QDL_PAD_CSI0_DAT13__UART4_RX_DATA 0x1b0b1 739*4882a593Smuzhiyun MX6QDL_PAD_CSI0_DAT16__UART4_RTS_B 0x1b0b1 740*4882a593Smuzhiyun MX6QDL_PAD_CSI0_DAT17__UART4_CTS_B 0x1b0b1 741*4882a593Smuzhiyun >; 742*4882a593Smuzhiyun }; 743*4882a593Smuzhiyun 744*4882a593Smuzhiyun pinctrl_uart5: uart5grp { 745*4882a593Smuzhiyun fsl,pins = < 746*4882a593Smuzhiyun MX6QDL_PAD_KEY_COL1__UART5_TX_DATA 0x1b0b1 747*4882a593Smuzhiyun MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x1b0b1 748*4882a593Smuzhiyun >; 749*4882a593Smuzhiyun }; 750*4882a593Smuzhiyun 751*4882a593Smuzhiyun pinctrl_usbotg: usbotggrp { 752*4882a593Smuzhiyun fsl,pins = < 753*4882a593Smuzhiyun MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059 754*4882a593Smuzhiyun MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x1b0b0 /* PWR_EN */ 755*4882a593Smuzhiyun MX6QDL_PAD_KEY_COL4__GPIO4_IO14 0x1b0b0 /* OC */ 756*4882a593Smuzhiyun >; 757*4882a593Smuzhiyun }; 758*4882a593Smuzhiyun 759*4882a593Smuzhiyun pinctrl_usdhc3: usdhc3grp { 760*4882a593Smuzhiyun fsl,pins = < 761*4882a593Smuzhiyun MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 762*4882a593Smuzhiyun MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 763*4882a593Smuzhiyun MX6QDL_PAD_SD3_RST__SD3_RESET 0x10059 764*4882a593Smuzhiyun MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 765*4882a593Smuzhiyun MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 766*4882a593Smuzhiyun MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 767*4882a593Smuzhiyun MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 768*4882a593Smuzhiyun MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x17059 769*4882a593Smuzhiyun MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x17059 770*4882a593Smuzhiyun MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x17059 771*4882a593Smuzhiyun MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x17059 772*4882a593Smuzhiyun >; 773*4882a593Smuzhiyun }; 774*4882a593Smuzhiyun 775*4882a593Smuzhiyun pinctrl_usdhc3_100mhz: usdhc3grp100mhz { 776*4882a593Smuzhiyun fsl,pins = < 777*4882a593Smuzhiyun MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170b9 778*4882a593Smuzhiyun MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100b9 779*4882a593Smuzhiyun MX6QDL_PAD_SD3_RST__SD3_RESET 0x100b9 780*4882a593Smuzhiyun MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170b9 781*4882a593Smuzhiyun MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170b9 782*4882a593Smuzhiyun MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170b9 783*4882a593Smuzhiyun MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170b9 784*4882a593Smuzhiyun MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x170b9 785*4882a593Smuzhiyun MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x170b9 786*4882a593Smuzhiyun MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x170b9 787*4882a593Smuzhiyun MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x170b9 788*4882a593Smuzhiyun >; 789*4882a593Smuzhiyun }; 790*4882a593Smuzhiyun 791*4882a593Smuzhiyun pinctrl_usdhc3_200mhz: usdhc3grp200mhz { 792*4882a593Smuzhiyun fsl,pins = < 793*4882a593Smuzhiyun MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170f9 794*4882a593Smuzhiyun MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100f9 795*4882a593Smuzhiyun MX6QDL_PAD_SD3_RST__SD3_RESET 0x100f9 796*4882a593Smuzhiyun MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170f9 797*4882a593Smuzhiyun MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170f9 798*4882a593Smuzhiyun MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170f9 799*4882a593Smuzhiyun MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170f9 800*4882a593Smuzhiyun MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x170f9 801*4882a593Smuzhiyun MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x170f9 802*4882a593Smuzhiyun MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x170f9 803*4882a593Smuzhiyun MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x170f9 804*4882a593Smuzhiyun >; 805*4882a593Smuzhiyun }; 806*4882a593Smuzhiyun 807*4882a593Smuzhiyun pinctrl_wdog: wdoggrp { 808*4882a593Smuzhiyun fsl,pins = < 809*4882a593Smuzhiyun MX6QDL_PAD_DISP0_DAT8__WDOG1_B 0x1b0b0 810*4882a593Smuzhiyun >; 811*4882a593Smuzhiyun }; 812*4882a593Smuzhiyun}; 813