xref: /OK3568_Linux_fs/kernel/scripts/dtc/include-prefixes/arm/imx6q-prti6q.dts (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
2*4882a593Smuzhiyun/*
3*4882a593Smuzhiyun * Copyright (c) 2014 Protonic Holland
4*4882a593Smuzhiyun */
5*4882a593Smuzhiyun
6*4882a593Smuzhiyun/dts-v1/;
7*4882a593Smuzhiyun#include "imx6q.dtsi"
8*4882a593Smuzhiyun#include "imx6qdl-prti6q.dtsi"
9*4882a593Smuzhiyun#include <dt-bindings/leds/common.h>
10*4882a593Smuzhiyun#include <dt-bindings/sound/fsl-imx-audmux.h>
11*4882a593Smuzhiyun
12*4882a593Smuzhiyun/ {
13*4882a593Smuzhiyun	model = "Protonic PRTI6Q board";
14*4882a593Smuzhiyun	compatible = "prt,prti6q", "fsl,imx6q";
15*4882a593Smuzhiyun
16*4882a593Smuzhiyun	memory@10000000 {
17*4882a593Smuzhiyun		device_type = "memory";
18*4882a593Smuzhiyun		reg = <0x10000000 0xf0000000>;
19*4882a593Smuzhiyun	};
20*4882a593Smuzhiyun
21*4882a593Smuzhiyun	backlight_lcd: backlight-lcd {
22*4882a593Smuzhiyun		compatible = "pwm-backlight";
23*4882a593Smuzhiyun		pinctrl-names = "default";
24*4882a593Smuzhiyun		pinctrl-0 = <&pinctrl_backlight>;
25*4882a593Smuzhiyun		pwms = <&pwm1 0 5000000>;
26*4882a593Smuzhiyun		brightness-levels = <0 16 64 255>;
27*4882a593Smuzhiyun		num-interpolated-steps = <16>;
28*4882a593Smuzhiyun		default-brightness-level = <1>;
29*4882a593Smuzhiyun		power-supply = <&reg_3v3>;
30*4882a593Smuzhiyun		enable-gpios = <&gpio4 28 GPIO_ACTIVE_HIGH>;
31*4882a593Smuzhiyun	};
32*4882a593Smuzhiyun
33*4882a593Smuzhiyun	can_osc: can-osc {
34*4882a593Smuzhiyun		compatible = "fixed-clock";
35*4882a593Smuzhiyun		#clock-cells = <0>;
36*4882a593Smuzhiyun		clock-frequency = <25000000>;
37*4882a593Smuzhiyun	};
38*4882a593Smuzhiyun
39*4882a593Smuzhiyun	leds {
40*4882a593Smuzhiyun		compatible = "gpio-leds";
41*4882a593Smuzhiyun		pinctrl-names = "default";
42*4882a593Smuzhiyun		pinctrl-0 = <&pinctrl_leds>;
43*4882a593Smuzhiyun
44*4882a593Smuzhiyun		led-debug0 {
45*4882a593Smuzhiyun			function = LED_FUNCTION_STATUS;
46*4882a593Smuzhiyun			gpios = <&gpio1 8 GPIO_ACTIVE_HIGH>;
47*4882a593Smuzhiyun			linux,default-trigger = "heartbeat";
48*4882a593Smuzhiyun		};
49*4882a593Smuzhiyun
50*4882a593Smuzhiyun		led-debug1 {
51*4882a593Smuzhiyun			function = LED_FUNCTION_SD;
52*4882a593Smuzhiyun			gpios = <&gpio1 9 GPIO_ACTIVE_HIGH>;
53*4882a593Smuzhiyun			linux,default-trigger = "disk-activity";
54*4882a593Smuzhiyun		};
55*4882a593Smuzhiyun	};
56*4882a593Smuzhiyun
57*4882a593Smuzhiyun	panel {
58*4882a593Smuzhiyun		compatible = "kyo,tcg121xglp";
59*4882a593Smuzhiyun		backlight = <&backlight_lcd>;
60*4882a593Smuzhiyun
61*4882a593Smuzhiyun		port {
62*4882a593Smuzhiyun			panel_in: endpoint {
63*4882a593Smuzhiyun				remote-endpoint = <&lvds0_out>;
64*4882a593Smuzhiyun			};
65*4882a593Smuzhiyun		};
66*4882a593Smuzhiyun	};
67*4882a593Smuzhiyun
68*4882a593Smuzhiyun	reg_1v8: regulator-1v8 {
69*4882a593Smuzhiyun		compatible = "regulator-fixed";
70*4882a593Smuzhiyun		regulator-name = "1v8";
71*4882a593Smuzhiyun		regulator-min-microvolt = <1800000>;
72*4882a593Smuzhiyun		regulator-max-microvolt = <1800000>;
73*4882a593Smuzhiyun	};
74*4882a593Smuzhiyun
75*4882a593Smuzhiyun	reg_wifi: regulator-wifi {
76*4882a593Smuzhiyun		compatible = "regulator-fixed";
77*4882a593Smuzhiyun		pinctrl-names = "default";
78*4882a593Smuzhiyun		pinctrl-0 = <&pinctrl_wifi_npd>;
79*4882a593Smuzhiyun		enable-active-high;
80*4882a593Smuzhiyun		gpio = <&gpio1 26 GPIO_ACTIVE_HIGH>;
81*4882a593Smuzhiyun		regulator-max-microvolt = <1800000>;
82*4882a593Smuzhiyun		regulator-min-microvolt = <1800000>;
83*4882a593Smuzhiyun		regulator-name = "regulator-WL12xx";
84*4882a593Smuzhiyun		startup-delay-us = <70000>;
85*4882a593Smuzhiyun	};
86*4882a593Smuzhiyun
87*4882a593Smuzhiyun	sound {
88*4882a593Smuzhiyun		compatible = "simple-audio-card";
89*4882a593Smuzhiyun		simple-audio-card,name = "prti6q-sgtl5000";
90*4882a593Smuzhiyun		simple-audio-card,format = "i2s";
91*4882a593Smuzhiyun		simple-audio-card,widgets =
92*4882a593Smuzhiyun			"Microphone", "Microphone Jack",
93*4882a593Smuzhiyun			"Line", "Line In Jack",
94*4882a593Smuzhiyun			"Headphone", "Headphone Jack",
95*4882a593Smuzhiyun			"Speaker", "External Speaker";
96*4882a593Smuzhiyun		simple-audio-card,routing =
97*4882a593Smuzhiyun			"MIC_IN", "Microphone Jack",
98*4882a593Smuzhiyun			"LINE_IN", "Line In Jack",
99*4882a593Smuzhiyun			"Headphone Jack", "HP_OUT",
100*4882a593Smuzhiyun			"External Speaker", "LINE_OUT";
101*4882a593Smuzhiyun
102*4882a593Smuzhiyun		simple-audio-card,cpu {
103*4882a593Smuzhiyun			sound-dai = <&ssi1>;
104*4882a593Smuzhiyun			system-clock-frequency = <0>;
105*4882a593Smuzhiyun		};
106*4882a593Smuzhiyun
107*4882a593Smuzhiyun		simple-audio-card,codec {
108*4882a593Smuzhiyun			sound-dai = <&sgtl5000>;
109*4882a593Smuzhiyun			bitclock-master;
110*4882a593Smuzhiyun			frame-master;
111*4882a593Smuzhiyun		};
112*4882a593Smuzhiyun	};
113*4882a593Smuzhiyun
114*4882a593Smuzhiyun	sound-spdif {
115*4882a593Smuzhiyun		compatible = "fsl,imx-audio-spdif";
116*4882a593Smuzhiyun		model = "imx-spdif";
117*4882a593Smuzhiyun		spdif-controller = <&spdif>;
118*4882a593Smuzhiyun		spdif-in;
119*4882a593Smuzhiyun		spdif-out;
120*4882a593Smuzhiyun	};
121*4882a593Smuzhiyun};
122*4882a593Smuzhiyun
123*4882a593Smuzhiyun&audmux {
124*4882a593Smuzhiyun	pinctrl-names = "default";
125*4882a593Smuzhiyun	pinctrl-0 = <&pinctrl_audmux>;
126*4882a593Smuzhiyun	status = "okay";
127*4882a593Smuzhiyun
128*4882a593Smuzhiyun	mux-ssi1 {
129*4882a593Smuzhiyun		fsl,audmux-port = <0>;
130*4882a593Smuzhiyun		fsl,port-config = <
131*4882a593Smuzhiyun			IMX_AUDMUX_V2_PTCR_SYN		0
132*4882a593Smuzhiyun			IMX_AUDMUX_V2_PTCR_TFSEL(2)	0
133*4882a593Smuzhiyun			IMX_AUDMUX_V2_PTCR_TCSEL(2)	0
134*4882a593Smuzhiyun			IMX_AUDMUX_V2_PTCR_TFSDIR	0
135*4882a593Smuzhiyun			IMX_AUDMUX_V2_PTCR_TCLKDIR IMX_AUDMUX_V2_PDCR_RXDSEL(2)
136*4882a593Smuzhiyun		>;
137*4882a593Smuzhiyun	};
138*4882a593Smuzhiyun
139*4882a593Smuzhiyun	mux-pins3 {
140*4882a593Smuzhiyun		fsl,audmux-port = <2>;
141*4882a593Smuzhiyun		fsl,port-config = <
142*4882a593Smuzhiyun			IMX_AUDMUX_V2_PTCR_SYN IMX_AUDMUX_V2_PDCR_RXDSEL(0)
143*4882a593Smuzhiyun			0		       IMX_AUDMUX_V2_PDCR_TXRXEN
144*4882a593Smuzhiyun		>;
145*4882a593Smuzhiyun	};
146*4882a593Smuzhiyun};
147*4882a593Smuzhiyun
148*4882a593Smuzhiyun&can1 {
149*4882a593Smuzhiyun	pinctrl-names = "default";
150*4882a593Smuzhiyun	pinctrl-0 = <&pinctrl_can1>;
151*4882a593Smuzhiyun	status = "okay";
152*4882a593Smuzhiyun};
153*4882a593Smuzhiyun
154*4882a593Smuzhiyun&can2 {
155*4882a593Smuzhiyun	pinctrl-names = "default";
156*4882a593Smuzhiyun	pinctrl-0 = <&pinctrl_can2>;
157*4882a593Smuzhiyun	status = "okay";
158*4882a593Smuzhiyun};
159*4882a593Smuzhiyun
160*4882a593Smuzhiyun&ecspi1 {
161*4882a593Smuzhiyun	cs-gpios = <&gpio3 19 GPIO_ACTIVE_LOW>;
162*4882a593Smuzhiyun	pinctrl-names = "default";
163*4882a593Smuzhiyun	pinctrl-0 = <&pinctrl_ecspi1>;
164*4882a593Smuzhiyun	status = "okay";
165*4882a593Smuzhiyun
166*4882a593Smuzhiyun	flash@0 {
167*4882a593Smuzhiyun		compatible = "jedec,spi-nor";
168*4882a593Smuzhiyun		reg = <0>;
169*4882a593Smuzhiyun		spi-max-frequency = <20000000>;
170*4882a593Smuzhiyun	};
171*4882a593Smuzhiyun};
172*4882a593Smuzhiyun
173*4882a593Smuzhiyun&ecspi2 {
174*4882a593Smuzhiyun	cs-gpios = <&gpio2 26 GPIO_ACTIVE_LOW>, <&gpio4 25 GPIO_ACTIVE_LOW>;
175*4882a593Smuzhiyun	pinctrl-names = "default";
176*4882a593Smuzhiyun	pinctrl-0 = <&pinctrl_ecspi2 &pinctrl_ecspi2_cs>;
177*4882a593Smuzhiyun	status = "okay";
178*4882a593Smuzhiyun
179*4882a593Smuzhiyun	can@0 {
180*4882a593Smuzhiyun		compatible = "microchip,mcp2515";
181*4882a593Smuzhiyun		reg = <0>;
182*4882a593Smuzhiyun		pinctrl-names = "default";
183*4882a593Smuzhiyun		pinctrl-0 = <&pinctrl_can3>;
184*4882a593Smuzhiyun		clocks = <&can_osc>;
185*4882a593Smuzhiyun		interrupts-extended = <&gpio3 20 IRQ_TYPE_LEVEL_LOW>;
186*4882a593Smuzhiyun		spi-max-frequency = <5000000>;
187*4882a593Smuzhiyun	};
188*4882a593Smuzhiyun
189*4882a593Smuzhiyun	adc@1 {
190*4882a593Smuzhiyun		compatible = "ti,adc128s052";
191*4882a593Smuzhiyun		reg = <1>;
192*4882a593Smuzhiyun		spi-max-frequency = <2000000>;
193*4882a593Smuzhiyun		vref-supply = <&reg_3v3>;
194*4882a593Smuzhiyun	};
195*4882a593Smuzhiyun};
196*4882a593Smuzhiyun
197*4882a593Smuzhiyun&ecspi3 {
198*4882a593Smuzhiyun	cs-gpios = <&gpio4 24 GPIO_ACTIVE_LOW>;
199*4882a593Smuzhiyun	pinctrl-names = "default";
200*4882a593Smuzhiyun	pinctrl-0 = <&pinctrl_ecspi3>;
201*4882a593Smuzhiyun	status = "okay";
202*4882a593Smuzhiyun};
203*4882a593Smuzhiyun
204*4882a593Smuzhiyun&fec {
205*4882a593Smuzhiyun	pinctrl-names = "default";
206*4882a593Smuzhiyun	pinctrl-0 = <&pinctrl_enet>;
207*4882a593Smuzhiyun	phy-mode = "rgmii-id";
208*4882a593Smuzhiyun	phy-handle = <&rgmii_phy>;
209*4882a593Smuzhiyun	status = "okay";
210*4882a593Smuzhiyun
211*4882a593Smuzhiyun	mdio {
212*4882a593Smuzhiyun		#address-cells = <1>;
213*4882a593Smuzhiyun		#size-cells = <0>;
214*4882a593Smuzhiyun
215*4882a593Smuzhiyun		/* Microchip KSZ9031RNX PHY */
216*4882a593Smuzhiyun		rgmii_phy: ethernet-phy@0 {
217*4882a593Smuzhiyun			reg = <0>;
218*4882a593Smuzhiyun			interrupts-extended = <&gpio1 28 IRQ_TYPE_LEVEL_LOW>;
219*4882a593Smuzhiyun			reset-gpios = <&gpio1 25 GPIO_ACTIVE_LOW>;
220*4882a593Smuzhiyun			reset-assert-us = <10000>;
221*4882a593Smuzhiyun			reset-deassert-us = <300>;
222*4882a593Smuzhiyun		};
223*4882a593Smuzhiyun	};
224*4882a593Smuzhiyun};
225*4882a593Smuzhiyun
226*4882a593Smuzhiyun&hdmi {
227*4882a593Smuzhiyun	pinctrl-names = "default";
228*4882a593Smuzhiyun	pinctrl-0 = <&pinctrl_hdmi>;
229*4882a593Smuzhiyun	ddc-i2c-bus = <&i2c2>;
230*4882a593Smuzhiyun	status = "okay";
231*4882a593Smuzhiyun};
232*4882a593Smuzhiyun
233*4882a593Smuzhiyun&i2c1 {
234*4882a593Smuzhiyun	sgtl5000: audio-codec@a {
235*4882a593Smuzhiyun		compatible = "fsl,sgtl5000";
236*4882a593Smuzhiyun		reg = <0xa>;
237*4882a593Smuzhiyun		#sound-dai-cells = <0>;
238*4882a593Smuzhiyun		clocks = <&clks 201>;
239*4882a593Smuzhiyun		VDDA-supply = <&reg_3v3>;
240*4882a593Smuzhiyun		VDDIO-supply = <&reg_3v3>;
241*4882a593Smuzhiyun		VDDD-supply = <&reg_1v8>;
242*4882a593Smuzhiyun	};
243*4882a593Smuzhiyun};
244*4882a593Smuzhiyun
245*4882a593Smuzhiyun/* DDC */
246*4882a593Smuzhiyun&i2c2 {
247*4882a593Smuzhiyun	clock-frequency = <100000>;
248*4882a593Smuzhiyun	pinctrl-names = "default";
249*4882a593Smuzhiyun	pinctrl-0 = <&pinctrl_i2c2>;
250*4882a593Smuzhiyun	status = "okay";
251*4882a593Smuzhiyun};
252*4882a593Smuzhiyun
253*4882a593Smuzhiyun&i2c3 {
254*4882a593Smuzhiyun	adc@49 {
255*4882a593Smuzhiyun		compatible = "ti,ads1015";
256*4882a593Smuzhiyun		reg = <0x49>;
257*4882a593Smuzhiyun		#address-cells = <1>;
258*4882a593Smuzhiyun		#size-cells = <0>;
259*4882a593Smuzhiyun
260*4882a593Smuzhiyun		/* can2_l */
261*4882a593Smuzhiyun		channel@4 {
262*4882a593Smuzhiyun			reg = <4>;
263*4882a593Smuzhiyun			ti,gain = <3>;
264*4882a593Smuzhiyun			ti,datarate = <3>;
265*4882a593Smuzhiyun		};
266*4882a593Smuzhiyun
267*4882a593Smuzhiyun		/* can2_h */
268*4882a593Smuzhiyun		channel@5 {
269*4882a593Smuzhiyun			reg = <5>;
270*4882a593Smuzhiyun			ti,gain = <3>;
271*4882a593Smuzhiyun			ti,datarate = <3>;
272*4882a593Smuzhiyun		};
273*4882a593Smuzhiyun
274*4882a593Smuzhiyun		/* can1_l */
275*4882a593Smuzhiyun		channel@6 {
276*4882a593Smuzhiyun			reg = <6>;
277*4882a593Smuzhiyun			ti,gain = <3>;
278*4882a593Smuzhiyun			ti,datarate = <3>;
279*4882a593Smuzhiyun		};
280*4882a593Smuzhiyun
281*4882a593Smuzhiyun		/* can1_h */
282*4882a593Smuzhiyun		channel@7 {
283*4882a593Smuzhiyun			reg = <7>;
284*4882a593Smuzhiyun			ti,gain = <3>;
285*4882a593Smuzhiyun			ti,datarate = <3>;
286*4882a593Smuzhiyun		};
287*4882a593Smuzhiyun	};
288*4882a593Smuzhiyun};
289*4882a593Smuzhiyun
290*4882a593Smuzhiyun&pcie {
291*4882a593Smuzhiyun	status = "okay";
292*4882a593Smuzhiyun};
293*4882a593Smuzhiyun
294*4882a593Smuzhiyun&pwm1 {
295*4882a593Smuzhiyun	#pwm-cells = <2>;
296*4882a593Smuzhiyun	pinctrl-names = "default";
297*4882a593Smuzhiyun	pinctrl-0 = <&pinctrl_pwm1>;
298*4882a593Smuzhiyun	status = "okay";
299*4882a593Smuzhiyun};
300*4882a593Smuzhiyun
301*4882a593Smuzhiyun&ldb {
302*4882a593Smuzhiyun	status = "okay";
303*4882a593Smuzhiyun
304*4882a593Smuzhiyun	lvds-channel@0 {
305*4882a593Smuzhiyun		status = "okay";
306*4882a593Smuzhiyun
307*4882a593Smuzhiyun		port@4 {
308*4882a593Smuzhiyun			reg = <4>;
309*4882a593Smuzhiyun
310*4882a593Smuzhiyun			lvds0_out: endpoint {
311*4882a593Smuzhiyun				remote-endpoint = <&panel_in>;
312*4882a593Smuzhiyun			};
313*4882a593Smuzhiyun		};
314*4882a593Smuzhiyun	};
315*4882a593Smuzhiyun};
316*4882a593Smuzhiyun
317*4882a593Smuzhiyun&sata {
318*4882a593Smuzhiyun	status = "okay";
319*4882a593Smuzhiyun};
320*4882a593Smuzhiyun
321*4882a593Smuzhiyun&snvs_poweroff {
322*4882a593Smuzhiyun	status = "okay";
323*4882a593Smuzhiyun};
324*4882a593Smuzhiyun
325*4882a593Smuzhiyun&spdif {
326*4882a593Smuzhiyun	pinctrl-names = "default";
327*4882a593Smuzhiyun	pinctrl-0 = <&pinctrl_spdif>;
328*4882a593Smuzhiyun	status = "okay";
329*4882a593Smuzhiyun};
330*4882a593Smuzhiyun
331*4882a593Smuzhiyun&ssi1 {
332*4882a593Smuzhiyun	#sound-dai-cells = <0>;
333*4882a593Smuzhiyun	fsl,mode = "ac97-slave";
334*4882a593Smuzhiyun	status = "okay";
335*4882a593Smuzhiyun};
336*4882a593Smuzhiyun
337*4882a593Smuzhiyun&uart2 {
338*4882a593Smuzhiyun	pinctrl-names = "default";
339*4882a593Smuzhiyun	pinctrl-0 = <&pinctrl_uart2>;
340*4882a593Smuzhiyun	status = "okay";
341*4882a593Smuzhiyun};
342*4882a593Smuzhiyun
343*4882a593Smuzhiyun&uart5 {
344*4882a593Smuzhiyun	pinctrl-names = "default";
345*4882a593Smuzhiyun	pinctrl-0 = <&pinctrl_uart5>;
346*4882a593Smuzhiyun	status = "okay";
347*4882a593Smuzhiyun};
348*4882a593Smuzhiyun
349*4882a593Smuzhiyun&usbotg {
350*4882a593Smuzhiyun	pinctrl-0 = <&pinctrl_usbotg &pinctrl_usbotg_id>;
351*4882a593Smuzhiyun};
352*4882a593Smuzhiyun
353*4882a593Smuzhiyun&usdhc2 {
354*4882a593Smuzhiyun	pinctrl-names = "default";
355*4882a593Smuzhiyun	pinctrl-0 = <&pinctrl_usdhc2>;
356*4882a593Smuzhiyun	non-removable;
357*4882a593Smuzhiyun	vmmc-supply = <&reg_wifi>;
358*4882a593Smuzhiyun	cap-power-off-card;
359*4882a593Smuzhiyun	keep-power-in-suspend;
360*4882a593Smuzhiyun	status = "okay";
361*4882a593Smuzhiyun
362*4882a593Smuzhiyun	wifi {
363*4882a593Smuzhiyun		compatible = "ti,wl1271";
364*4882a593Smuzhiyun		pinctrl-names = "default";
365*4882a593Smuzhiyun		pinctrl-0 = <&pinctrl_wifi>;
366*4882a593Smuzhiyun		interrupts-extended = <&gpio1 30 IRQ_TYPE_LEVEL_HIGH>;
367*4882a593Smuzhiyun		ref-clock-frequency = <38400000>;
368*4882a593Smuzhiyun		tcxo-clock-frequency = <19200000>;
369*4882a593Smuzhiyun	};
370*4882a593Smuzhiyun};
371*4882a593Smuzhiyun
372*4882a593Smuzhiyun&iomuxc {
373*4882a593Smuzhiyun	pinctrl_audmux: audmuxgrp {
374*4882a593Smuzhiyun		fsl,pins = <
375*4882a593Smuzhiyun			MX6QDL_PAD_CSI0_MCLK__CCM_CLKO1		0x030b0
376*4882a593Smuzhiyun			MX6QDL_PAD_CSI0_DAT7__AUD3_RXD		0x130b0
377*4882a593Smuzhiyun			MX6QDL_PAD_CSI0_DAT4__AUD3_TXC		0x130b0
378*4882a593Smuzhiyun			MX6QDL_PAD_CSI0_DAT5__AUD3_TXD		0x110b0
379*4882a593Smuzhiyun			MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS		0x130b0
380*4882a593Smuzhiyun		>;
381*4882a593Smuzhiyun	};
382*4882a593Smuzhiyun
383*4882a593Smuzhiyun	pinctrl_backlight: backlightgrp {
384*4882a593Smuzhiyun		fsl,pins = <
385*4882a593Smuzhiyun			MX6QDL_PAD_DISP0_DAT7__GPIO4_IO28	0x1b0b0
386*4882a593Smuzhiyun		>;
387*4882a593Smuzhiyun	};
388*4882a593Smuzhiyun
389*4882a593Smuzhiyun	pinctrl_can2: can2grp {
390*4882a593Smuzhiyun		fsl,pins = <
391*4882a593Smuzhiyun			MX6QDL_PAD_KEY_COL4__FLEXCAN2_TX	0x1b008
392*4882a593Smuzhiyun			MX6QDL_PAD_KEY_ROW4__FLEXCAN2_RX	0x1b008
393*4882a593Smuzhiyun		>;
394*4882a593Smuzhiyun	};
395*4882a593Smuzhiyun
396*4882a593Smuzhiyun	pinctrl_can3: can3grp {
397*4882a593Smuzhiyun		fsl,pins = <
398*4882a593Smuzhiyun			MX6QDL_PAD_EIM_D20__GPIO3_IO20		0x1b0b1
399*4882a593Smuzhiyun		>;
400*4882a593Smuzhiyun	};
401*4882a593Smuzhiyun
402*4882a593Smuzhiyun	pinctrl_ecspi1: ecspi1grp {
403*4882a593Smuzhiyun		fsl,pins = <
404*4882a593Smuzhiyun			MX6QDL_PAD_EIM_D17__ECSPI1_MISO		0x100b1
405*4882a593Smuzhiyun			MX6QDL_PAD_EIM_D18__ECSPI1_MOSI		0x100b1
406*4882a593Smuzhiyun			MX6QDL_PAD_EIM_D16__ECSPI1_SCLK		0x100b1
407*4882a593Smuzhiyun			/* CS */
408*4882a593Smuzhiyun			MX6QDL_PAD_EIM_D19__GPIO3_IO19		0x000b1
409*4882a593Smuzhiyun		>;
410*4882a593Smuzhiyun	};
411*4882a593Smuzhiyun
412*4882a593Smuzhiyun	pinctrl_ecspi2: ecspi2grp {
413*4882a593Smuzhiyun		fsl,pins = <
414*4882a593Smuzhiyun			MX6QDL_PAD_EIM_OE__ECSPI2_MISO		0x100b1
415*4882a593Smuzhiyun			MX6QDL_PAD_EIM_CS0__ECSPI2_SCLK		0x100b1
416*4882a593Smuzhiyun			MX6QDL_PAD_EIM_CS1__ECSPI2_MOSI		0x100b1
417*4882a593Smuzhiyun			MX6QDL_PAD_EIM_RW__GPIO2_IO26		0x000b1
418*4882a593Smuzhiyun		>;
419*4882a593Smuzhiyun	};
420*4882a593Smuzhiyun
421*4882a593Smuzhiyun	pinctrl_ecspi2_cs: ecspi2csgrp {
422*4882a593Smuzhiyun		fsl,pins = <
423*4882a593Smuzhiyun			/* ADC128S022 CS */
424*4882a593Smuzhiyun			MX6QDL_PAD_DISP0_DAT4__GPIO4_IO25	0x1b0b1
425*4882a593Smuzhiyun		>;
426*4882a593Smuzhiyun	};
427*4882a593Smuzhiyun
428*4882a593Smuzhiyun	pinctrl_ecspi3: ecspi3grp {
429*4882a593Smuzhiyun		fsl,pins = <
430*4882a593Smuzhiyun			MX6QDL_PAD_DISP0_DAT0__ECSPI3_SCLK	0x100b1
431*4882a593Smuzhiyun			MX6QDL_PAD_DISP0_DAT1__ECSPI3_MOSI	0x100b1
432*4882a593Smuzhiyun			MX6QDL_PAD_DISP0_DAT2__ECSPI3_MISO	0x100b1
433*4882a593Smuzhiyun			MX6QDL_PAD_DISP0_DAT3__GPIO4_IO24	0x000b1
434*4882a593Smuzhiyun		>;
435*4882a593Smuzhiyun	};
436*4882a593Smuzhiyun
437*4882a593Smuzhiyun	pinctrl_enet: enetgrp {
438*4882a593Smuzhiyun		fsl,pins = <
439*4882a593Smuzhiyun			MX6QDL_PAD_RGMII_RXC__RGMII_RXC		0x1b030
440*4882a593Smuzhiyun			MX6QDL_PAD_RGMII_RD0__RGMII_RD0		0x1b030
441*4882a593Smuzhiyun			MX6QDL_PAD_RGMII_RD1__RGMII_RD1		0x1b030
442*4882a593Smuzhiyun			MX6QDL_PAD_RGMII_RD2__RGMII_RD2		0x1b030
443*4882a593Smuzhiyun			MX6QDL_PAD_RGMII_RD3__RGMII_RD3		0x1b030
444*4882a593Smuzhiyun			MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL	0x1b030
445*4882a593Smuzhiyun			MX6QDL_PAD_RGMII_TXC__RGMII_TXC		0x10030
446*4882a593Smuzhiyun			MX6QDL_PAD_RGMII_TD0__RGMII_TD0		0x10030
447*4882a593Smuzhiyun			MX6QDL_PAD_RGMII_TD1__RGMII_TD1		0x10030
448*4882a593Smuzhiyun			MX6QDL_PAD_RGMII_TD2__RGMII_TD2		0x10030
449*4882a593Smuzhiyun			MX6QDL_PAD_RGMII_TD3__RGMII_TD3		0x10030
450*4882a593Smuzhiyun			MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL	0x10030
451*4882a593Smuzhiyun			MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK	0x10030
452*4882a593Smuzhiyun			MX6QDL_PAD_ENET_MDIO__ENET_MDIO		0x10030
453*4882a593Smuzhiyun			MX6QDL_PAD_ENET_MDC__ENET_MDC		0x10030
454*4882a593Smuzhiyun
455*4882a593Smuzhiyun			/* Phy reset */
456*4882a593Smuzhiyun			MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25	0x1b0b0
457*4882a593Smuzhiyun			MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28	0x1b0b1
458*4882a593Smuzhiyun		>;
459*4882a593Smuzhiyun	};
460*4882a593Smuzhiyun
461*4882a593Smuzhiyun	pinctrl_hdmi: hdmigrp {
462*4882a593Smuzhiyun		fsl,pins = <
463*4882a593Smuzhiyun			/* NOTE: DDC is done via I2C2, so DON'T
464*4882a593Smuzhiyun			 * configure DDC pins for HDMI!
465*4882a593Smuzhiyun			 */
466*4882a593Smuzhiyun			MX6QDL_PAD_EIM_A25__HDMI_TX_CEC_LINE	0x1f8b0
467*4882a593Smuzhiyun		>;
468*4882a593Smuzhiyun	};
469*4882a593Smuzhiyun
470*4882a593Smuzhiyun	/* DDC */
471*4882a593Smuzhiyun	pinctrl_i2c2: i2c2grp {
472*4882a593Smuzhiyun		fsl,pins = <
473*4882a593Smuzhiyun			MX6QDL_PAD_KEY_COL3__I2C2_SCL	0x4001b8b1
474*4882a593Smuzhiyun			MX6QDL_PAD_KEY_ROW3__I2C2_SDA	0x4001b8b1
475*4882a593Smuzhiyun		>;
476*4882a593Smuzhiyun	};
477*4882a593Smuzhiyun
478*4882a593Smuzhiyun	pinctrl_leds: ledsgrp {
479*4882a593Smuzhiyun		fsl,pins = <
480*4882a593Smuzhiyun			MX6QDL_PAD_GPIO_8__GPIO1_IO08		0x1b0b0
481*4882a593Smuzhiyun			MX6QDL_PAD_GPIO_9__GPIO1_IO09		0x1b0b0
482*4882a593Smuzhiyun		>;
483*4882a593Smuzhiyun	};
484*4882a593Smuzhiyun
485*4882a593Smuzhiyun	pinctrl_pwm1: pwm1grp {
486*4882a593Smuzhiyun		fsl,pins = <
487*4882a593Smuzhiyun			MX6QDL_PAD_DISP0_DAT8__PWM1_OUT		0x1b0b0
488*4882a593Smuzhiyun		>;
489*4882a593Smuzhiyun	};
490*4882a593Smuzhiyun
491*4882a593Smuzhiyun	pinctrl_spdif: spdifgrp {
492*4882a593Smuzhiyun		fsl,pins = <
493*4882a593Smuzhiyun			MX6QDL_PAD_GPIO_16__SPDIF_IN		0x1b0b0
494*4882a593Smuzhiyun			MX6QDL_PAD_GPIO_19__SPDIF_OUT		0x1b0b0
495*4882a593Smuzhiyun		>;
496*4882a593Smuzhiyun	};
497*4882a593Smuzhiyun
498*4882a593Smuzhiyun	pinctrl_uart2: uart2grp {
499*4882a593Smuzhiyun		fsl,pins = <
500*4882a593Smuzhiyun			MX6QDL_PAD_EIM_D26__UART2_RX_DATA	0x1b0b1
501*4882a593Smuzhiyun			MX6QDL_PAD_EIM_D27__UART2_TX_DATA	0x1b0b1
502*4882a593Smuzhiyun			MX6QDL_PAD_EIM_D28__UART2_DTE_CTS_B	0x1b0b1
503*4882a593Smuzhiyun			MX6QDL_PAD_EIM_D29__UART2_DTE_RTS_B	0x1b0b1
504*4882a593Smuzhiyun		>;
505*4882a593Smuzhiyun	};
506*4882a593Smuzhiyun
507*4882a593Smuzhiyun	pinctrl_uart5: uart5grp {
508*4882a593Smuzhiyun		fsl,pins = <
509*4882a593Smuzhiyun			MX6QDL_PAD_KEY_COL1__UART5_TX_DATA	0x1b0b1
510*4882a593Smuzhiyun			MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA	0x1b0b1
511*4882a593Smuzhiyun		>;
512*4882a593Smuzhiyun	};
513*4882a593Smuzhiyun
514*4882a593Smuzhiyun	pinctrl_usbotg_id: usbotgidgrp {
515*4882a593Smuzhiyun		fsl,pins = <
516*4882a593Smuzhiyun			MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID	0x1f058
517*4882a593Smuzhiyun		>;
518*4882a593Smuzhiyun	};
519*4882a593Smuzhiyun
520*4882a593Smuzhiyun	pinctrl_usdhc2: usdhc2grp {
521*4882a593Smuzhiyun		fsl,pins = <
522*4882a593Smuzhiyun			MX6QDL_PAD_SD2_CMD__SD2_CMD		0x170b9
523*4882a593Smuzhiyun			MX6QDL_PAD_SD2_CLK__SD2_CLK		0x100b9
524*4882a593Smuzhiyun			MX6QDL_PAD_SD2_DAT0__SD2_DATA0		0x170b9
525*4882a593Smuzhiyun			MX6QDL_PAD_SD2_DAT1__SD2_DATA1		0x170b9
526*4882a593Smuzhiyun			MX6QDL_PAD_SD2_DAT2__SD2_DATA2		0x170b9
527*4882a593Smuzhiyun			MX6QDL_PAD_SD2_DAT3__SD2_DATA3		0x170b9
528*4882a593Smuzhiyun		>;
529*4882a593Smuzhiyun	};
530*4882a593Smuzhiyun
531*4882a593Smuzhiyun	pinctrl_wifi: wifigrp {
532*4882a593Smuzhiyun		fsl,pins = <
533*4882a593Smuzhiyun			/* WL12xx IRQ */
534*4882a593Smuzhiyun			MX6QDL_PAD_ENET_TXD0__GPIO1_IO30	0x10880
535*4882a593Smuzhiyun		>;
536*4882a593Smuzhiyun	};
537*4882a593Smuzhiyun
538*4882a593Smuzhiyun	pinctrl_wifi_npd: wifinpd {
539*4882a593Smuzhiyun		fsl,pins = <
540*4882a593Smuzhiyun			MX6QDL_PAD_ENET_RXD1__GPIO1_IO26	0x1b8b0
541*4882a593Smuzhiyun		>;
542*4882a593Smuzhiyun	};
543*4882a593Smuzhiyun};
544