1*4882a593Smuzhiyun// SPDX-License-Identifier: GPL-2.0-or-later 2*4882a593Smuzhiyun/* 3*4882a593Smuzhiyun * Copyright 2013 Gateworks Corporation 4*4882a593Smuzhiyun */ 5*4882a593Smuzhiyun 6*4882a593Smuzhiyun/dts-v1/; 7*4882a593Smuzhiyun#include <dt-bindings/gpio/gpio.h> 8*4882a593Smuzhiyun#include "imx6q.dtsi" 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun/ { 11*4882a593Smuzhiyun model = "Gateworks Ventana GW5400-A"; 12*4882a593Smuzhiyun compatible = "gw,imx6q-gw5400-a", "gw,ventana", "fsl,imx6q"; 13*4882a593Smuzhiyun 14*4882a593Smuzhiyun /* these are used by bootloader for disabling nodes */ 15*4882a593Smuzhiyun aliases { 16*4882a593Smuzhiyun i2c0 = &i2c1; 17*4882a593Smuzhiyun i2c1 = &i2c2; 18*4882a593Smuzhiyun i2c2 = &i2c3; 19*4882a593Smuzhiyun led0 = &led0; 20*4882a593Smuzhiyun led1 = &led1; 21*4882a593Smuzhiyun led2 = &led2; 22*4882a593Smuzhiyun ssi0 = &ssi1; 23*4882a593Smuzhiyun spi0 = &ecspi1; 24*4882a593Smuzhiyun usb0 = &usbh1; 25*4882a593Smuzhiyun usb1 = &usbotg; 26*4882a593Smuzhiyun }; 27*4882a593Smuzhiyun 28*4882a593Smuzhiyun chosen { 29*4882a593Smuzhiyun bootargs = "console=ttymxc1,115200"; 30*4882a593Smuzhiyun }; 31*4882a593Smuzhiyun 32*4882a593Smuzhiyun leds { 33*4882a593Smuzhiyun compatible = "gpio-leds"; 34*4882a593Smuzhiyun pinctrl-names = "default"; 35*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_gpio_leds>; 36*4882a593Smuzhiyun 37*4882a593Smuzhiyun led0: user1 { 38*4882a593Smuzhiyun label = "user1"; 39*4882a593Smuzhiyun gpios = <&gpio4 6 GPIO_ACTIVE_HIGH>; /* 102 -> MX6_PANLEDG */ 40*4882a593Smuzhiyun default-state = "on"; 41*4882a593Smuzhiyun linux,default-trigger = "heartbeat"; 42*4882a593Smuzhiyun }; 43*4882a593Smuzhiyun 44*4882a593Smuzhiyun led1: user2 { 45*4882a593Smuzhiyun label = "user2"; 46*4882a593Smuzhiyun gpios = <&gpio4 10 GPIO_ACTIVE_HIGH>; /* 106 -> MX6_PANLEDR */ 47*4882a593Smuzhiyun default-state = "off"; 48*4882a593Smuzhiyun }; 49*4882a593Smuzhiyun 50*4882a593Smuzhiyun led2: user3 { 51*4882a593Smuzhiyun label = "user3"; 52*4882a593Smuzhiyun gpios = <&gpio4 15 GPIO_ACTIVE_LOW>; /* 111 -> MX6_LOCLED# */ 53*4882a593Smuzhiyun default-state = "off"; 54*4882a593Smuzhiyun }; 55*4882a593Smuzhiyun }; 56*4882a593Smuzhiyun 57*4882a593Smuzhiyun memory@10000000 { 58*4882a593Smuzhiyun device_type = "memory"; 59*4882a593Smuzhiyun reg = <0x10000000 0x40000000>; 60*4882a593Smuzhiyun }; 61*4882a593Smuzhiyun 62*4882a593Smuzhiyun pps { 63*4882a593Smuzhiyun compatible = "pps-gpio"; 64*4882a593Smuzhiyun pinctrl-names = "default"; 65*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_gpio_leds>; 66*4882a593Smuzhiyun gpios = <&gpio1 5 GPIO_ACTIVE_HIGH>; 67*4882a593Smuzhiyun status = "okay"; 68*4882a593Smuzhiyun }; 69*4882a593Smuzhiyun 70*4882a593Smuzhiyun regulators { 71*4882a593Smuzhiyun compatible = "simple-bus"; 72*4882a593Smuzhiyun #address-cells = <1>; 73*4882a593Smuzhiyun #size-cells = <0>; 74*4882a593Smuzhiyun 75*4882a593Smuzhiyun reg_1p0v: regulator@0 { 76*4882a593Smuzhiyun compatible = "regulator-fixed"; 77*4882a593Smuzhiyun reg = <0>; 78*4882a593Smuzhiyun regulator-name = "1P0V"; 79*4882a593Smuzhiyun regulator-min-microvolt = <1000000>; 80*4882a593Smuzhiyun regulator-max-microvolt = <1000000>; 81*4882a593Smuzhiyun regulator-always-on; 82*4882a593Smuzhiyun }; 83*4882a593Smuzhiyun 84*4882a593Smuzhiyun reg_3p3v: regulator@1 { 85*4882a593Smuzhiyun compatible = "regulator-fixed"; 86*4882a593Smuzhiyun reg = <1>; 87*4882a593Smuzhiyun regulator-name = "3P3V"; 88*4882a593Smuzhiyun regulator-min-microvolt = <3300000>; 89*4882a593Smuzhiyun regulator-max-microvolt = <3300000>; 90*4882a593Smuzhiyun regulator-always-on; 91*4882a593Smuzhiyun }; 92*4882a593Smuzhiyun 93*4882a593Smuzhiyun reg_usb_h1_vbus: regulator@2 { 94*4882a593Smuzhiyun compatible = "regulator-fixed"; 95*4882a593Smuzhiyun reg = <2>; 96*4882a593Smuzhiyun regulator-name = "usb_h1_vbus"; 97*4882a593Smuzhiyun regulator-min-microvolt = <5000000>; 98*4882a593Smuzhiyun regulator-max-microvolt = <5000000>; 99*4882a593Smuzhiyun regulator-always-on; 100*4882a593Smuzhiyun }; 101*4882a593Smuzhiyun 102*4882a593Smuzhiyun reg_usb_otg_vbus: regulator@3 { 103*4882a593Smuzhiyun compatible = "regulator-fixed"; 104*4882a593Smuzhiyun reg = <3>; 105*4882a593Smuzhiyun regulator-name = "usb_otg_vbus"; 106*4882a593Smuzhiyun regulator-min-microvolt = <5000000>; 107*4882a593Smuzhiyun regulator-max-microvolt = <5000000>; 108*4882a593Smuzhiyun gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>; 109*4882a593Smuzhiyun enable-active-high; 110*4882a593Smuzhiyun }; 111*4882a593Smuzhiyun }; 112*4882a593Smuzhiyun 113*4882a593Smuzhiyun sound { 114*4882a593Smuzhiyun compatible = "fsl,imx6q-ventana-sgtl5000", 115*4882a593Smuzhiyun "fsl,imx-audio-sgtl5000"; 116*4882a593Smuzhiyun model = "sgtl5000-audio"; 117*4882a593Smuzhiyun ssi-controller = <&ssi1>; 118*4882a593Smuzhiyun audio-codec = <&codec>; 119*4882a593Smuzhiyun audio-routing = 120*4882a593Smuzhiyun "MIC_IN", "Mic Jack", 121*4882a593Smuzhiyun "Mic Jack", "Mic Bias", 122*4882a593Smuzhiyun "Headphone Jack", "HP_OUT"; 123*4882a593Smuzhiyun mux-int-port = <1>; 124*4882a593Smuzhiyun mux-ext-port = <4>; 125*4882a593Smuzhiyun }; 126*4882a593Smuzhiyun}; 127*4882a593Smuzhiyun 128*4882a593Smuzhiyun&audmux { 129*4882a593Smuzhiyun pinctrl-names = "default"; 130*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_audmux>; 131*4882a593Smuzhiyun status = "okay"; 132*4882a593Smuzhiyun}; 133*4882a593Smuzhiyun 134*4882a593Smuzhiyun&ecspi1 { 135*4882a593Smuzhiyun cs-gpios = <&gpio3 19 GPIO_ACTIVE_LOW>; 136*4882a593Smuzhiyun pinctrl-names = "default"; 137*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_ecspi1>; 138*4882a593Smuzhiyun status = "okay"; 139*4882a593Smuzhiyun 140*4882a593Smuzhiyun flash: flash@0 { 141*4882a593Smuzhiyun compatible = "sst,w25q256", "jedec,spi-nor"; 142*4882a593Smuzhiyun spi-max-frequency = <30000000>; 143*4882a593Smuzhiyun reg = <0>; 144*4882a593Smuzhiyun }; 145*4882a593Smuzhiyun}; 146*4882a593Smuzhiyun 147*4882a593Smuzhiyun&fec { 148*4882a593Smuzhiyun pinctrl-names = "default"; 149*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_enet>; 150*4882a593Smuzhiyun phy-mode = "rgmii-id"; 151*4882a593Smuzhiyun phy-reset-gpios = <&gpio1 30 GPIO_ACTIVE_LOW>; 152*4882a593Smuzhiyun status = "okay"; 153*4882a593Smuzhiyun}; 154*4882a593Smuzhiyun 155*4882a593Smuzhiyun&hdmi { 156*4882a593Smuzhiyun ddc-i2c-bus = <&i2c3>; 157*4882a593Smuzhiyun status = "okay"; 158*4882a593Smuzhiyun}; 159*4882a593Smuzhiyun 160*4882a593Smuzhiyun&i2c1 { 161*4882a593Smuzhiyun clock-frequency = <100000>; 162*4882a593Smuzhiyun pinctrl-names = "default"; 163*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_i2c1>; 164*4882a593Smuzhiyun status = "okay"; 165*4882a593Smuzhiyun 166*4882a593Smuzhiyun eeprom1: eeprom@50 { 167*4882a593Smuzhiyun compatible = "atmel,24c02"; 168*4882a593Smuzhiyun reg = <0x50>; 169*4882a593Smuzhiyun pagesize = <16>; 170*4882a593Smuzhiyun }; 171*4882a593Smuzhiyun 172*4882a593Smuzhiyun eeprom2: eeprom@51 { 173*4882a593Smuzhiyun compatible = "atmel,24c02"; 174*4882a593Smuzhiyun reg = <0x51>; 175*4882a593Smuzhiyun pagesize = <16>; 176*4882a593Smuzhiyun }; 177*4882a593Smuzhiyun 178*4882a593Smuzhiyun eeprom3: eeprom@52 { 179*4882a593Smuzhiyun compatible = "atmel,24c02"; 180*4882a593Smuzhiyun reg = <0x52>; 181*4882a593Smuzhiyun pagesize = <16>; 182*4882a593Smuzhiyun }; 183*4882a593Smuzhiyun 184*4882a593Smuzhiyun eeprom4: eeprom@53 { 185*4882a593Smuzhiyun compatible = "atmel,24c02"; 186*4882a593Smuzhiyun reg = <0x53>; 187*4882a593Smuzhiyun pagesize = <16>; 188*4882a593Smuzhiyun }; 189*4882a593Smuzhiyun 190*4882a593Smuzhiyun gpio: pca9555@23 { 191*4882a593Smuzhiyun compatible = "nxp,pca9555"; 192*4882a593Smuzhiyun reg = <0x23>; 193*4882a593Smuzhiyun gpio-controller; 194*4882a593Smuzhiyun #gpio-cells = <2>; 195*4882a593Smuzhiyun }; 196*4882a593Smuzhiyun 197*4882a593Smuzhiyun rtc: ds1672@68 { 198*4882a593Smuzhiyun compatible = "dallas,ds1672"; 199*4882a593Smuzhiyun reg = <0x68>; 200*4882a593Smuzhiyun }; 201*4882a593Smuzhiyun}; 202*4882a593Smuzhiyun 203*4882a593Smuzhiyun&i2c2 { 204*4882a593Smuzhiyun clock-frequency = <100000>; 205*4882a593Smuzhiyun pinctrl-names = "default"; 206*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_i2c2>; 207*4882a593Smuzhiyun status = "okay"; 208*4882a593Smuzhiyun 209*4882a593Smuzhiyun pmic: pfuze100@8 { 210*4882a593Smuzhiyun compatible = "fsl,pfuze100"; 211*4882a593Smuzhiyun reg = <0x08>; 212*4882a593Smuzhiyun 213*4882a593Smuzhiyun regulators { 214*4882a593Smuzhiyun sw1a_reg: sw1ab { 215*4882a593Smuzhiyun regulator-min-microvolt = <300000>; 216*4882a593Smuzhiyun regulator-max-microvolt = <1875000>; 217*4882a593Smuzhiyun regulator-boot-on; 218*4882a593Smuzhiyun regulator-always-on; 219*4882a593Smuzhiyun regulator-ramp-delay = <6250>; 220*4882a593Smuzhiyun }; 221*4882a593Smuzhiyun 222*4882a593Smuzhiyun sw1c_reg: sw1c { 223*4882a593Smuzhiyun regulator-min-microvolt = <300000>; 224*4882a593Smuzhiyun regulator-max-microvolt = <1875000>; 225*4882a593Smuzhiyun regulator-boot-on; 226*4882a593Smuzhiyun regulator-always-on; 227*4882a593Smuzhiyun regulator-ramp-delay = <6250>; 228*4882a593Smuzhiyun }; 229*4882a593Smuzhiyun 230*4882a593Smuzhiyun sw2_reg: sw2 { 231*4882a593Smuzhiyun regulator-min-microvolt = <800000>; 232*4882a593Smuzhiyun regulator-max-microvolt = <3950000>; 233*4882a593Smuzhiyun regulator-boot-on; 234*4882a593Smuzhiyun regulator-always-on; 235*4882a593Smuzhiyun }; 236*4882a593Smuzhiyun 237*4882a593Smuzhiyun sw3a_reg: sw3a { 238*4882a593Smuzhiyun regulator-min-microvolt = <400000>; 239*4882a593Smuzhiyun regulator-max-microvolt = <1975000>; 240*4882a593Smuzhiyun regulator-boot-on; 241*4882a593Smuzhiyun regulator-always-on; 242*4882a593Smuzhiyun }; 243*4882a593Smuzhiyun 244*4882a593Smuzhiyun sw3b_reg: sw3b { 245*4882a593Smuzhiyun regulator-min-microvolt = <400000>; 246*4882a593Smuzhiyun regulator-max-microvolt = <1975000>; 247*4882a593Smuzhiyun regulator-boot-on; 248*4882a593Smuzhiyun regulator-always-on; 249*4882a593Smuzhiyun }; 250*4882a593Smuzhiyun 251*4882a593Smuzhiyun sw4_reg: sw4 { 252*4882a593Smuzhiyun regulator-min-microvolt = <800000>; 253*4882a593Smuzhiyun regulator-max-microvolt = <3300000>; 254*4882a593Smuzhiyun }; 255*4882a593Smuzhiyun 256*4882a593Smuzhiyun swbst_reg: swbst { 257*4882a593Smuzhiyun regulator-min-microvolt = <5000000>; 258*4882a593Smuzhiyun regulator-max-microvolt = <5150000>; 259*4882a593Smuzhiyun }; 260*4882a593Smuzhiyun 261*4882a593Smuzhiyun snvs_reg: vsnvs { 262*4882a593Smuzhiyun regulator-min-microvolt = <1000000>; 263*4882a593Smuzhiyun regulator-max-microvolt = <3000000>; 264*4882a593Smuzhiyun regulator-boot-on; 265*4882a593Smuzhiyun regulator-always-on; 266*4882a593Smuzhiyun }; 267*4882a593Smuzhiyun 268*4882a593Smuzhiyun vref_reg: vrefddr { 269*4882a593Smuzhiyun regulator-boot-on; 270*4882a593Smuzhiyun regulator-always-on; 271*4882a593Smuzhiyun }; 272*4882a593Smuzhiyun 273*4882a593Smuzhiyun vgen1_reg: vgen1 { 274*4882a593Smuzhiyun regulator-min-microvolt = <800000>; 275*4882a593Smuzhiyun regulator-max-microvolt = <1550000>; 276*4882a593Smuzhiyun }; 277*4882a593Smuzhiyun 278*4882a593Smuzhiyun vgen2_reg: vgen2 { 279*4882a593Smuzhiyun regulator-min-microvolt = <800000>; 280*4882a593Smuzhiyun regulator-max-microvolt = <1550000>; 281*4882a593Smuzhiyun }; 282*4882a593Smuzhiyun 283*4882a593Smuzhiyun vgen3_reg: vgen3 { 284*4882a593Smuzhiyun regulator-min-microvolt = <1800000>; 285*4882a593Smuzhiyun regulator-max-microvolt = <3300000>; 286*4882a593Smuzhiyun }; 287*4882a593Smuzhiyun 288*4882a593Smuzhiyun vgen4_reg: vgen4 { 289*4882a593Smuzhiyun regulator-min-microvolt = <1800000>; 290*4882a593Smuzhiyun regulator-max-microvolt = <3300000>; 291*4882a593Smuzhiyun regulator-always-on; 292*4882a593Smuzhiyun }; 293*4882a593Smuzhiyun 294*4882a593Smuzhiyun vgen5_reg: vgen5 { 295*4882a593Smuzhiyun regulator-min-microvolt = <1800000>; 296*4882a593Smuzhiyun regulator-max-microvolt = <3300000>; 297*4882a593Smuzhiyun regulator-always-on; 298*4882a593Smuzhiyun }; 299*4882a593Smuzhiyun 300*4882a593Smuzhiyun vgen6_reg: vgen6 { 301*4882a593Smuzhiyun regulator-min-microvolt = <1800000>; 302*4882a593Smuzhiyun regulator-max-microvolt = <3300000>; 303*4882a593Smuzhiyun regulator-always-on; 304*4882a593Smuzhiyun }; 305*4882a593Smuzhiyun }; 306*4882a593Smuzhiyun }; 307*4882a593Smuzhiyun}; 308*4882a593Smuzhiyun 309*4882a593Smuzhiyun&i2c3 { 310*4882a593Smuzhiyun clock-frequency = <100000>; 311*4882a593Smuzhiyun pinctrl-names = "default"; 312*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_i2c3>; 313*4882a593Smuzhiyun status = "okay"; 314*4882a593Smuzhiyun 315*4882a593Smuzhiyun accelerometer: mma8450@1c { 316*4882a593Smuzhiyun compatible = "fsl,mma8450"; 317*4882a593Smuzhiyun reg = <0x1c>; 318*4882a593Smuzhiyun }; 319*4882a593Smuzhiyun 320*4882a593Smuzhiyun codec: sgtl5000@a { 321*4882a593Smuzhiyun compatible = "fsl,sgtl5000"; 322*4882a593Smuzhiyun reg = <0x0a>; 323*4882a593Smuzhiyun clocks = <&clks IMX6QDL_CLK_CKO>; 324*4882a593Smuzhiyun VDDA-supply = <&sw4_reg>; 325*4882a593Smuzhiyun VDDIO-supply = <®_3p3v>; 326*4882a593Smuzhiyun }; 327*4882a593Smuzhiyun 328*4882a593Smuzhiyun touchscreen: egalax_ts@4 { 329*4882a593Smuzhiyun compatible = "eeti,egalax_ts"; 330*4882a593Smuzhiyun reg = <0x04>; 331*4882a593Smuzhiyun interrupt-parent = <&gpio7>; 332*4882a593Smuzhiyun interrupts = <12 2>; 333*4882a593Smuzhiyun wakeup-gpios = <&gpio7 12 GPIO_ACTIVE_LOW>; 334*4882a593Smuzhiyun }; 335*4882a593Smuzhiyun}; 336*4882a593Smuzhiyun 337*4882a593Smuzhiyun&ldb { 338*4882a593Smuzhiyun status = "okay"; 339*4882a593Smuzhiyun}; 340*4882a593Smuzhiyun 341*4882a593Smuzhiyun&pcie { 342*4882a593Smuzhiyun reset-gpio = <&gpio1 29 GPIO_ACTIVE_LOW>; 343*4882a593Smuzhiyun status = "okay"; 344*4882a593Smuzhiyun}; 345*4882a593Smuzhiyun 346*4882a593Smuzhiyun&ssi1 { 347*4882a593Smuzhiyun status = "okay"; 348*4882a593Smuzhiyun}; 349*4882a593Smuzhiyun 350*4882a593Smuzhiyun&uart1 { 351*4882a593Smuzhiyun pinctrl-names = "default"; 352*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_uart1>; 353*4882a593Smuzhiyun status = "okay"; 354*4882a593Smuzhiyun}; 355*4882a593Smuzhiyun 356*4882a593Smuzhiyun&uart2 { 357*4882a593Smuzhiyun pinctrl-names = "default"; 358*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_uart2>; 359*4882a593Smuzhiyun status = "okay"; 360*4882a593Smuzhiyun}; 361*4882a593Smuzhiyun 362*4882a593Smuzhiyun&uart5 { 363*4882a593Smuzhiyun pinctrl-names = "default"; 364*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_uart5>; 365*4882a593Smuzhiyun status = "okay"; 366*4882a593Smuzhiyun}; 367*4882a593Smuzhiyun 368*4882a593Smuzhiyun&usbotg { 369*4882a593Smuzhiyun vbus-supply = <®_usb_otg_vbus>; 370*4882a593Smuzhiyun pinctrl-names = "default"; 371*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_usbotg>; 372*4882a593Smuzhiyun disable-over-current; 373*4882a593Smuzhiyun status = "okay"; 374*4882a593Smuzhiyun}; 375*4882a593Smuzhiyun 376*4882a593Smuzhiyun&usbh1 { 377*4882a593Smuzhiyun vbus-supply = <®_usb_h1_vbus>; 378*4882a593Smuzhiyun status = "okay"; 379*4882a593Smuzhiyun}; 380*4882a593Smuzhiyun 381*4882a593Smuzhiyun&usdhc3 { 382*4882a593Smuzhiyun pinctrl-names = "default"; 383*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_usdhc3>; 384*4882a593Smuzhiyun cd-gpios = <&gpio7 0 GPIO_ACTIVE_LOW>; 385*4882a593Smuzhiyun vmmc-supply = <®_3p3v>; 386*4882a593Smuzhiyun status = "okay"; 387*4882a593Smuzhiyun}; 388*4882a593Smuzhiyun 389*4882a593Smuzhiyun&iomuxc { 390*4882a593Smuzhiyun pinctrl_audmux: audmuxgrp { 391*4882a593Smuzhiyun fsl,pins = < 392*4882a593Smuzhiyun MX6QDL_PAD_SD2_DAT0__AUD4_RXD 0x130b0 393*4882a593Smuzhiyun MX6QDL_PAD_SD2_DAT3__AUD4_TXC 0x130b0 394*4882a593Smuzhiyun MX6QDL_PAD_SD2_DAT2__AUD4_TXD 0x110b0 395*4882a593Smuzhiyun MX6QDL_PAD_SD2_DAT1__AUD4_TXFS 0x130b0 396*4882a593Smuzhiyun MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x130b0 /* AUD4_MCK */ 397*4882a593Smuzhiyun >; 398*4882a593Smuzhiyun }; 399*4882a593Smuzhiyun 400*4882a593Smuzhiyun pinctrl_ecspi1: ecspi1grp { 401*4882a593Smuzhiyun fsl,pins = < 402*4882a593Smuzhiyun MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1 403*4882a593Smuzhiyun MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1 404*4882a593Smuzhiyun MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x100b1 405*4882a593Smuzhiyun MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x1b0b0 /* SPINOR_CS0# */ 406*4882a593Smuzhiyun >; 407*4882a593Smuzhiyun }; 408*4882a593Smuzhiyun 409*4882a593Smuzhiyun pinctrl_enet: enetgrp { 410*4882a593Smuzhiyun fsl,pins = < 411*4882a593Smuzhiyun MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030 412*4882a593Smuzhiyun MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030 413*4882a593Smuzhiyun MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030 414*4882a593Smuzhiyun MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030 415*4882a593Smuzhiyun MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030 416*4882a593Smuzhiyun MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030 417*4882a593Smuzhiyun MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030 418*4882a593Smuzhiyun MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030 419*4882a593Smuzhiyun MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030 420*4882a593Smuzhiyun MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030 421*4882a593Smuzhiyun MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030 422*4882a593Smuzhiyun MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030 423*4882a593Smuzhiyun MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 424*4882a593Smuzhiyun MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 425*4882a593Smuzhiyun MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 426*4882a593Smuzhiyun MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8 427*4882a593Smuzhiyun >; 428*4882a593Smuzhiyun }; 429*4882a593Smuzhiyun 430*4882a593Smuzhiyun pinctrl_gpio_leds: gpioledsgrp { 431*4882a593Smuzhiyun fsl,pins = < 432*4882a593Smuzhiyun MX6QDL_PAD_KEY_COL0__GPIO4_IO06 0x1b0b0 /* user1 led */ 433*4882a593Smuzhiyun MX6QDL_PAD_KEY_COL2__GPIO4_IO10 0x1b0b0 /* user2 led */ 434*4882a593Smuzhiyun MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x1b0b0 /* user3 led */ 435*4882a593Smuzhiyun >; 436*4882a593Smuzhiyun }; 437*4882a593Smuzhiyun 438*4882a593Smuzhiyun pinctrl_i2c1: i2c1grp { 439*4882a593Smuzhiyun fsl,pins = < 440*4882a593Smuzhiyun MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1 441*4882a593Smuzhiyun MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1 442*4882a593Smuzhiyun >; 443*4882a593Smuzhiyun }; 444*4882a593Smuzhiyun 445*4882a593Smuzhiyun pinctrl_i2c2: i2c2grp { 446*4882a593Smuzhiyun fsl,pins = < 447*4882a593Smuzhiyun MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 448*4882a593Smuzhiyun MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 449*4882a593Smuzhiyun >; 450*4882a593Smuzhiyun }; 451*4882a593Smuzhiyun 452*4882a593Smuzhiyun pinctrl_i2c3: i2c3grp { 453*4882a593Smuzhiyun fsl,pins = < 454*4882a593Smuzhiyun MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1 455*4882a593Smuzhiyun MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1 456*4882a593Smuzhiyun >; 457*4882a593Smuzhiyun }; 458*4882a593Smuzhiyun 459*4882a593Smuzhiyun pinctrl_pcie: pciegrp { 460*4882a593Smuzhiyun fsl,pins = < 461*4882a593Smuzhiyun MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x1b0b0 /* PCIE IRQ */ 462*4882a593Smuzhiyun MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x1b0b0 /* PCIE RST */ 463*4882a593Smuzhiyun >; 464*4882a593Smuzhiyun }; 465*4882a593Smuzhiyun 466*4882a593Smuzhiyun pinctrl_pps: ppsgrp { 467*4882a593Smuzhiyun fsl,pins = < 468*4882a593Smuzhiyun MX6QDL_PAD_GPIO_5__GPIO1_IO05 0x1b0b0 /* GPS_PPS */ 469*4882a593Smuzhiyun >; 470*4882a593Smuzhiyun }; 471*4882a593Smuzhiyun 472*4882a593Smuzhiyun pinctrl_uart1: uart1grp { 473*4882a593Smuzhiyun fsl,pins = < 474*4882a593Smuzhiyun MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1 475*4882a593Smuzhiyun MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA 0x1b0b1 476*4882a593Smuzhiyun >; 477*4882a593Smuzhiyun }; 478*4882a593Smuzhiyun 479*4882a593Smuzhiyun pinctrl_uart2: uart2grp { 480*4882a593Smuzhiyun fsl,pins = < 481*4882a593Smuzhiyun MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b1 482*4882a593Smuzhiyun MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b1 483*4882a593Smuzhiyun >; 484*4882a593Smuzhiyun }; 485*4882a593Smuzhiyun 486*4882a593Smuzhiyun pinctrl_uart5: uart5grp { 487*4882a593Smuzhiyun fsl,pins = < 488*4882a593Smuzhiyun MX6QDL_PAD_KEY_COL1__UART5_TX_DATA 0x1b0b1 489*4882a593Smuzhiyun MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x1b0b1 490*4882a593Smuzhiyun >; 491*4882a593Smuzhiyun }; 492*4882a593Smuzhiyun 493*4882a593Smuzhiyun pinctrl_usbotg: usbotggrp { 494*4882a593Smuzhiyun fsl,pins = < 495*4882a593Smuzhiyun MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059 496*4882a593Smuzhiyun MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x1b0b0 /* OTG_PWR_EN */ 497*4882a593Smuzhiyun >; 498*4882a593Smuzhiyun }; 499*4882a593Smuzhiyun 500*4882a593Smuzhiyun pinctrl_usdhc3: usdhc3grp { 501*4882a593Smuzhiyun fsl,pins = < 502*4882a593Smuzhiyun MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 503*4882a593Smuzhiyun MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 504*4882a593Smuzhiyun MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 505*4882a593Smuzhiyun MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 506*4882a593Smuzhiyun MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 507*4882a593Smuzhiyun MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 508*4882a593Smuzhiyun >; 509*4882a593Smuzhiyun }; 510*4882a593Smuzhiyun}; 511