1*4882a593Smuzhiyun// SPDX-License-Identifier: (GPL-2.0 OR MIT) 2*4882a593Smuzhiyun 3*4882a593Smuzhiyun/* 4*4882a593Smuzhiyun * Copyright (C) 2018 Zodiac Inflight Innovations 5*4882a593Smuzhiyun */ 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun/dts-v1/; 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun#include "imx51.dtsi" 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun/ { 12*4882a593Smuzhiyun model = "ZII SCU3 ESB board"; 13*4882a593Smuzhiyun compatible = "zii,imx51-scu3-esb", "fsl,imx51"; 14*4882a593Smuzhiyun 15*4882a593Smuzhiyun chosen { 16*4882a593Smuzhiyun stdout-path = &uart1; 17*4882a593Smuzhiyun }; 18*4882a593Smuzhiyun 19*4882a593Smuzhiyun /* Will be filled by the bootloader */ 20*4882a593Smuzhiyun memory@90000000 { 21*4882a593Smuzhiyun device_type = "memory"; 22*4882a593Smuzhiyun reg = <0x90000000 0>; 23*4882a593Smuzhiyun }; 24*4882a593Smuzhiyun 25*4882a593Smuzhiyun usb_vbus: regulator-usb-vbus { 26*4882a593Smuzhiyun compatible = "regulator-fixed"; 27*4882a593Smuzhiyun regulator-name = "usb_vbus"; 28*4882a593Smuzhiyun regulator-min-microvolt = <5000000>; 29*4882a593Smuzhiyun regulator-max-microvolt = <5000000>; 30*4882a593Smuzhiyun 31*4882a593Smuzhiyun pinctrl-names = "default"; 32*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_usb_mmc_reset>; 33*4882a593Smuzhiyun gpio = <&gpio4 19 GPIO_ACTIVE_LOW>; 34*4882a593Smuzhiyun startup-delay-us = <150000>; 35*4882a593Smuzhiyun }; 36*4882a593Smuzhiyun}; 37*4882a593Smuzhiyun 38*4882a593Smuzhiyun&cpu { 39*4882a593Smuzhiyun cpu-supply = <&sw1_reg>; 40*4882a593Smuzhiyun}; 41*4882a593Smuzhiyun 42*4882a593Smuzhiyun&ecspi1 { 43*4882a593Smuzhiyun pinctrl-names = "default"; 44*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_ecspi1>; 45*4882a593Smuzhiyun cs-gpios = <&gpio4 24 GPIO_ACTIVE_HIGH>, 46*4882a593Smuzhiyun <&gpio4 25 GPIO_ACTIVE_LOW>; 47*4882a593Smuzhiyun status = "okay"; 48*4882a593Smuzhiyun 49*4882a593Smuzhiyun pmic@0 { 50*4882a593Smuzhiyun compatible = "fsl,mc13892"; 51*4882a593Smuzhiyun pinctrl-names = "default"; 52*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_pmic>; 53*4882a593Smuzhiyun spi-max-frequency = <6000000>; 54*4882a593Smuzhiyun spi-cs-high; 55*4882a593Smuzhiyun reg = <0>; 56*4882a593Smuzhiyun interrupt-parent = <&gpio1>; 57*4882a593Smuzhiyun interrupts = <8 IRQ_TYPE_LEVEL_HIGH>; 58*4882a593Smuzhiyun fsl,mc13xxx-uses-adc; 59*4882a593Smuzhiyun 60*4882a593Smuzhiyun regulators { 61*4882a593Smuzhiyun sw1_reg: sw1 { 62*4882a593Smuzhiyun regulator-min-microvolt = <600000>; 63*4882a593Smuzhiyun regulator-max-microvolt = <1375000>; 64*4882a593Smuzhiyun regulator-boot-on; 65*4882a593Smuzhiyun regulator-always-on; 66*4882a593Smuzhiyun }; 67*4882a593Smuzhiyun 68*4882a593Smuzhiyun sw2_reg: sw2 { 69*4882a593Smuzhiyun regulator-min-microvolt = <900000>; 70*4882a593Smuzhiyun regulator-max-microvolt = <1850000>; 71*4882a593Smuzhiyun regulator-boot-on; 72*4882a593Smuzhiyun regulator-always-on; 73*4882a593Smuzhiyun }; 74*4882a593Smuzhiyun 75*4882a593Smuzhiyun sw3_reg: sw3 { 76*4882a593Smuzhiyun regulator-min-microvolt = <1100000>; 77*4882a593Smuzhiyun regulator-max-microvolt = <1850000>; 78*4882a593Smuzhiyun regulator-boot-on; 79*4882a593Smuzhiyun regulator-always-on; 80*4882a593Smuzhiyun }; 81*4882a593Smuzhiyun 82*4882a593Smuzhiyun sw4_reg: sw4 { 83*4882a593Smuzhiyun regulator-min-microvolt = <1100000>; 84*4882a593Smuzhiyun regulator-max-microvolt = <1850000>; 85*4882a593Smuzhiyun regulator-boot-on; 86*4882a593Smuzhiyun regulator-always-on; 87*4882a593Smuzhiyun }; 88*4882a593Smuzhiyun 89*4882a593Smuzhiyun vpll_reg: vpll { 90*4882a593Smuzhiyun regulator-min-microvolt = <1050000>; 91*4882a593Smuzhiyun regulator-max-microvolt = <1800000>; 92*4882a593Smuzhiyun regulator-boot-on; 93*4882a593Smuzhiyun regulator-always-on; 94*4882a593Smuzhiyun }; 95*4882a593Smuzhiyun 96*4882a593Smuzhiyun vdig_reg: vdig { 97*4882a593Smuzhiyun regulator-min-microvolt = <1650000>; 98*4882a593Smuzhiyun regulator-max-microvolt = <1650000>; 99*4882a593Smuzhiyun regulator-boot-on; 100*4882a593Smuzhiyun }; 101*4882a593Smuzhiyun 102*4882a593Smuzhiyun vsd_reg: vsd { 103*4882a593Smuzhiyun regulator-min-microvolt = <1800000>; 104*4882a593Smuzhiyun regulator-max-microvolt = <3150000>; 105*4882a593Smuzhiyun }; 106*4882a593Smuzhiyun 107*4882a593Smuzhiyun vusb_reg: vusb { 108*4882a593Smuzhiyun regulator-always-on; 109*4882a593Smuzhiyun }; 110*4882a593Smuzhiyun 111*4882a593Smuzhiyun vusb2_reg: vusb2 { 112*4882a593Smuzhiyun regulator-min-microvolt = <2400000>; 113*4882a593Smuzhiyun regulator-max-microvolt = <2775000>; 114*4882a593Smuzhiyun regulator-boot-on; 115*4882a593Smuzhiyun regulator-always-on; 116*4882a593Smuzhiyun }; 117*4882a593Smuzhiyun 118*4882a593Smuzhiyun vvideo_reg: vvideo { 119*4882a593Smuzhiyun regulator-min-microvolt = <2775000>; 120*4882a593Smuzhiyun regulator-max-microvolt = <2775000>; 121*4882a593Smuzhiyun }; 122*4882a593Smuzhiyun 123*4882a593Smuzhiyun vaudio_reg: vaudio { 124*4882a593Smuzhiyun regulator-min-microvolt = <2300000>; 125*4882a593Smuzhiyun regulator-max-microvolt = <3000000>; 126*4882a593Smuzhiyun }; 127*4882a593Smuzhiyun 128*4882a593Smuzhiyun vcam_reg: vcam { 129*4882a593Smuzhiyun regulator-min-microvolt = <2500000>; 130*4882a593Smuzhiyun regulator-max-microvolt = <3000000>; 131*4882a593Smuzhiyun }; 132*4882a593Smuzhiyun 133*4882a593Smuzhiyun vgen1_reg: vgen1 { 134*4882a593Smuzhiyun regulator-min-microvolt = <1200000>; 135*4882a593Smuzhiyun regulator-max-microvolt = <1200000>; 136*4882a593Smuzhiyun }; 137*4882a593Smuzhiyun 138*4882a593Smuzhiyun vgen2_reg: vgen2 { 139*4882a593Smuzhiyun regulator-min-microvolt = <1200000>; 140*4882a593Smuzhiyun regulator-max-microvolt = <3150000>; 141*4882a593Smuzhiyun regulator-always-on; 142*4882a593Smuzhiyun }; 143*4882a593Smuzhiyun 144*4882a593Smuzhiyun vgen3_reg: vgen3 { 145*4882a593Smuzhiyun regulator-min-microvolt = <1800000>; 146*4882a593Smuzhiyun regulator-max-microvolt = <2900000>; 147*4882a593Smuzhiyun regulator-always-on; 148*4882a593Smuzhiyun }; 149*4882a593Smuzhiyun }; 150*4882a593Smuzhiyun 151*4882a593Smuzhiyun leds { 152*4882a593Smuzhiyun #address-cells = <1>; 153*4882a593Smuzhiyun #size-cells = <0>; 154*4882a593Smuzhiyun led-control = <0x0 0x0 0x3f83f8 0x0>; 155*4882a593Smuzhiyun 156*4882a593Smuzhiyun sysled3: led3@3 { 157*4882a593Smuzhiyun reg = <3>; 158*4882a593Smuzhiyun label = "system:red:power"; 159*4882a593Smuzhiyun linux,default-trigger = "default-on"; 160*4882a593Smuzhiyun }; 161*4882a593Smuzhiyun 162*4882a593Smuzhiyun sysled4: led4@4 { 163*4882a593Smuzhiyun reg = <4>; 164*4882a593Smuzhiyun label = "system:green:act"; 165*4882a593Smuzhiyun linux,default-trigger = "heartbeat"; 166*4882a593Smuzhiyun }; 167*4882a593Smuzhiyun }; 168*4882a593Smuzhiyun }; 169*4882a593Smuzhiyun 170*4882a593Smuzhiyun flash@1 { 171*4882a593Smuzhiyun #address-cells = <1>; 172*4882a593Smuzhiyun #size-cells = <1>; 173*4882a593Smuzhiyun compatible = "atmel,at45", "atmel,dataflash"; 174*4882a593Smuzhiyun spi-max-frequency = <25000000>; 175*4882a593Smuzhiyun reg = <1>; 176*4882a593Smuzhiyun }; 177*4882a593Smuzhiyun}; 178*4882a593Smuzhiyun 179*4882a593Smuzhiyun&esdhc1 { 180*4882a593Smuzhiyun pinctrl-names = "default"; 181*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_esdhc1>; 182*4882a593Smuzhiyun bus-width = <8>; 183*4882a593Smuzhiyun non-removable; 184*4882a593Smuzhiyun no-1-8-v; 185*4882a593Smuzhiyun no-sdio; 186*4882a593Smuzhiyun no-sd; 187*4882a593Smuzhiyun status = "okay"; 188*4882a593Smuzhiyun}; 189*4882a593Smuzhiyun 190*4882a593Smuzhiyun&esdhc4 { 191*4882a593Smuzhiyun pinctrl-names = "default"; 192*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_esdhc4>; 193*4882a593Smuzhiyun bus-width = <4>; 194*4882a593Smuzhiyun no-1-8-v; 195*4882a593Smuzhiyun no-sdio; 196*4882a593Smuzhiyun cd-gpios = <&gpio4 8 GPIO_ACTIVE_LOW>; 197*4882a593Smuzhiyun status = "okay"; 198*4882a593Smuzhiyun}; 199*4882a593Smuzhiyun 200*4882a593Smuzhiyun&fec { 201*4882a593Smuzhiyun pinctrl-names = "default"; 202*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_fec>; 203*4882a593Smuzhiyun phy-mode = "mii"; 204*4882a593Smuzhiyun status = "okay"; 205*4882a593Smuzhiyun 206*4882a593Smuzhiyun fixed-link { 207*4882a593Smuzhiyun speed = <100>; 208*4882a593Smuzhiyun full-duplex; 209*4882a593Smuzhiyun }; 210*4882a593Smuzhiyun 211*4882a593Smuzhiyun fec_mdio: mdio { 212*4882a593Smuzhiyun #address-cells = <1>; 213*4882a593Smuzhiyun #size-cells = <0>; 214*4882a593Smuzhiyun status = "okay"; 215*4882a593Smuzhiyun 216*4882a593Smuzhiyun switch@0 { 217*4882a593Smuzhiyun compatible = "marvell,mv88e6085"; 218*4882a593Smuzhiyun reg = <0>; 219*4882a593Smuzhiyun dsa,member = <0 0>; 220*4882a593Smuzhiyun eeprom-length = <512>; 221*4882a593Smuzhiyun interrupt-parent = <&gpio4>; 222*4882a593Smuzhiyun interrupts = <20 IRQ_TYPE_LEVEL_HIGH>; 223*4882a593Smuzhiyun interrupt-controller; 224*4882a593Smuzhiyun #interrupt-cells = <2>; 225*4882a593Smuzhiyun pinctrl-names = "default"; 226*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_switch>; 227*4882a593Smuzhiyun 228*4882a593Smuzhiyun ports { 229*4882a593Smuzhiyun #address-cells = <1>; 230*4882a593Smuzhiyun #size-cells = <0>; 231*4882a593Smuzhiyun 232*4882a593Smuzhiyun port@0 { 233*4882a593Smuzhiyun reg = <0>; 234*4882a593Smuzhiyun label = "port1"; 235*4882a593Smuzhiyun }; 236*4882a593Smuzhiyun 237*4882a593Smuzhiyun port@1 { 238*4882a593Smuzhiyun reg = <1>; 239*4882a593Smuzhiyun label = "port2"; 240*4882a593Smuzhiyun }; 241*4882a593Smuzhiyun 242*4882a593Smuzhiyun port@2 { 243*4882a593Smuzhiyun reg = <2>; 244*4882a593Smuzhiyun label = "port3"; 245*4882a593Smuzhiyun }; 246*4882a593Smuzhiyun 247*4882a593Smuzhiyun port@3 { 248*4882a593Smuzhiyun reg = <3>; 249*4882a593Smuzhiyun label = "scu2scu"; 250*4882a593Smuzhiyun }; 251*4882a593Smuzhiyun 252*4882a593Smuzhiyun port@4 { 253*4882a593Smuzhiyun reg = <4>; 254*4882a593Smuzhiyun label = "esb2host"; 255*4882a593Smuzhiyun }; 256*4882a593Smuzhiyun 257*4882a593Smuzhiyun port@5 { 258*4882a593Smuzhiyun reg = <5>; 259*4882a593Smuzhiyun label = "esb2mezz"; 260*4882a593Smuzhiyun phy-mode = "sgmii"; 261*4882a593Smuzhiyun 262*4882a593Smuzhiyun fixed-link { 263*4882a593Smuzhiyun speed = <1000>; 264*4882a593Smuzhiyun full-duplex; 265*4882a593Smuzhiyun }; 266*4882a593Smuzhiyun }; 267*4882a593Smuzhiyun 268*4882a593Smuzhiyun port@6 { 269*4882a593Smuzhiyun reg = <6>; 270*4882a593Smuzhiyun label = "cpu"; 271*4882a593Smuzhiyun phy-mode = "mii"; 272*4882a593Smuzhiyun ethernet = <&fec>; 273*4882a593Smuzhiyun 274*4882a593Smuzhiyun fixed-link { 275*4882a593Smuzhiyun speed = <100>; 276*4882a593Smuzhiyun full-duplex; 277*4882a593Smuzhiyun }; 278*4882a593Smuzhiyun }; 279*4882a593Smuzhiyun }; 280*4882a593Smuzhiyun }; 281*4882a593Smuzhiyun }; 282*4882a593Smuzhiyun}; 283*4882a593Smuzhiyun 284*4882a593Smuzhiyun&ipu { 285*4882a593Smuzhiyun status = "disabled"; 286*4882a593Smuzhiyun}; 287*4882a593Smuzhiyun 288*4882a593Smuzhiyun&i2c2 { 289*4882a593Smuzhiyun pinctrl-names = "default"; 290*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_i2c2>; 291*4882a593Smuzhiyun status = "okay"; 292*4882a593Smuzhiyun 293*4882a593Smuzhiyun eeprom@50 { 294*4882a593Smuzhiyun compatible = "atmel,24c04"; 295*4882a593Smuzhiyun pagesize = <16>; 296*4882a593Smuzhiyun reg = <0x50>; 297*4882a593Smuzhiyun }; 298*4882a593Smuzhiyun 299*4882a593Smuzhiyun lm75@48 { 300*4882a593Smuzhiyun compatible = "national,lm75"; 301*4882a593Smuzhiyun reg = <0x48>; 302*4882a593Smuzhiyun }; 303*4882a593Smuzhiyun}; 304*4882a593Smuzhiyun 305*4882a593Smuzhiyun&uart1 { 306*4882a593Smuzhiyun pinctrl-names = "default"; 307*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_uart1>; 308*4882a593Smuzhiyun status = "okay"; 309*4882a593Smuzhiyun}; 310*4882a593Smuzhiyun 311*4882a593Smuzhiyun&uart2 { 312*4882a593Smuzhiyun pinctrl-names = "default"; 313*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_uart2>; 314*4882a593Smuzhiyun status = "okay"; 315*4882a593Smuzhiyun}; 316*4882a593Smuzhiyun 317*4882a593Smuzhiyun&uart3 { 318*4882a593Smuzhiyun pinctrl-names = "default"; 319*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_uart3>; 320*4882a593Smuzhiyun status = "okay"; 321*4882a593Smuzhiyun 322*4882a593Smuzhiyun rave-sp { 323*4882a593Smuzhiyun compatible = "zii,rave-sp-esb"; 324*4882a593Smuzhiyun current-speed = <57600>; 325*4882a593Smuzhiyun #address-cells = <1>; 326*4882a593Smuzhiyun #size-cells = <1>; 327*4882a593Smuzhiyun 328*4882a593Smuzhiyun watchdog { 329*4882a593Smuzhiyun compatible = "zii,rave-sp-watchdog-legacy"; 330*4882a593Smuzhiyun }; 331*4882a593Smuzhiyun 332*4882a593Smuzhiyun eeprom@a4 { 333*4882a593Smuzhiyun compatible = "zii,rave-sp-eeprom"; 334*4882a593Smuzhiyun reg = <0xa4 0x4000>; 335*4882a593Smuzhiyun #address-cells = <1>; 336*4882a593Smuzhiyun #size-cells = <1>; 337*4882a593Smuzhiyun zii,eeprom-name = "main-eeprom"; 338*4882a593Smuzhiyun }; 339*4882a593Smuzhiyun }; 340*4882a593Smuzhiyun}; 341*4882a593Smuzhiyun 342*4882a593Smuzhiyun&usbotg { 343*4882a593Smuzhiyun dr_mode = "host"; 344*4882a593Smuzhiyun disable-over-current; 345*4882a593Smuzhiyun phy_type = "utmi_wide"; 346*4882a593Smuzhiyun vbus-supply = <&usb_vbus>; 347*4882a593Smuzhiyun status = "okay"; 348*4882a593Smuzhiyun}; 349*4882a593Smuzhiyun 350*4882a593Smuzhiyun&usbphy0 { 351*4882a593Smuzhiyun vcc-supply = <&vusb2_reg>; 352*4882a593Smuzhiyun}; 353*4882a593Smuzhiyun 354*4882a593Smuzhiyun&vpu { 355*4882a593Smuzhiyun status = "disabled"; 356*4882a593Smuzhiyun}; 357*4882a593Smuzhiyun 358*4882a593Smuzhiyun&wdog1 { 359*4882a593Smuzhiyun status = "disabled"; 360*4882a593Smuzhiyun}; 361*4882a593Smuzhiyun 362*4882a593Smuzhiyun&iomuxc { 363*4882a593Smuzhiyun pinctrl_ecspi1: ecspi1grp { 364*4882a593Smuzhiyun fsl,pins = < 365*4882a593Smuzhiyun MX51_PAD_CSPI1_MISO__ECSPI1_MISO 0x185 366*4882a593Smuzhiyun MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI 0x185 367*4882a593Smuzhiyun MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK 0x185 368*4882a593Smuzhiyun MX51_PAD_CSPI1_SS0__GPIO4_24 0x85 369*4882a593Smuzhiyun MX51_PAD_CSPI1_SS1__GPIO4_25 0x85 370*4882a593Smuzhiyun >; 371*4882a593Smuzhiyun }; 372*4882a593Smuzhiyun 373*4882a593Smuzhiyun pinctrl_esdhc1: esdhc1grp { 374*4882a593Smuzhiyun fsl,pins = < 375*4882a593Smuzhiyun MX51_PAD_SD1_CMD__SD1_CMD 0x400020d5 376*4882a593Smuzhiyun MX51_PAD_SD1_CLK__SD1_CLK 0x20d5 377*4882a593Smuzhiyun MX51_PAD_SD1_DATA0__SD1_DATA0 0x20d5 378*4882a593Smuzhiyun MX51_PAD_SD1_DATA1__SD1_DATA1 0x20d5 379*4882a593Smuzhiyun MX51_PAD_SD1_DATA2__SD1_DATA2 0x20d5 380*4882a593Smuzhiyun MX51_PAD_SD1_DATA3__SD1_DATA3 0x20d5 381*4882a593Smuzhiyun MX51_PAD_SD2_DATA0__SD1_DAT4 0x20d5 382*4882a593Smuzhiyun MX51_PAD_SD2_DATA1__SD1_DAT5 0x20d5 383*4882a593Smuzhiyun MX51_PAD_SD2_DATA2__SD1_DAT6 0x20d5 384*4882a593Smuzhiyun MX51_PAD_SD2_DATA3__SD1_DAT7 0x20d5 385*4882a593Smuzhiyun >; 386*4882a593Smuzhiyun }; 387*4882a593Smuzhiyun 388*4882a593Smuzhiyun pinctrl_esdhc4: esdhc4grp { 389*4882a593Smuzhiyun fsl,pins = < 390*4882a593Smuzhiyun MX51_PAD_NANDF_RB1__SD4_CMD 0x400020d5 391*4882a593Smuzhiyun MX51_PAD_NANDF_CS2__SD4_CLK 0x20d5 392*4882a593Smuzhiyun MX51_PAD_NANDF_CS3__SD4_DAT0 0x20d5 393*4882a593Smuzhiyun MX51_PAD_NANDF_CS4__SD4_DAT1 0x20d5 394*4882a593Smuzhiyun MX51_PAD_NANDF_CS5__SD4_DAT2 0x20d5 395*4882a593Smuzhiyun MX51_PAD_NANDF_CS6__SD4_DAT3 0x20d5 396*4882a593Smuzhiyun MX51_PAD_NANDF_D0__GPIO4_8 0x100 397*4882a593Smuzhiyun >; 398*4882a593Smuzhiyun }; 399*4882a593Smuzhiyun 400*4882a593Smuzhiyun pinctrl_fec: fecgrp { 401*4882a593Smuzhiyun fsl,pins = < 402*4882a593Smuzhiyun MX51_PAD_DISP2_DAT15__FEC_TDATA0 0x2004 403*4882a593Smuzhiyun MX51_PAD_DISP2_DAT6__FEC_TDATA1 0x2004 404*4882a593Smuzhiyun MX51_PAD_DISP2_DAT7__FEC_TDATA2 0x2004 405*4882a593Smuzhiyun MX51_PAD_DISP2_DAT8__FEC_TDATA3 0x2004 406*4882a593Smuzhiyun MX51_PAD_DISP2_DAT9__FEC_TX_EN 0x2004 407*4882a593Smuzhiyun MX51_PAD_DISP2_DAT10__FEC_COL 0x0180 408*4882a593Smuzhiyun MX51_PAD_DISP2_DAT11__FEC_RX_CLK 0x0180 409*4882a593Smuzhiyun MX51_PAD_DISP2_DAT12__FEC_RX_DV 0x20a4 410*4882a593Smuzhiyun 411*4882a593Smuzhiyun MX51_PAD_DISP2_DAT13__FEC_TX_CLK 0x2180 412*4882a593Smuzhiyun MX51_PAD_DISP2_DAT14__FEC_RDATA0 0x2180 413*4882a593Smuzhiyun MX51_PAD_DI2_DISP_CLK__FEC_RDATA1 0x0085 414*4882a593Smuzhiyun MX51_PAD_DI_GP4__FEC_RDATA2 0x0085 415*4882a593Smuzhiyun MX51_PAD_DISP2_DAT0__FEC_RDATA3 0x0085 416*4882a593Smuzhiyun MX51_PAD_DI2_PIN2__FEC_MDC 0x2004 417*4882a593Smuzhiyun MX51_PAD_DI2_PIN3__FEC_MDIO 0x01f5 418*4882a593Smuzhiyun MX51_PAD_DI2_PIN4__FEC_CRS 0x0180 419*4882a593Smuzhiyun >; 420*4882a593Smuzhiyun }; 421*4882a593Smuzhiyun 422*4882a593Smuzhiyun pinctrl_i2c2: i2c2grp { 423*4882a593Smuzhiyun fsl,pins = < 424*4882a593Smuzhiyun MX51_PAD_KEY_COL4__I2C2_SCL 0x400001ed 425*4882a593Smuzhiyun MX51_PAD_KEY_COL5__I2C2_SDA 0x400001ed 426*4882a593Smuzhiyun >; 427*4882a593Smuzhiyun }; 428*4882a593Smuzhiyun 429*4882a593Smuzhiyun pinctrl_pmic: pmicgrp { 430*4882a593Smuzhiyun fsl,pins = < 431*4882a593Smuzhiyun MX51_PAD_GPIO1_4__GPIO1_4 0x85 432*4882a593Smuzhiyun MX51_PAD_GPIO1_8__GPIO1_8 0xe5 433*4882a593Smuzhiyun >; 434*4882a593Smuzhiyun }; 435*4882a593Smuzhiyun 436*4882a593Smuzhiyun pinctrl_switch: switchgrp { 437*4882a593Smuzhiyun fsl,pins = < 438*4882a593Smuzhiyun MX51_PAD_AUD3_BB_CK__GPIO4_20 0xc5 439*4882a593Smuzhiyun >; 440*4882a593Smuzhiyun }; 441*4882a593Smuzhiyun 442*4882a593Smuzhiyun pinctrl_uart1: uart1grp { 443*4882a593Smuzhiyun fsl,pins = < 444*4882a593Smuzhiyun MX51_PAD_UART1_RXD__UART1_RXD 0x1c5 445*4882a593Smuzhiyun MX51_PAD_UART1_TXD__UART1_TXD 0x1c5 446*4882a593Smuzhiyun MX51_PAD_UART1_RTS__UART1_RTS 0x1c5 447*4882a593Smuzhiyun MX51_PAD_UART1_CTS__UART1_CTS 0x1c5 448*4882a593Smuzhiyun >; 449*4882a593Smuzhiyun }; 450*4882a593Smuzhiyun 451*4882a593Smuzhiyun pinctrl_uart2: uart2grp { 452*4882a593Smuzhiyun fsl,pins = < 453*4882a593Smuzhiyun MX51_PAD_UART2_RXD__UART2_RXD 0x1c5 454*4882a593Smuzhiyun MX51_PAD_UART2_TXD__UART2_TXD 0x1c5 455*4882a593Smuzhiyun MX51_PAD_USBH1_DATA0__UART2_CTS 0x1c5 456*4882a593Smuzhiyun MX51_PAD_USBH1_DATA3__UART2_RTS 0x1c5 457*4882a593Smuzhiyun >; 458*4882a593Smuzhiyun }; 459*4882a593Smuzhiyun 460*4882a593Smuzhiyun pinctrl_uart3: uart3grp { 461*4882a593Smuzhiyun fsl,pins = < 462*4882a593Smuzhiyun MX51_PAD_UART3_RXD__UART3_RXD 0x1c5 463*4882a593Smuzhiyun MX51_PAD_UART3_TXD__UART3_TXD 0x1c5 464*4882a593Smuzhiyun >; 465*4882a593Smuzhiyun }; 466*4882a593Smuzhiyun 467*4882a593Smuzhiyun pinctrl_usb_mmc_reset: usbmmcgrp { 468*4882a593Smuzhiyun fsl,pins = < 469*4882a593Smuzhiyun MX51_PAD_AUD3_BB_RXD__GPIO4_19 0x100 470*4882a593Smuzhiyun >; 471*4882a593Smuzhiyun }; 472*4882a593Smuzhiyun}; 473