xref: /OK3568_Linux_fs/kernel/scripts/dtc/include-prefixes/arm/imx51-eukrea-mbimxsd51-baseboard.dts (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun// SPDX-License-Identifier: GPL-2.0-or-later
2*4882a593Smuzhiyun/*
3*4882a593Smuzhiyun * Copyright 2013 Eukréa Electromatique <denis@eukrea.com>
4*4882a593Smuzhiyun */
5*4882a593Smuzhiyun
6*4882a593Smuzhiyun/dts-v1/;
7*4882a593Smuzhiyun#include "imx51-eukrea-cpuimx51.dtsi"
8*4882a593Smuzhiyun#include <dt-bindings/gpio/gpio.h>
9*4882a593Smuzhiyun
10*4882a593Smuzhiyun/ {
11*4882a593Smuzhiyun	model = "Eukrea CPUIMX51";
12*4882a593Smuzhiyun	compatible = "eukrea,mbimxsd51","eukrea,cpuimx51", "fsl,imx51";
13*4882a593Smuzhiyun
14*4882a593Smuzhiyun	clocks {
15*4882a593Smuzhiyun		clk24M: can_clock {
16*4882a593Smuzhiyun			compatible = "fixed-clock";
17*4882a593Smuzhiyun			#clock-cells = <0>;
18*4882a593Smuzhiyun			clock-frequency = <24000000>;
19*4882a593Smuzhiyun		};
20*4882a593Smuzhiyun	};
21*4882a593Smuzhiyun
22*4882a593Smuzhiyun	gpio_keys {
23*4882a593Smuzhiyun		compatible = "gpio-keys";
24*4882a593Smuzhiyun		pinctrl-names = "default";
25*4882a593Smuzhiyun		pinctrl-0 = <&pinctrl_gpiokeys_1>;
26*4882a593Smuzhiyun
27*4882a593Smuzhiyun		button-1 {
28*4882a593Smuzhiyun			label = "BP1";
29*4882a593Smuzhiyun			gpios = <&gpio3 31 GPIO_ACTIVE_LOW>;
30*4882a593Smuzhiyun			linux,code = <256>;
31*4882a593Smuzhiyun			wakeup-source;
32*4882a593Smuzhiyun			linux,input-type = <1>;
33*4882a593Smuzhiyun		};
34*4882a593Smuzhiyun	};
35*4882a593Smuzhiyun
36*4882a593Smuzhiyun	leds {
37*4882a593Smuzhiyun		compatible = "gpio-leds";
38*4882a593Smuzhiyun		pinctrl-names = "default";
39*4882a593Smuzhiyun		pinctrl-0 = <&pinctrl_gpioled>;
40*4882a593Smuzhiyun
41*4882a593Smuzhiyun		led1 {
42*4882a593Smuzhiyun			label = "led1";
43*4882a593Smuzhiyun			gpios = <&gpio3 30 GPIO_ACTIVE_LOW>;
44*4882a593Smuzhiyun			linux,default-trigger = "heartbeat";
45*4882a593Smuzhiyun		};
46*4882a593Smuzhiyun	};
47*4882a593Smuzhiyun
48*4882a593Smuzhiyun	regulators {
49*4882a593Smuzhiyun		compatible = "simple-bus";
50*4882a593Smuzhiyun		#address-cells = <1>;
51*4882a593Smuzhiyun		#size-cells = <0>;
52*4882a593Smuzhiyun
53*4882a593Smuzhiyun		reg_can: regulator@0 {
54*4882a593Smuzhiyun			compatible = "regulator-fixed";
55*4882a593Smuzhiyun			reg = <0>;
56*4882a593Smuzhiyun			regulator-name = "CAN_RST";
57*4882a593Smuzhiyun			regulator-min-microvolt = <3300000>;
58*4882a593Smuzhiyun			regulator-max-microvolt = <3300000>;
59*4882a593Smuzhiyun			gpio = <&gpio4 15 GPIO_ACTIVE_HIGH>;
60*4882a593Smuzhiyun			startup-delay-us = <20000>;
61*4882a593Smuzhiyun			enable-active-high;
62*4882a593Smuzhiyun		};
63*4882a593Smuzhiyun	};
64*4882a593Smuzhiyun
65*4882a593Smuzhiyun	sound {
66*4882a593Smuzhiyun		compatible = "eukrea,asoc-tlv320";
67*4882a593Smuzhiyun		eukrea,model = "imx51-eukrea-tlv320aic23";
68*4882a593Smuzhiyun		ssi-controller = <&ssi2>;
69*4882a593Smuzhiyun		fsl,mux-int-port = <2>;
70*4882a593Smuzhiyun		fsl,mux-ext-port = <3>;
71*4882a593Smuzhiyun	};
72*4882a593Smuzhiyun
73*4882a593Smuzhiyun	usbphy1: usbphy1 {
74*4882a593Smuzhiyun		compatible = "usb-nop-xceiv";
75*4882a593Smuzhiyun		clocks = <&clks IMX5_CLK_USB_PHY_GATE>;
76*4882a593Smuzhiyun		clock-names = "main_clk";
77*4882a593Smuzhiyun		clock-frequency = <19200000>;
78*4882a593Smuzhiyun		#phy-cells = <0>;
79*4882a593Smuzhiyun	};
80*4882a593Smuzhiyun};
81*4882a593Smuzhiyun
82*4882a593Smuzhiyun&audmux {
83*4882a593Smuzhiyun	pinctrl-names = "default";
84*4882a593Smuzhiyun	pinctrl-0 = <&pinctrl_audmux>;
85*4882a593Smuzhiyun	status = "okay";
86*4882a593Smuzhiyun};
87*4882a593Smuzhiyun
88*4882a593Smuzhiyun&esdhc1 {
89*4882a593Smuzhiyun	pinctrl-names = "default";
90*4882a593Smuzhiyun	pinctrl-0 = <&pinctrl_esdhc1 &pinctrl_esdhc1_cd>;
91*4882a593Smuzhiyun	cd-gpios = <&gpio1 0 GPIO_ACTIVE_LOW>;
92*4882a593Smuzhiyun	status = "okay";
93*4882a593Smuzhiyun};
94*4882a593Smuzhiyun
95*4882a593Smuzhiyun&ecspi1 {
96*4882a593Smuzhiyun	pinctrl-names = "default";
97*4882a593Smuzhiyun	pinctrl-0 = <&pinctrl_ecspi1>;
98*4882a593Smuzhiyun	cs-gpios = <&gpio4 24 GPIO_ACTIVE_LOW>;
99*4882a593Smuzhiyun	status = "okay";
100*4882a593Smuzhiyun
101*4882a593Smuzhiyun	can0: can@0 {
102*4882a593Smuzhiyun		pinctrl-names = "default";
103*4882a593Smuzhiyun		pinctrl-0 = <&pinctrl_can>;
104*4882a593Smuzhiyun		compatible = "microchip,mcp2515";
105*4882a593Smuzhiyun		reg = <0>;
106*4882a593Smuzhiyun		clocks = <&clk24M>;
107*4882a593Smuzhiyun		spi-max-frequency = <10000000>;
108*4882a593Smuzhiyun		interrupt-parent = <&gpio1>;
109*4882a593Smuzhiyun		interrupts = <1 IRQ_TYPE_EDGE_FALLING>;
110*4882a593Smuzhiyun		vdd-supply = <&reg_can>;
111*4882a593Smuzhiyun	};
112*4882a593Smuzhiyun};
113*4882a593Smuzhiyun
114*4882a593Smuzhiyun&i2c1 {
115*4882a593Smuzhiyun	tlv320aic23: codec@1a {
116*4882a593Smuzhiyun		compatible = "ti,tlv320aic23";
117*4882a593Smuzhiyun		reg = <0x1a>;
118*4882a593Smuzhiyun	};
119*4882a593Smuzhiyun};
120*4882a593Smuzhiyun
121*4882a593Smuzhiyun&iomuxc {
122*4882a593Smuzhiyun	imx51-eukrea {
123*4882a593Smuzhiyun		pinctrl_audmux: audmuxgrp {
124*4882a593Smuzhiyun			fsl,pins = <
125*4882a593Smuzhiyun				MX51_PAD_AUD3_BB_TXD__AUD3_TXD		0x80000000
126*4882a593Smuzhiyun				MX51_PAD_AUD3_BB_RXD__AUD3_RXD		0x80000000
127*4882a593Smuzhiyun				MX51_PAD_AUD3_BB_CK__AUD3_TXC		0x80000000
128*4882a593Smuzhiyun				MX51_PAD_AUD3_BB_FS__AUD3_TXFS		0x80000000
129*4882a593Smuzhiyun			>;
130*4882a593Smuzhiyun		};
131*4882a593Smuzhiyun
132*4882a593Smuzhiyun
133*4882a593Smuzhiyun		pinctrl_can: cangrp {
134*4882a593Smuzhiyun			fsl,pins = <
135*4882a593Smuzhiyun				MX51_PAD_CSI2_PIXCLK__GPIO4_15		0x80000000	/* nReset */
136*4882a593Smuzhiyun				MX51_PAD_GPIO1_1__GPIO1_1		0x80000000	/* IRQ */
137*4882a593Smuzhiyun			>;
138*4882a593Smuzhiyun		};
139*4882a593Smuzhiyun
140*4882a593Smuzhiyun		pinctrl_ecspi1: ecspi1grp {
141*4882a593Smuzhiyun			fsl,pins = <
142*4882a593Smuzhiyun				MX51_PAD_CSPI1_MISO__ECSPI1_MISO	0x185
143*4882a593Smuzhiyun				MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI	0x185
144*4882a593Smuzhiyun				MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK	0x185
145*4882a593Smuzhiyun				MX51_PAD_CSPI1_SS0__GPIO4_24		0x80000000 	/* CS0 */
146*4882a593Smuzhiyun			>;
147*4882a593Smuzhiyun		};
148*4882a593Smuzhiyun
149*4882a593Smuzhiyun		pinctrl_esdhc1: esdhc1grp {
150*4882a593Smuzhiyun			fsl,pins = <
151*4882a593Smuzhiyun				MX51_PAD_SD1_CMD__SD1_CMD		0x400020d5
152*4882a593Smuzhiyun				MX51_PAD_SD1_CLK__SD1_CLK		0x20d5
153*4882a593Smuzhiyun				MX51_PAD_SD1_DATA0__SD1_DATA0		0x20d5
154*4882a593Smuzhiyun				MX51_PAD_SD1_DATA1__SD1_DATA1		0x20d5
155*4882a593Smuzhiyun				MX51_PAD_SD1_DATA2__SD1_DATA2		0x20d5
156*4882a593Smuzhiyun				MX51_PAD_SD1_DATA3__SD1_DATA3		0x20d5
157*4882a593Smuzhiyun			>;
158*4882a593Smuzhiyun		};
159*4882a593Smuzhiyun
160*4882a593Smuzhiyun		pinctrl_uart1: uart1grp {
161*4882a593Smuzhiyun			fsl,pins = <
162*4882a593Smuzhiyun				MX51_PAD_UART1_RXD__UART1_RXD		0x1c5
163*4882a593Smuzhiyun				MX51_PAD_UART1_TXD__UART1_TXD		0x1c5
164*4882a593Smuzhiyun			>;
165*4882a593Smuzhiyun		};
166*4882a593Smuzhiyun
167*4882a593Smuzhiyun		pinctrl_uart3: uart3grp {
168*4882a593Smuzhiyun			fsl,pins = <
169*4882a593Smuzhiyun				MX51_PAD_UART3_RXD__UART3_RXD		0x1c5
170*4882a593Smuzhiyun				MX51_PAD_UART3_TXD__UART3_TXD		0x1c5
171*4882a593Smuzhiyun			>;
172*4882a593Smuzhiyun		};
173*4882a593Smuzhiyun
174*4882a593Smuzhiyun		pinctrl_uart3_rtscts: uart3rtsctsgrp {
175*4882a593Smuzhiyun			fsl,pins = <
176*4882a593Smuzhiyun				MX51_PAD_KEY_COL4__UART3_RTS		0x1c5
177*4882a593Smuzhiyun				MX51_PAD_KEY_COL5__UART3_CTS		0x1c5
178*4882a593Smuzhiyun			>;
179*4882a593Smuzhiyun		};
180*4882a593Smuzhiyun
181*4882a593Smuzhiyun		pinctrl_backlight_1: backlightgrp-1 {
182*4882a593Smuzhiyun			fsl,pins = <
183*4882a593Smuzhiyun				MX51_PAD_DI1_D1_CS__GPIO3_4 0x1f5
184*4882a593Smuzhiyun			>;
185*4882a593Smuzhiyun		};
186*4882a593Smuzhiyun
187*4882a593Smuzhiyun		pinctrl_esdhc1_cd: esdhc1_cd {
188*4882a593Smuzhiyun			fsl,pins = <
189*4882a593Smuzhiyun				MX51_PAD_GPIO1_0__GPIO1_0 0xd5
190*4882a593Smuzhiyun			>;
191*4882a593Smuzhiyun		};
192*4882a593Smuzhiyun
193*4882a593Smuzhiyun		pinctrl_gpiokeys_1: gpiokeysgrp-1 {
194*4882a593Smuzhiyun			fsl,pins = <
195*4882a593Smuzhiyun				MX51_PAD_NANDF_D9__GPIO3_31 0x1f5
196*4882a593Smuzhiyun			>;
197*4882a593Smuzhiyun		};
198*4882a593Smuzhiyun
199*4882a593Smuzhiyun		pinctrl_gpioled: gpioledgrp-1 {
200*4882a593Smuzhiyun			fsl,pins = <
201*4882a593Smuzhiyun				MX51_PAD_NANDF_D10__GPIO3_30 0x80000000
202*4882a593Smuzhiyun			>;
203*4882a593Smuzhiyun		};
204*4882a593Smuzhiyun
205*4882a593Smuzhiyun		pinctrl_reg_lcd_3v3: reg_lcd_3v3 {
206*4882a593Smuzhiyun			fsl,pins = <
207*4882a593Smuzhiyun				MX51_PAD_CSI1_D9__GPIO3_13 0x1f5
208*4882a593Smuzhiyun			>;
209*4882a593Smuzhiyun		};
210*4882a593Smuzhiyun
211*4882a593Smuzhiyun		pinctrl_usbh1: usbh1grp {
212*4882a593Smuzhiyun			fsl,pins = <
213*4882a593Smuzhiyun				MX51_PAD_USBH1_CLK__USBH1_CLK     0x1e5
214*4882a593Smuzhiyun				MX51_PAD_USBH1_DIR__USBH1_DIR     0x1e5
215*4882a593Smuzhiyun				MX51_PAD_USBH1_NXT__USBH1_NXT     0x1e5
216*4882a593Smuzhiyun				MX51_PAD_USBH1_DATA0__USBH1_DATA0 0x1e5
217*4882a593Smuzhiyun				MX51_PAD_USBH1_DATA1__USBH1_DATA1 0x1e5
218*4882a593Smuzhiyun				MX51_PAD_USBH1_DATA2__USBH1_DATA2 0x1e5
219*4882a593Smuzhiyun				MX51_PAD_USBH1_DATA3__USBH1_DATA3 0x1e5
220*4882a593Smuzhiyun				MX51_PAD_USBH1_DATA4__USBH1_DATA4 0x1e5
221*4882a593Smuzhiyun				MX51_PAD_USBH1_DATA5__USBH1_DATA5 0x1e5
222*4882a593Smuzhiyun				MX51_PAD_USBH1_DATA6__USBH1_DATA6 0x1e5
223*4882a593Smuzhiyun				MX51_PAD_USBH1_DATA7__USBH1_DATA7 0x1e5
224*4882a593Smuzhiyun				MX51_PAD_USBH1_STP__USBH1_STP     0x1e5
225*4882a593Smuzhiyun			>;
226*4882a593Smuzhiyun		};
227*4882a593Smuzhiyun
228*4882a593Smuzhiyun		pinctrl_usbh1_vbus: usbh1-vbusgrp {
229*4882a593Smuzhiyun			fsl,pins = <
230*4882a593Smuzhiyun				MX51_PAD_EIM_CS3__GPIO2_28 0x1f5
231*4882a593Smuzhiyun			>;
232*4882a593Smuzhiyun		};
233*4882a593Smuzhiyun	};
234*4882a593Smuzhiyun};
235*4882a593Smuzhiyun
236*4882a593Smuzhiyun&ssi2 {
237*4882a593Smuzhiyun	codec-handle = <&tlv320aic23>;
238*4882a593Smuzhiyun	status = "okay";
239*4882a593Smuzhiyun};
240*4882a593Smuzhiyun
241*4882a593Smuzhiyun&uart1 {
242*4882a593Smuzhiyun	pinctrl-names = "default";
243*4882a593Smuzhiyun	pinctrl-0 = <&pinctrl_uart1>;
244*4882a593Smuzhiyun	uart-has-rtscts;
245*4882a593Smuzhiyun	status = "okay";
246*4882a593Smuzhiyun};
247*4882a593Smuzhiyun
248*4882a593Smuzhiyun&uart3 {
249*4882a593Smuzhiyun	pinctrl-names = "default";
250*4882a593Smuzhiyun	pinctrl-0 = <&pinctrl_uart3 &pinctrl_uart3_rtscts>;
251*4882a593Smuzhiyun	uart-has-rtscts;
252*4882a593Smuzhiyun	status = "okay";
253*4882a593Smuzhiyun};
254*4882a593Smuzhiyun
255*4882a593Smuzhiyun&usbh1 {
256*4882a593Smuzhiyun	pinctrl-names = "default";
257*4882a593Smuzhiyun	pinctrl-0 = <&pinctrl_usbh1>;
258*4882a593Smuzhiyun	fsl,usbphy = <&usbphy1>;
259*4882a593Smuzhiyun	dr_mode = "host";
260*4882a593Smuzhiyun	phy_type = "ulpi";
261*4882a593Smuzhiyun	status = "okay";
262*4882a593Smuzhiyun};
263*4882a593Smuzhiyun
264*4882a593Smuzhiyun&usbotg {
265*4882a593Smuzhiyun	dr_mode = "otg";
266*4882a593Smuzhiyun	phy_type = "utmi_wide";
267*4882a593Smuzhiyun	status = "okay";
268*4882a593Smuzhiyun};
269*4882a593Smuzhiyun
270*4882a593Smuzhiyun&usbphy0 {
271*4882a593Smuzhiyun	pinctrl-names = "default";
272*4882a593Smuzhiyun	pinctrl-0 = <&pinctrl_usbh1_vbus>;
273*4882a593Smuzhiyun	reset-gpios = <&gpio2 28 GPIO_ACTIVE_LOW>;
274*4882a593Smuzhiyun};
275