1*4882a593Smuzhiyun// SPDX-License-Identifier: GPL-2.0+ 2*4882a593Smuzhiyun// 3*4882a593Smuzhiyun// Copyright 2011 Freescale Semiconductor, Inc. 4*4882a593Smuzhiyun// Copyright 2011 Linaro Ltd. 5*4882a593Smuzhiyun 6*4882a593Smuzhiyun/dts-v1/; 7*4882a593Smuzhiyun#include "imx51.dtsi" 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun/ { 10*4882a593Smuzhiyun model = "Freescale i.MX51 Babbage Board"; 11*4882a593Smuzhiyun compatible = "fsl,imx51-babbage", "fsl,imx51"; 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun chosen { 14*4882a593Smuzhiyun stdout-path = &uart1; 15*4882a593Smuzhiyun }; 16*4882a593Smuzhiyun 17*4882a593Smuzhiyun memory@90000000 { 18*4882a593Smuzhiyun device_type = "memory"; 19*4882a593Smuzhiyun reg = <0x90000000 0x20000000>; 20*4882a593Smuzhiyun }; 21*4882a593Smuzhiyun 22*4882a593Smuzhiyun ckih1 { 23*4882a593Smuzhiyun clock-frequency = <22579200>; 24*4882a593Smuzhiyun }; 25*4882a593Smuzhiyun 26*4882a593Smuzhiyun clk_osc: clk-osc { 27*4882a593Smuzhiyun compatible = "fixed-clock"; 28*4882a593Smuzhiyun #clock-cells = <0>; 29*4882a593Smuzhiyun clock-frequency = <26000000>; 30*4882a593Smuzhiyun }; 31*4882a593Smuzhiyun 32*4882a593Smuzhiyun clk_osc_gate: clk-osc-gate { 33*4882a593Smuzhiyun compatible = "gpio-gate-clock"; 34*4882a593Smuzhiyun pinctrl-names = "default"; 35*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_clk26mhz_osc>; 36*4882a593Smuzhiyun clocks = <&clk_osc>; 37*4882a593Smuzhiyun #clock-cells = <0>; 38*4882a593Smuzhiyun enable-gpios = <&gpio3 1 GPIO_ACTIVE_HIGH>; 39*4882a593Smuzhiyun }; 40*4882a593Smuzhiyun 41*4882a593Smuzhiyun clk_audio: clk-audio { 42*4882a593Smuzhiyun compatible = "gpio-gate-clock"; 43*4882a593Smuzhiyun pinctrl-names = "default"; 44*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_clk26mhz_audio>; 45*4882a593Smuzhiyun clocks = <&clk_osc_gate>; 46*4882a593Smuzhiyun #clock-cells = <0>; 47*4882a593Smuzhiyun enable-gpios = <&gpio4 26 GPIO_ACTIVE_LOW>; 48*4882a593Smuzhiyun }; 49*4882a593Smuzhiyun 50*4882a593Smuzhiyun clk_usb: clk-usb { 51*4882a593Smuzhiyun compatible = "gpio-gate-clock"; 52*4882a593Smuzhiyun pinctrl-names = "default"; 53*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_clk26mhz_usb>; 54*4882a593Smuzhiyun clocks = <&clk_osc_gate>; 55*4882a593Smuzhiyun #clock-cells = <0>; 56*4882a593Smuzhiyun enable-gpios = <&gpio2 1 GPIO_ACTIVE_LOW>; 57*4882a593Smuzhiyun }; 58*4882a593Smuzhiyun 59*4882a593Smuzhiyun display1: disp1 { 60*4882a593Smuzhiyun compatible = "fsl,imx-parallel-display"; 61*4882a593Smuzhiyun #address-cells = <1>; 62*4882a593Smuzhiyun #size-cells = <0>; 63*4882a593Smuzhiyun interface-pix-fmt = "rgb24"; 64*4882a593Smuzhiyun pinctrl-names = "default"; 65*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_ipu_disp1>; 66*4882a593Smuzhiyun 67*4882a593Smuzhiyun port@0 { 68*4882a593Smuzhiyun reg = <0>; 69*4882a593Smuzhiyun 70*4882a593Smuzhiyun display0_in: endpoint { 71*4882a593Smuzhiyun remote-endpoint = <&ipu_di0_disp1>; 72*4882a593Smuzhiyun }; 73*4882a593Smuzhiyun }; 74*4882a593Smuzhiyun 75*4882a593Smuzhiyun port@1 { 76*4882a593Smuzhiyun reg = <1>; 77*4882a593Smuzhiyun 78*4882a593Smuzhiyun parallel_display_out: endpoint { 79*4882a593Smuzhiyun remote-endpoint = <&tfp410_in>; 80*4882a593Smuzhiyun }; 81*4882a593Smuzhiyun }; 82*4882a593Smuzhiyun }; 83*4882a593Smuzhiyun 84*4882a593Smuzhiyun display2: disp2 { 85*4882a593Smuzhiyun compatible = "fsl,imx-parallel-display"; 86*4882a593Smuzhiyun interface-pix-fmt = "rgb565"; 87*4882a593Smuzhiyun pinctrl-names = "default"; 88*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_ipu_disp2>; 89*4882a593Smuzhiyun status = "disabled"; 90*4882a593Smuzhiyun display-timings { 91*4882a593Smuzhiyun native-mode = <&timing1>; 92*4882a593Smuzhiyun timing1: claawvga { 93*4882a593Smuzhiyun clock-frequency = <27000000>; 94*4882a593Smuzhiyun hactive = <800>; 95*4882a593Smuzhiyun vactive = <480>; 96*4882a593Smuzhiyun hback-porch = <40>; 97*4882a593Smuzhiyun hfront-porch = <60>; 98*4882a593Smuzhiyun vback-porch = <10>; 99*4882a593Smuzhiyun vfront-porch = <10>; 100*4882a593Smuzhiyun hsync-len = <20>; 101*4882a593Smuzhiyun vsync-len = <10>; 102*4882a593Smuzhiyun hsync-active = <0>; 103*4882a593Smuzhiyun vsync-active = <0>; 104*4882a593Smuzhiyun de-active = <1>; 105*4882a593Smuzhiyun pixelclk-active = <0>; 106*4882a593Smuzhiyun }; 107*4882a593Smuzhiyun }; 108*4882a593Smuzhiyun 109*4882a593Smuzhiyun port { 110*4882a593Smuzhiyun display1_in: endpoint { 111*4882a593Smuzhiyun remote-endpoint = <&ipu_di1_disp2>; 112*4882a593Smuzhiyun }; 113*4882a593Smuzhiyun }; 114*4882a593Smuzhiyun }; 115*4882a593Smuzhiyun 116*4882a593Smuzhiyun dvi-connector { 117*4882a593Smuzhiyun compatible = "dvi-connector"; 118*4882a593Smuzhiyun digital; 119*4882a593Smuzhiyun 120*4882a593Smuzhiyun port { 121*4882a593Smuzhiyun dvi_connector_in: endpoint { 122*4882a593Smuzhiyun remote-endpoint = <&tfp410_out>; 123*4882a593Smuzhiyun }; 124*4882a593Smuzhiyun }; 125*4882a593Smuzhiyun }; 126*4882a593Smuzhiyun 127*4882a593Smuzhiyun dvi-encoder { 128*4882a593Smuzhiyun compatible = "ti,tfp410"; 129*4882a593Smuzhiyun 130*4882a593Smuzhiyun ports { 131*4882a593Smuzhiyun #address-cells = <1>; 132*4882a593Smuzhiyun #size-cells = <0>; 133*4882a593Smuzhiyun 134*4882a593Smuzhiyun port@0 { 135*4882a593Smuzhiyun reg = <0>; 136*4882a593Smuzhiyun 137*4882a593Smuzhiyun tfp410_in: endpoint { 138*4882a593Smuzhiyun remote-endpoint = <¶llel_display_out>; 139*4882a593Smuzhiyun }; 140*4882a593Smuzhiyun }; 141*4882a593Smuzhiyun 142*4882a593Smuzhiyun port@1 { 143*4882a593Smuzhiyun reg = <1>; 144*4882a593Smuzhiyun 145*4882a593Smuzhiyun tfp410_out: endpoint { 146*4882a593Smuzhiyun remote-endpoint = <&dvi_connector_in>; 147*4882a593Smuzhiyun }; 148*4882a593Smuzhiyun }; 149*4882a593Smuzhiyun }; 150*4882a593Smuzhiyun }; 151*4882a593Smuzhiyun 152*4882a593Smuzhiyun gpio-keys { 153*4882a593Smuzhiyun compatible = "gpio-keys"; 154*4882a593Smuzhiyun pinctrl-names = "default"; 155*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_gpio_keys>; 156*4882a593Smuzhiyun 157*4882a593Smuzhiyun power { 158*4882a593Smuzhiyun label = "Power Button"; 159*4882a593Smuzhiyun gpios = <&gpio2 21 GPIO_ACTIVE_HIGH>; 160*4882a593Smuzhiyun linux,code = <KEY_POWER>; 161*4882a593Smuzhiyun wakeup-source; 162*4882a593Smuzhiyun }; 163*4882a593Smuzhiyun }; 164*4882a593Smuzhiyun 165*4882a593Smuzhiyun leds { 166*4882a593Smuzhiyun compatible = "gpio-leds"; 167*4882a593Smuzhiyun pinctrl-names = "default"; 168*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_gpio_leds>; 169*4882a593Smuzhiyun 170*4882a593Smuzhiyun led-diagnostic { 171*4882a593Smuzhiyun label = "diagnostic"; 172*4882a593Smuzhiyun gpios = <&gpio2 6 GPIO_ACTIVE_HIGH>; 173*4882a593Smuzhiyun }; 174*4882a593Smuzhiyun }; 175*4882a593Smuzhiyun 176*4882a593Smuzhiyun regulators { 177*4882a593Smuzhiyun compatible = "simple-bus"; 178*4882a593Smuzhiyun #address-cells = <1>; 179*4882a593Smuzhiyun #size-cells = <0>; 180*4882a593Smuzhiyun 181*4882a593Smuzhiyun reg_hub_reset: regulator@0 { 182*4882a593Smuzhiyun compatible = "regulator-fixed"; 183*4882a593Smuzhiyun pinctrl-names = "default"; 184*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_usbotgreg>; 185*4882a593Smuzhiyun reg = <0>; 186*4882a593Smuzhiyun regulator-name = "hub_reset"; 187*4882a593Smuzhiyun regulator-min-microvolt = <5000000>; 188*4882a593Smuzhiyun regulator-max-microvolt = <5000000>; 189*4882a593Smuzhiyun gpio = <&gpio1 7 GPIO_ACTIVE_HIGH>; 190*4882a593Smuzhiyun enable-active-high; 191*4882a593Smuzhiyun }; 192*4882a593Smuzhiyun }; 193*4882a593Smuzhiyun 194*4882a593Smuzhiyun sound { 195*4882a593Smuzhiyun compatible = "fsl,imx51-babbage-sgtl5000", 196*4882a593Smuzhiyun "fsl,imx-audio-sgtl5000"; 197*4882a593Smuzhiyun model = "imx51-babbage-sgtl5000"; 198*4882a593Smuzhiyun ssi-controller = <&ssi2>; 199*4882a593Smuzhiyun audio-codec = <&sgtl5000>; 200*4882a593Smuzhiyun audio-routing = 201*4882a593Smuzhiyun "MIC_IN", "Mic Jack", 202*4882a593Smuzhiyun "Mic Jack", "Mic Bias", 203*4882a593Smuzhiyun "Headphone Jack", "HP_OUT"; 204*4882a593Smuzhiyun mux-int-port = <2>; 205*4882a593Smuzhiyun mux-ext-port = <3>; 206*4882a593Smuzhiyun }; 207*4882a593Smuzhiyun 208*4882a593Smuzhiyun usbphy1: usbphy1 { 209*4882a593Smuzhiyun compatible = "usb-nop-xceiv"; 210*4882a593Smuzhiyun pinctrl-names = "default"; 211*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_usbh1reg>; 212*4882a593Smuzhiyun clocks = <&clk_usb>; 213*4882a593Smuzhiyun clock-names = "main_clk"; 214*4882a593Smuzhiyun reset-gpios = <&gpio2 5 GPIO_ACTIVE_LOW>; 215*4882a593Smuzhiyun vcc-supply = <&vusb_reg>; 216*4882a593Smuzhiyun #phy-cells = <0>; 217*4882a593Smuzhiyun }; 218*4882a593Smuzhiyun}; 219*4882a593Smuzhiyun 220*4882a593Smuzhiyun&audmux { 221*4882a593Smuzhiyun pinctrl-names = "default"; 222*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_audmux>; 223*4882a593Smuzhiyun status = "okay"; 224*4882a593Smuzhiyun}; 225*4882a593Smuzhiyun 226*4882a593Smuzhiyun&ecspi1 { 227*4882a593Smuzhiyun pinctrl-names = "default"; 228*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_ecspi1>; 229*4882a593Smuzhiyun cs-gpios = <&gpio4 24 GPIO_ACTIVE_HIGH>, 230*4882a593Smuzhiyun <&gpio4 25 GPIO_ACTIVE_LOW>; 231*4882a593Smuzhiyun status = "okay"; 232*4882a593Smuzhiyun 233*4882a593Smuzhiyun pmic: mc13892@0 { 234*4882a593Smuzhiyun compatible = "fsl,mc13892"; 235*4882a593Smuzhiyun pinctrl-names = "default"; 236*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_pmic>; 237*4882a593Smuzhiyun spi-max-frequency = <6000000>; 238*4882a593Smuzhiyun spi-cs-high; 239*4882a593Smuzhiyun reg = <0>; 240*4882a593Smuzhiyun interrupt-parent = <&gpio1>; 241*4882a593Smuzhiyun interrupts = <8 IRQ_TYPE_LEVEL_HIGH>; 242*4882a593Smuzhiyun fsl,mc13xxx-uses-adc; 243*4882a593Smuzhiyun fsl,mc13xxx-uses-rtc; 244*4882a593Smuzhiyun 245*4882a593Smuzhiyun regulators { 246*4882a593Smuzhiyun sw1_reg: sw1 { 247*4882a593Smuzhiyun regulator-min-microvolt = <600000>; 248*4882a593Smuzhiyun regulator-max-microvolt = <1375000>; 249*4882a593Smuzhiyun regulator-boot-on; 250*4882a593Smuzhiyun regulator-always-on; 251*4882a593Smuzhiyun }; 252*4882a593Smuzhiyun 253*4882a593Smuzhiyun sw2_reg: sw2 { 254*4882a593Smuzhiyun regulator-min-microvolt = <900000>; 255*4882a593Smuzhiyun regulator-max-microvolt = <1850000>; 256*4882a593Smuzhiyun regulator-boot-on; 257*4882a593Smuzhiyun regulator-always-on; 258*4882a593Smuzhiyun }; 259*4882a593Smuzhiyun 260*4882a593Smuzhiyun sw3_reg: sw3 { 261*4882a593Smuzhiyun regulator-min-microvolt = <1100000>; 262*4882a593Smuzhiyun regulator-max-microvolt = <1850000>; 263*4882a593Smuzhiyun regulator-boot-on; 264*4882a593Smuzhiyun regulator-always-on; 265*4882a593Smuzhiyun }; 266*4882a593Smuzhiyun 267*4882a593Smuzhiyun sw4_reg: sw4 { 268*4882a593Smuzhiyun regulator-min-microvolt = <1100000>; 269*4882a593Smuzhiyun regulator-max-microvolt = <1850000>; 270*4882a593Smuzhiyun regulator-boot-on; 271*4882a593Smuzhiyun regulator-always-on; 272*4882a593Smuzhiyun }; 273*4882a593Smuzhiyun 274*4882a593Smuzhiyun vpll_reg: vpll { 275*4882a593Smuzhiyun regulator-min-microvolt = <1050000>; 276*4882a593Smuzhiyun regulator-max-microvolt = <1800000>; 277*4882a593Smuzhiyun regulator-boot-on; 278*4882a593Smuzhiyun regulator-always-on; 279*4882a593Smuzhiyun }; 280*4882a593Smuzhiyun 281*4882a593Smuzhiyun vdig_reg: vdig { 282*4882a593Smuzhiyun regulator-min-microvolt = <1650000>; 283*4882a593Smuzhiyun regulator-max-microvolt = <1650000>; 284*4882a593Smuzhiyun regulator-boot-on; 285*4882a593Smuzhiyun }; 286*4882a593Smuzhiyun 287*4882a593Smuzhiyun vsd_reg: vsd { 288*4882a593Smuzhiyun regulator-min-microvolt = <1800000>; 289*4882a593Smuzhiyun regulator-max-microvolt = <3150000>; 290*4882a593Smuzhiyun }; 291*4882a593Smuzhiyun 292*4882a593Smuzhiyun vusb_reg: vusb { 293*4882a593Smuzhiyun regulator-boot-on; 294*4882a593Smuzhiyun }; 295*4882a593Smuzhiyun 296*4882a593Smuzhiyun vusb2_reg: vusb2 { 297*4882a593Smuzhiyun regulator-min-microvolt = <2400000>; 298*4882a593Smuzhiyun regulator-max-microvolt = <2775000>; 299*4882a593Smuzhiyun regulator-boot-on; 300*4882a593Smuzhiyun regulator-always-on; 301*4882a593Smuzhiyun }; 302*4882a593Smuzhiyun 303*4882a593Smuzhiyun vvideo_reg: vvideo { 304*4882a593Smuzhiyun regulator-min-microvolt = <2775000>; 305*4882a593Smuzhiyun regulator-max-microvolt = <2775000>; 306*4882a593Smuzhiyun }; 307*4882a593Smuzhiyun 308*4882a593Smuzhiyun vaudio_reg: vaudio { 309*4882a593Smuzhiyun regulator-min-microvolt = <2300000>; 310*4882a593Smuzhiyun regulator-max-microvolt = <3000000>; 311*4882a593Smuzhiyun }; 312*4882a593Smuzhiyun 313*4882a593Smuzhiyun vcam_reg: vcam { 314*4882a593Smuzhiyun regulator-min-microvolt = <2500000>; 315*4882a593Smuzhiyun regulator-max-microvolt = <3000000>; 316*4882a593Smuzhiyun }; 317*4882a593Smuzhiyun 318*4882a593Smuzhiyun vgen1_reg: vgen1 { 319*4882a593Smuzhiyun regulator-min-microvolt = <1200000>; 320*4882a593Smuzhiyun regulator-max-microvolt = <1200000>; 321*4882a593Smuzhiyun }; 322*4882a593Smuzhiyun 323*4882a593Smuzhiyun vgen2_reg: vgen2 { 324*4882a593Smuzhiyun regulator-min-microvolt = <1200000>; 325*4882a593Smuzhiyun regulator-max-microvolt = <3150000>; 326*4882a593Smuzhiyun regulator-always-on; 327*4882a593Smuzhiyun }; 328*4882a593Smuzhiyun 329*4882a593Smuzhiyun vgen3_reg: vgen3 { 330*4882a593Smuzhiyun regulator-min-microvolt = <1800000>; 331*4882a593Smuzhiyun regulator-max-microvolt = <2900000>; 332*4882a593Smuzhiyun regulator-always-on; 333*4882a593Smuzhiyun }; 334*4882a593Smuzhiyun }; 335*4882a593Smuzhiyun }; 336*4882a593Smuzhiyun 337*4882a593Smuzhiyun flash: at45db321d@1 { 338*4882a593Smuzhiyun #address-cells = <1>; 339*4882a593Smuzhiyun #size-cells = <1>; 340*4882a593Smuzhiyun compatible = "atmel,at45db321d", "atmel,at45", "atmel,dataflash"; 341*4882a593Smuzhiyun spi-max-frequency = <25000000>; 342*4882a593Smuzhiyun reg = <1>; 343*4882a593Smuzhiyun 344*4882a593Smuzhiyun partition@0 { 345*4882a593Smuzhiyun label = "U-Boot"; 346*4882a593Smuzhiyun reg = <0x0 0x40000>; 347*4882a593Smuzhiyun read-only; 348*4882a593Smuzhiyun }; 349*4882a593Smuzhiyun 350*4882a593Smuzhiyun partition@40000 { 351*4882a593Smuzhiyun label = "Kernel"; 352*4882a593Smuzhiyun reg = <0x40000 0x3c0000>; 353*4882a593Smuzhiyun }; 354*4882a593Smuzhiyun }; 355*4882a593Smuzhiyun}; 356*4882a593Smuzhiyun 357*4882a593Smuzhiyun&esdhc1 { 358*4882a593Smuzhiyun pinctrl-names = "default"; 359*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_esdhc1>; 360*4882a593Smuzhiyun cd-gpios = <&gpio1 0 GPIO_ACTIVE_LOW>; 361*4882a593Smuzhiyun wp-gpios = <&gpio1 1 GPIO_ACTIVE_HIGH>; 362*4882a593Smuzhiyun status = "okay"; 363*4882a593Smuzhiyun}; 364*4882a593Smuzhiyun 365*4882a593Smuzhiyun&esdhc2 { 366*4882a593Smuzhiyun pinctrl-names = "default"; 367*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_esdhc2>; 368*4882a593Smuzhiyun cd-gpios = <&gpio1 6 GPIO_ACTIVE_LOW>; 369*4882a593Smuzhiyun wp-gpios = <&gpio1 5 GPIO_ACTIVE_HIGH>; 370*4882a593Smuzhiyun status = "okay"; 371*4882a593Smuzhiyun}; 372*4882a593Smuzhiyun 373*4882a593Smuzhiyun&fec { 374*4882a593Smuzhiyun pinctrl-names = "default"; 375*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_fec>; 376*4882a593Smuzhiyun phy-mode = "mii"; 377*4882a593Smuzhiyun phy-reset-gpios = <&gpio2 14 GPIO_ACTIVE_LOW>; 378*4882a593Smuzhiyun phy-reset-duration = <1>; 379*4882a593Smuzhiyun status = "okay"; 380*4882a593Smuzhiyun}; 381*4882a593Smuzhiyun 382*4882a593Smuzhiyun&i2c1 { 383*4882a593Smuzhiyun pinctrl-names = "default"; 384*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_i2c1>; 385*4882a593Smuzhiyun status = "okay"; 386*4882a593Smuzhiyun}; 387*4882a593Smuzhiyun 388*4882a593Smuzhiyun&i2c2 { 389*4882a593Smuzhiyun pinctrl-names = "default"; 390*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_i2c2>; 391*4882a593Smuzhiyun status = "okay"; 392*4882a593Smuzhiyun 393*4882a593Smuzhiyun sgtl5000: codec@a { 394*4882a593Smuzhiyun compatible = "fsl,sgtl5000"; 395*4882a593Smuzhiyun reg = <0x0a>; 396*4882a593Smuzhiyun #sound-dai-cells = <0>; 397*4882a593Smuzhiyun clocks = <&clk_audio>; 398*4882a593Smuzhiyun VDDA-supply = <&vdig_reg>; 399*4882a593Smuzhiyun VDDIO-supply = <&vvideo_reg>; 400*4882a593Smuzhiyun }; 401*4882a593Smuzhiyun}; 402*4882a593Smuzhiyun 403*4882a593Smuzhiyun&ipu_di0_disp1 { 404*4882a593Smuzhiyun remote-endpoint = <&display0_in>; 405*4882a593Smuzhiyun}; 406*4882a593Smuzhiyun 407*4882a593Smuzhiyun&ipu_di1_disp2 { 408*4882a593Smuzhiyun remote-endpoint = <&display1_in>; 409*4882a593Smuzhiyun}; 410*4882a593Smuzhiyun 411*4882a593Smuzhiyun&kpp { 412*4882a593Smuzhiyun pinctrl-names = "default"; 413*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_kpp>; 414*4882a593Smuzhiyun linux,keymap = < 415*4882a593Smuzhiyun MATRIX_KEY(0, 0, KEY_UP) 416*4882a593Smuzhiyun MATRIX_KEY(0, 1, KEY_DOWN) 417*4882a593Smuzhiyun MATRIX_KEY(0, 2, KEY_VOLUMEDOWN) 418*4882a593Smuzhiyun MATRIX_KEY(0, 3, KEY_HOME) 419*4882a593Smuzhiyun MATRIX_KEY(1, 0, KEY_RIGHT) 420*4882a593Smuzhiyun MATRIX_KEY(1, 1, KEY_LEFT) 421*4882a593Smuzhiyun MATRIX_KEY(1, 2, KEY_ENTER) 422*4882a593Smuzhiyun MATRIX_KEY(1, 3, KEY_VOLUMEUP) 423*4882a593Smuzhiyun MATRIX_KEY(2, 0, KEY_F6) 424*4882a593Smuzhiyun MATRIX_KEY(2, 1, KEY_F8) 425*4882a593Smuzhiyun MATRIX_KEY(2, 2, KEY_F9) 426*4882a593Smuzhiyun MATRIX_KEY(2, 3, KEY_F10) 427*4882a593Smuzhiyun MATRIX_KEY(3, 0, KEY_F1) 428*4882a593Smuzhiyun MATRIX_KEY(3, 1, KEY_F2) 429*4882a593Smuzhiyun MATRIX_KEY(3, 2, KEY_F3) 430*4882a593Smuzhiyun MATRIX_KEY(3, 3, KEY_POWER) 431*4882a593Smuzhiyun >; 432*4882a593Smuzhiyun status = "okay"; 433*4882a593Smuzhiyun}; 434*4882a593Smuzhiyun 435*4882a593Smuzhiyun&pmu { 436*4882a593Smuzhiyun secure-reg-access; 437*4882a593Smuzhiyun}; 438*4882a593Smuzhiyun 439*4882a593Smuzhiyun&ssi2 { 440*4882a593Smuzhiyun status = "okay"; 441*4882a593Smuzhiyun}; 442*4882a593Smuzhiyun 443*4882a593Smuzhiyun&uart1 { 444*4882a593Smuzhiyun pinctrl-names = "default"; 445*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_uart1>; 446*4882a593Smuzhiyun uart-has-rtscts; 447*4882a593Smuzhiyun status = "okay"; 448*4882a593Smuzhiyun}; 449*4882a593Smuzhiyun 450*4882a593Smuzhiyun&uart2 { 451*4882a593Smuzhiyun pinctrl-names = "default"; 452*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_uart2>; 453*4882a593Smuzhiyun status = "okay"; 454*4882a593Smuzhiyun}; 455*4882a593Smuzhiyun 456*4882a593Smuzhiyun&uart3 { 457*4882a593Smuzhiyun pinctrl-names = "default"; 458*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_uart3>; 459*4882a593Smuzhiyun uart-has-rtscts; 460*4882a593Smuzhiyun status = "okay"; 461*4882a593Smuzhiyun}; 462*4882a593Smuzhiyun 463*4882a593Smuzhiyun&usbh1 { 464*4882a593Smuzhiyun pinctrl-names = "default"; 465*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_usbh1>; 466*4882a593Smuzhiyun vbus-supply = <®_hub_reset>; 467*4882a593Smuzhiyun fsl,usbphy = <&usbphy1>; 468*4882a593Smuzhiyun phy_type = "ulpi"; 469*4882a593Smuzhiyun status = "okay"; 470*4882a593Smuzhiyun}; 471*4882a593Smuzhiyun 472*4882a593Smuzhiyun&usbphy0 { 473*4882a593Smuzhiyun vcc-supply = <&vusb_reg>; 474*4882a593Smuzhiyun}; 475*4882a593Smuzhiyun 476*4882a593Smuzhiyun&usbotg { 477*4882a593Smuzhiyun dr_mode = "otg"; 478*4882a593Smuzhiyun disable-over-current; 479*4882a593Smuzhiyun phy_type = "utmi_wide"; 480*4882a593Smuzhiyun status = "okay"; 481*4882a593Smuzhiyun}; 482*4882a593Smuzhiyun 483*4882a593Smuzhiyun&iomuxc { 484*4882a593Smuzhiyun imx51-babbage { 485*4882a593Smuzhiyun pinctrl_audmux: audmuxgrp { 486*4882a593Smuzhiyun fsl,pins = < 487*4882a593Smuzhiyun MX51_PAD_AUD3_BB_TXD__AUD3_TXD 0x80000000 488*4882a593Smuzhiyun MX51_PAD_AUD3_BB_RXD__AUD3_RXD 0x80000000 489*4882a593Smuzhiyun MX51_PAD_AUD3_BB_CK__AUD3_TXC 0x80000000 490*4882a593Smuzhiyun MX51_PAD_AUD3_BB_FS__AUD3_TXFS 0x80000000 491*4882a593Smuzhiyun >; 492*4882a593Smuzhiyun }; 493*4882a593Smuzhiyun 494*4882a593Smuzhiyun pinctrl_clk26mhz_audio: clk26mhzaudiocgrp { 495*4882a593Smuzhiyun fsl,pins = < 496*4882a593Smuzhiyun MX51_PAD_CSPI1_RDY__GPIO4_26 0x85 497*4882a593Smuzhiyun >; 498*4882a593Smuzhiyun }; 499*4882a593Smuzhiyun 500*4882a593Smuzhiyun pinctrl_clk26mhz_osc: clk26mhzoscgrp { 501*4882a593Smuzhiyun fsl,pins = < 502*4882a593Smuzhiyun MX51_PAD_DI1_PIN12__GPIO3_1 0x85 503*4882a593Smuzhiyun >; 504*4882a593Smuzhiyun }; 505*4882a593Smuzhiyun 506*4882a593Smuzhiyun pinctrl_clk26mhz_usb: clk26mhzusbgrp { 507*4882a593Smuzhiyun fsl,pins = < 508*4882a593Smuzhiyun MX51_PAD_EIM_D17__GPIO2_1 0x85 509*4882a593Smuzhiyun >; 510*4882a593Smuzhiyun }; 511*4882a593Smuzhiyun 512*4882a593Smuzhiyun pinctrl_ecspi1: ecspi1grp { 513*4882a593Smuzhiyun fsl,pins = < 514*4882a593Smuzhiyun MX51_PAD_CSPI1_MISO__ECSPI1_MISO 0x185 515*4882a593Smuzhiyun MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI 0x185 516*4882a593Smuzhiyun MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK 0x185 517*4882a593Smuzhiyun MX51_PAD_CSPI1_SS0__GPIO4_24 0x85 /* CS0 */ 518*4882a593Smuzhiyun MX51_PAD_CSPI1_SS1__GPIO4_25 0x85 /* CS1 */ 519*4882a593Smuzhiyun >; 520*4882a593Smuzhiyun }; 521*4882a593Smuzhiyun 522*4882a593Smuzhiyun pinctrl_esdhc1: esdhc1grp { 523*4882a593Smuzhiyun fsl,pins = < 524*4882a593Smuzhiyun MX51_PAD_SD1_CMD__SD1_CMD 0x400020d5 525*4882a593Smuzhiyun MX51_PAD_SD1_CLK__SD1_CLK 0x20d5 526*4882a593Smuzhiyun MX51_PAD_SD1_DATA0__SD1_DATA0 0x20d5 527*4882a593Smuzhiyun MX51_PAD_SD1_DATA1__SD1_DATA1 0x20d5 528*4882a593Smuzhiyun MX51_PAD_SD1_DATA2__SD1_DATA2 0x20d5 529*4882a593Smuzhiyun MX51_PAD_SD1_DATA3__SD1_DATA3 0x20d5 530*4882a593Smuzhiyun MX51_PAD_GPIO1_0__GPIO1_0 0x100 531*4882a593Smuzhiyun MX51_PAD_GPIO1_1__GPIO1_1 0x100 532*4882a593Smuzhiyun >; 533*4882a593Smuzhiyun }; 534*4882a593Smuzhiyun 535*4882a593Smuzhiyun pinctrl_esdhc2: esdhc2grp { 536*4882a593Smuzhiyun fsl,pins = < 537*4882a593Smuzhiyun MX51_PAD_SD2_CMD__SD2_CMD 0x400020d5 538*4882a593Smuzhiyun MX51_PAD_SD2_CLK__SD2_CLK 0x20d5 539*4882a593Smuzhiyun MX51_PAD_SD2_DATA0__SD2_DATA0 0x20d5 540*4882a593Smuzhiyun MX51_PAD_SD2_DATA1__SD2_DATA1 0x20d5 541*4882a593Smuzhiyun MX51_PAD_SD2_DATA2__SD2_DATA2 0x20d5 542*4882a593Smuzhiyun MX51_PAD_SD2_DATA3__SD2_DATA3 0x20d5 543*4882a593Smuzhiyun MX51_PAD_GPIO1_5__GPIO1_5 0x100 /* WP */ 544*4882a593Smuzhiyun MX51_PAD_GPIO1_6__GPIO1_6 0x100 /* CD */ 545*4882a593Smuzhiyun >; 546*4882a593Smuzhiyun }; 547*4882a593Smuzhiyun 548*4882a593Smuzhiyun pinctrl_fec: fecgrp { 549*4882a593Smuzhiyun fsl,pins = < 550*4882a593Smuzhiyun MX51_PAD_EIM_EB2__FEC_MDIO 0x000001f5 551*4882a593Smuzhiyun MX51_PAD_EIM_EB3__FEC_RDATA1 0x00000085 552*4882a593Smuzhiyun MX51_PAD_EIM_CS2__FEC_RDATA2 0x00000085 553*4882a593Smuzhiyun MX51_PAD_EIM_CS3__FEC_RDATA3 0x00000085 554*4882a593Smuzhiyun MX51_PAD_EIM_CS4__FEC_RX_ER 0x00000180 555*4882a593Smuzhiyun MX51_PAD_EIM_CS5__FEC_CRS 0x00000180 556*4882a593Smuzhiyun MX51_PAD_NANDF_RB2__FEC_COL 0x00000180 557*4882a593Smuzhiyun MX51_PAD_NANDF_RB3__FEC_RX_CLK 0x00000180 558*4882a593Smuzhiyun MX51_PAD_NANDF_D9__FEC_RDATA0 0x00002180 559*4882a593Smuzhiyun MX51_PAD_NANDF_D8__FEC_TDATA0 0x00002004 560*4882a593Smuzhiyun MX51_PAD_NANDF_CS2__FEC_TX_ER 0x00002004 561*4882a593Smuzhiyun MX51_PAD_NANDF_CS3__FEC_MDC 0x00002004 562*4882a593Smuzhiyun MX51_PAD_NANDF_CS4__FEC_TDATA1 0x00002004 563*4882a593Smuzhiyun MX51_PAD_NANDF_CS5__FEC_TDATA2 0x00002004 564*4882a593Smuzhiyun MX51_PAD_NANDF_CS6__FEC_TDATA3 0x00002004 565*4882a593Smuzhiyun MX51_PAD_NANDF_CS7__FEC_TX_EN 0x00002004 566*4882a593Smuzhiyun MX51_PAD_NANDF_RDY_INT__FEC_TX_CLK 0x00002180 567*4882a593Smuzhiyun MX51_PAD_NANDF_D11__FEC_RX_DV 0x000020a4 568*4882a593Smuzhiyun MX51_PAD_EIM_A20__GPIO2_14 0x00000085 /* Phy Reset */ 569*4882a593Smuzhiyun >; 570*4882a593Smuzhiyun }; 571*4882a593Smuzhiyun 572*4882a593Smuzhiyun pinctrl_gpio_keys: gpiokeysgrp { 573*4882a593Smuzhiyun fsl,pins = < 574*4882a593Smuzhiyun MX51_PAD_EIM_A27__GPIO2_21 0x5 575*4882a593Smuzhiyun >; 576*4882a593Smuzhiyun }; 577*4882a593Smuzhiyun 578*4882a593Smuzhiyun pinctrl_gpio_leds: gpioledsgrp { 579*4882a593Smuzhiyun fsl,pins = < 580*4882a593Smuzhiyun MX51_PAD_EIM_D22__GPIO2_6 0x80000000 581*4882a593Smuzhiyun >; 582*4882a593Smuzhiyun }; 583*4882a593Smuzhiyun 584*4882a593Smuzhiyun pinctrl_i2c1: i2c1grp { 585*4882a593Smuzhiyun fsl,pins = < 586*4882a593Smuzhiyun MX51_PAD_EIM_D19__I2C1_SCL 0x400001ed 587*4882a593Smuzhiyun MX51_PAD_EIM_D16__I2C1_SDA 0x400001ed 588*4882a593Smuzhiyun >; 589*4882a593Smuzhiyun }; 590*4882a593Smuzhiyun 591*4882a593Smuzhiyun pinctrl_i2c2: i2c2grp { 592*4882a593Smuzhiyun fsl,pins = < 593*4882a593Smuzhiyun MX51_PAD_KEY_COL4__I2C2_SCL 0x400001ed 594*4882a593Smuzhiyun MX51_PAD_KEY_COL5__I2C2_SDA 0x400001ed 595*4882a593Smuzhiyun >; 596*4882a593Smuzhiyun }; 597*4882a593Smuzhiyun 598*4882a593Smuzhiyun pinctrl_ipu_disp1: ipudisp1grp { 599*4882a593Smuzhiyun fsl,pins = < 600*4882a593Smuzhiyun MX51_PAD_DISP1_DAT0__DISP1_DAT0 0x5 601*4882a593Smuzhiyun MX51_PAD_DISP1_DAT1__DISP1_DAT1 0x5 602*4882a593Smuzhiyun MX51_PAD_DISP1_DAT2__DISP1_DAT2 0x5 603*4882a593Smuzhiyun MX51_PAD_DISP1_DAT3__DISP1_DAT3 0x5 604*4882a593Smuzhiyun MX51_PAD_DISP1_DAT4__DISP1_DAT4 0x5 605*4882a593Smuzhiyun MX51_PAD_DISP1_DAT5__DISP1_DAT5 0x5 606*4882a593Smuzhiyun MX51_PAD_DISP1_DAT6__DISP1_DAT6 0x5 607*4882a593Smuzhiyun MX51_PAD_DISP1_DAT7__DISP1_DAT7 0x5 608*4882a593Smuzhiyun MX51_PAD_DISP1_DAT8__DISP1_DAT8 0x5 609*4882a593Smuzhiyun MX51_PAD_DISP1_DAT9__DISP1_DAT9 0x5 610*4882a593Smuzhiyun MX51_PAD_DISP1_DAT10__DISP1_DAT10 0x5 611*4882a593Smuzhiyun MX51_PAD_DISP1_DAT11__DISP1_DAT11 0x5 612*4882a593Smuzhiyun MX51_PAD_DISP1_DAT12__DISP1_DAT12 0x5 613*4882a593Smuzhiyun MX51_PAD_DISP1_DAT13__DISP1_DAT13 0x5 614*4882a593Smuzhiyun MX51_PAD_DISP1_DAT14__DISP1_DAT14 0x5 615*4882a593Smuzhiyun MX51_PAD_DISP1_DAT15__DISP1_DAT15 0x5 616*4882a593Smuzhiyun MX51_PAD_DISP1_DAT16__DISP1_DAT16 0x5 617*4882a593Smuzhiyun MX51_PAD_DISP1_DAT17__DISP1_DAT17 0x5 618*4882a593Smuzhiyun MX51_PAD_DISP1_DAT18__DISP1_DAT18 0x5 619*4882a593Smuzhiyun MX51_PAD_DISP1_DAT19__DISP1_DAT19 0x5 620*4882a593Smuzhiyun MX51_PAD_DISP1_DAT20__DISP1_DAT20 0x5 621*4882a593Smuzhiyun MX51_PAD_DISP1_DAT21__DISP1_DAT21 0x5 622*4882a593Smuzhiyun MX51_PAD_DISP1_DAT22__DISP1_DAT22 0x5 623*4882a593Smuzhiyun MX51_PAD_DISP1_DAT23__DISP1_DAT23 0x5 624*4882a593Smuzhiyun MX51_PAD_DI1_PIN2__DI1_PIN2 0x5 625*4882a593Smuzhiyun MX51_PAD_DI1_PIN3__DI1_PIN3 0x5 626*4882a593Smuzhiyun >; 627*4882a593Smuzhiyun }; 628*4882a593Smuzhiyun 629*4882a593Smuzhiyun pinctrl_ipu_disp2: ipudisp2grp { 630*4882a593Smuzhiyun fsl,pins = < 631*4882a593Smuzhiyun MX51_PAD_DISP2_DAT0__DISP2_DAT0 0x5 632*4882a593Smuzhiyun MX51_PAD_DISP2_DAT1__DISP2_DAT1 0x5 633*4882a593Smuzhiyun MX51_PAD_DISP2_DAT2__DISP2_DAT2 0x5 634*4882a593Smuzhiyun MX51_PAD_DISP2_DAT3__DISP2_DAT3 0x5 635*4882a593Smuzhiyun MX51_PAD_DISP2_DAT4__DISP2_DAT4 0x5 636*4882a593Smuzhiyun MX51_PAD_DISP2_DAT5__DISP2_DAT5 0x5 637*4882a593Smuzhiyun MX51_PAD_DISP2_DAT6__DISP2_DAT6 0x5 638*4882a593Smuzhiyun MX51_PAD_DISP2_DAT7__DISP2_DAT7 0x5 639*4882a593Smuzhiyun MX51_PAD_DISP2_DAT8__DISP2_DAT8 0x5 640*4882a593Smuzhiyun MX51_PAD_DISP2_DAT9__DISP2_DAT9 0x5 641*4882a593Smuzhiyun MX51_PAD_DISP2_DAT10__DISP2_DAT10 0x5 642*4882a593Smuzhiyun MX51_PAD_DISP2_DAT11__DISP2_DAT11 0x5 643*4882a593Smuzhiyun MX51_PAD_DISP2_DAT12__DISP2_DAT12 0x5 644*4882a593Smuzhiyun MX51_PAD_DISP2_DAT13__DISP2_DAT13 0x5 645*4882a593Smuzhiyun MX51_PAD_DISP2_DAT14__DISP2_DAT14 0x5 646*4882a593Smuzhiyun MX51_PAD_DISP2_DAT15__DISP2_DAT15 0x5 647*4882a593Smuzhiyun MX51_PAD_DI2_PIN2__DI2_PIN2 0x5 648*4882a593Smuzhiyun MX51_PAD_DI2_PIN3__DI2_PIN3 0x5 649*4882a593Smuzhiyun MX51_PAD_DI2_DISP_CLK__DI2_DISP_CLK 0x5 650*4882a593Smuzhiyun MX51_PAD_DI_GP4__DI2_PIN15 0x5 651*4882a593Smuzhiyun >; 652*4882a593Smuzhiyun }; 653*4882a593Smuzhiyun 654*4882a593Smuzhiyun pinctrl_kpp: kppgrp { 655*4882a593Smuzhiyun fsl,pins = < 656*4882a593Smuzhiyun MX51_PAD_KEY_ROW0__KEY_ROW0 0xe0 657*4882a593Smuzhiyun MX51_PAD_KEY_ROW1__KEY_ROW1 0xe0 658*4882a593Smuzhiyun MX51_PAD_KEY_ROW2__KEY_ROW2 0xe0 659*4882a593Smuzhiyun MX51_PAD_KEY_ROW3__KEY_ROW3 0xe0 660*4882a593Smuzhiyun MX51_PAD_KEY_COL0__KEY_COL0 0xe8 661*4882a593Smuzhiyun MX51_PAD_KEY_COL1__KEY_COL1 0xe8 662*4882a593Smuzhiyun MX51_PAD_KEY_COL2__KEY_COL2 0xe8 663*4882a593Smuzhiyun MX51_PAD_KEY_COL3__KEY_COL3 0xe8 664*4882a593Smuzhiyun >; 665*4882a593Smuzhiyun }; 666*4882a593Smuzhiyun 667*4882a593Smuzhiyun pinctrl_pmic: pmicgrp { 668*4882a593Smuzhiyun fsl,pins = < 669*4882a593Smuzhiyun MX51_PAD_GPIO1_8__GPIO1_8 0xe5 /* IRQ */ 670*4882a593Smuzhiyun >; 671*4882a593Smuzhiyun }; 672*4882a593Smuzhiyun 673*4882a593Smuzhiyun pinctrl_uart1: uart1grp { 674*4882a593Smuzhiyun fsl,pins = < 675*4882a593Smuzhiyun MX51_PAD_UART1_RXD__UART1_RXD 0x1c5 676*4882a593Smuzhiyun MX51_PAD_UART1_TXD__UART1_TXD 0x1c5 677*4882a593Smuzhiyun MX51_PAD_UART1_RTS__UART1_RTS 0x1c5 678*4882a593Smuzhiyun MX51_PAD_UART1_CTS__UART1_CTS 0x1c5 679*4882a593Smuzhiyun >; 680*4882a593Smuzhiyun }; 681*4882a593Smuzhiyun 682*4882a593Smuzhiyun pinctrl_uart2: uart2grp { 683*4882a593Smuzhiyun fsl,pins = < 684*4882a593Smuzhiyun MX51_PAD_UART2_RXD__UART2_RXD 0x1c5 685*4882a593Smuzhiyun MX51_PAD_UART2_TXD__UART2_TXD 0x1c5 686*4882a593Smuzhiyun >; 687*4882a593Smuzhiyun }; 688*4882a593Smuzhiyun 689*4882a593Smuzhiyun pinctrl_uart3: uart3grp { 690*4882a593Smuzhiyun fsl,pins = < 691*4882a593Smuzhiyun MX51_PAD_EIM_D25__UART3_RXD 0x1c5 692*4882a593Smuzhiyun MX51_PAD_EIM_D26__UART3_TXD 0x1c5 693*4882a593Smuzhiyun MX51_PAD_EIM_D27__UART3_RTS 0x1c5 694*4882a593Smuzhiyun MX51_PAD_EIM_D24__UART3_CTS 0x1c5 695*4882a593Smuzhiyun >; 696*4882a593Smuzhiyun }; 697*4882a593Smuzhiyun 698*4882a593Smuzhiyun pinctrl_usbh1: usbh1grp { 699*4882a593Smuzhiyun fsl,pins = < 700*4882a593Smuzhiyun MX51_PAD_USBH1_CLK__USBH1_CLK 0x80000000 701*4882a593Smuzhiyun MX51_PAD_USBH1_DIR__USBH1_DIR 0x80000000 702*4882a593Smuzhiyun MX51_PAD_USBH1_NXT__USBH1_NXT 0x80000000 703*4882a593Smuzhiyun MX51_PAD_USBH1_DATA0__USBH1_DATA0 0x80000000 704*4882a593Smuzhiyun MX51_PAD_USBH1_DATA1__USBH1_DATA1 0x80000000 705*4882a593Smuzhiyun MX51_PAD_USBH1_DATA2__USBH1_DATA2 0x80000000 706*4882a593Smuzhiyun MX51_PAD_USBH1_DATA3__USBH1_DATA3 0x80000000 707*4882a593Smuzhiyun MX51_PAD_USBH1_DATA4__USBH1_DATA4 0x80000000 708*4882a593Smuzhiyun MX51_PAD_USBH1_DATA5__USBH1_DATA5 0x80000000 709*4882a593Smuzhiyun MX51_PAD_USBH1_DATA6__USBH1_DATA6 0x80000000 710*4882a593Smuzhiyun MX51_PAD_USBH1_DATA7__USBH1_DATA7 0x80000000 711*4882a593Smuzhiyun >; 712*4882a593Smuzhiyun }; 713*4882a593Smuzhiyun 714*4882a593Smuzhiyun pinctrl_usbh1reg: usbh1reggrp { 715*4882a593Smuzhiyun fsl,pins = < 716*4882a593Smuzhiyun MX51_PAD_EIM_D21__GPIO2_5 0x85 717*4882a593Smuzhiyun >; 718*4882a593Smuzhiyun }; 719*4882a593Smuzhiyun 720*4882a593Smuzhiyun pinctrl_usbotgreg: usbotgreggrp { 721*4882a593Smuzhiyun fsl,pins = < 722*4882a593Smuzhiyun MX51_PAD_GPIO1_7__GPIO1_7 0x85 723*4882a593Smuzhiyun >; 724*4882a593Smuzhiyun }; 725*4882a593Smuzhiyun }; 726*4882a593Smuzhiyun}; 727