1*4882a593Smuzhiyun// SPDX-License-Identifier: GPL-2.0-or-later 2*4882a593Smuzhiyun/* 3*4882a593Smuzhiyun * Copyright 2012 Armadeus Systems - <support@armadeus.com> 4*4882a593Smuzhiyun * Copyright 2012 Laurent Cans <laurent.cans@gmail.com> 5*4882a593Smuzhiyun * 6*4882a593Smuzhiyun * Based on mx51-babbage.dts 7*4882a593Smuzhiyun * Copyright 2011 Freescale Semiconductor, Inc. 8*4882a593Smuzhiyun * Copyright 2011 Linaro Ltd. 9*4882a593Smuzhiyun */ 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun/dts-v1/; 12*4882a593Smuzhiyun#include "imx51.dtsi" 13*4882a593Smuzhiyun 14*4882a593Smuzhiyun/ { 15*4882a593Smuzhiyun model = "Armadeus Systems APF51 module"; 16*4882a593Smuzhiyun compatible = "armadeus,imx51-apf51", "fsl,imx51"; 17*4882a593Smuzhiyun 18*4882a593Smuzhiyun memory@90000000 { 19*4882a593Smuzhiyun device_type = "memory"; 20*4882a593Smuzhiyun reg = <0x90000000 0x20000000>; 21*4882a593Smuzhiyun }; 22*4882a593Smuzhiyun 23*4882a593Smuzhiyun clocks { 24*4882a593Smuzhiyun osc { 25*4882a593Smuzhiyun clock-frequency = <33554432>; 26*4882a593Smuzhiyun }; 27*4882a593Smuzhiyun }; 28*4882a593Smuzhiyun}; 29*4882a593Smuzhiyun 30*4882a593Smuzhiyun&fec { 31*4882a593Smuzhiyun pinctrl-names = "default"; 32*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_fec>; 33*4882a593Smuzhiyun phy-mode = "mii"; 34*4882a593Smuzhiyun phy-reset-gpios = <&gpio3 0 GPIO_ACTIVE_LOW>; 35*4882a593Smuzhiyun phy-reset-duration = <1>; 36*4882a593Smuzhiyun status = "okay"; 37*4882a593Smuzhiyun}; 38*4882a593Smuzhiyun 39*4882a593Smuzhiyun&iomuxc { 40*4882a593Smuzhiyun imx51-apf51 { 41*4882a593Smuzhiyun pinctrl_fec: fecgrp { 42*4882a593Smuzhiyun fsl,pins = < 43*4882a593Smuzhiyun MX51_PAD_DI_GP3__FEC_TX_ER 0x80000000 44*4882a593Smuzhiyun MX51_PAD_DI2_PIN4__FEC_CRS 0x80000000 45*4882a593Smuzhiyun MX51_PAD_DI2_PIN2__FEC_MDC 0x80000000 46*4882a593Smuzhiyun MX51_PAD_DI2_PIN3__FEC_MDIO 0x80000000 47*4882a593Smuzhiyun MX51_PAD_DI2_DISP_CLK__FEC_RDATA1 0x80000000 48*4882a593Smuzhiyun MX51_PAD_DI_GP4__FEC_RDATA2 0x80000000 49*4882a593Smuzhiyun MX51_PAD_DISP2_DAT0__FEC_RDATA3 0x80000000 50*4882a593Smuzhiyun MX51_PAD_DISP2_DAT1__FEC_RX_ER 0x80000000 51*4882a593Smuzhiyun MX51_PAD_DISP2_DAT6__FEC_TDATA1 0x80000000 52*4882a593Smuzhiyun MX51_PAD_DISP2_DAT7__FEC_TDATA2 0x80000000 53*4882a593Smuzhiyun MX51_PAD_DISP2_DAT8__FEC_TDATA3 0x80000000 54*4882a593Smuzhiyun MX51_PAD_DISP2_DAT9__FEC_TX_EN 0x80000000 55*4882a593Smuzhiyun MX51_PAD_DISP2_DAT10__FEC_COL 0x80000000 56*4882a593Smuzhiyun MX51_PAD_DISP2_DAT11__FEC_RX_CLK 0x80000000 57*4882a593Smuzhiyun MX51_PAD_DISP2_DAT12__FEC_RX_DV 0x80000000 58*4882a593Smuzhiyun MX51_PAD_DISP2_DAT13__FEC_TX_CLK 0x80000000 59*4882a593Smuzhiyun MX51_PAD_DISP2_DAT14__FEC_RDATA0 0x80000000 60*4882a593Smuzhiyun MX51_PAD_DISP2_DAT15__FEC_TDATA0 0x80000000 61*4882a593Smuzhiyun >; 62*4882a593Smuzhiyun }; 63*4882a593Smuzhiyun 64*4882a593Smuzhiyun pinctrl_uart3: uart3grp { 65*4882a593Smuzhiyun fsl,pins = < 66*4882a593Smuzhiyun MX51_PAD_UART3_RXD__UART3_RXD 0x1c5 67*4882a593Smuzhiyun MX51_PAD_UART3_TXD__UART3_TXD 0x1c5 68*4882a593Smuzhiyun >; 69*4882a593Smuzhiyun }; 70*4882a593Smuzhiyun }; 71*4882a593Smuzhiyun}; 72*4882a593Smuzhiyun 73*4882a593Smuzhiyun&nfc { 74*4882a593Smuzhiyun nand-bus-width = <8>; 75*4882a593Smuzhiyun nand-ecc-mode = "hw"; 76*4882a593Smuzhiyun nand-on-flash-bbt; 77*4882a593Smuzhiyun status = "okay"; 78*4882a593Smuzhiyun}; 79*4882a593Smuzhiyun 80*4882a593Smuzhiyun&uart3 { 81*4882a593Smuzhiyun pinctrl-names = "default"; 82*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_uart3>; 83*4882a593Smuzhiyun status = "okay"; 84*4882a593Smuzhiyun}; 85