xref: /OK3568_Linux_fs/kernel/scripts/dtc/include-prefixes/arm/imx23.dtsi (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun// SPDX-License-Identifier: GPL-2.0+
2*4882a593Smuzhiyun//
3*4882a593Smuzhiyun// Copyright 2012 Freescale Semiconductor, Inc.
4*4882a593Smuzhiyun
5*4882a593Smuzhiyun#include "imx23-pinfunc.h"
6*4882a593Smuzhiyun
7*4882a593Smuzhiyun/ {
8*4882a593Smuzhiyun	#address-cells = <1>;
9*4882a593Smuzhiyun	#size-cells = <1>;
10*4882a593Smuzhiyun
11*4882a593Smuzhiyun	interrupt-parent = <&icoll>;
12*4882a593Smuzhiyun	/*
13*4882a593Smuzhiyun	 * The decompressor and also some bootloaders rely on a
14*4882a593Smuzhiyun	 * pre-existing /chosen node to be available to insert the
15*4882a593Smuzhiyun	 * command line and merge other ATAGS info.
16*4882a593Smuzhiyun	 */
17*4882a593Smuzhiyun	chosen {};
18*4882a593Smuzhiyun
19*4882a593Smuzhiyun	aliases {
20*4882a593Smuzhiyun		gpio0 = &gpio0;
21*4882a593Smuzhiyun		gpio1 = &gpio1;
22*4882a593Smuzhiyun		gpio2 = &gpio2;
23*4882a593Smuzhiyun		serial0 = &auart0;
24*4882a593Smuzhiyun		serial1 = &auart1;
25*4882a593Smuzhiyun		spi0 = &ssp0;
26*4882a593Smuzhiyun		spi1 = &ssp1;
27*4882a593Smuzhiyun		usbphy0 = &usbphy0;
28*4882a593Smuzhiyun	};
29*4882a593Smuzhiyun
30*4882a593Smuzhiyun	cpus {
31*4882a593Smuzhiyun		#address-cells = <1>;
32*4882a593Smuzhiyun		#size-cells = <0>;
33*4882a593Smuzhiyun
34*4882a593Smuzhiyun		cpu@0 {
35*4882a593Smuzhiyun			compatible = "arm,arm926ej-s";
36*4882a593Smuzhiyun			device_type = "cpu";
37*4882a593Smuzhiyun			reg = <0>;
38*4882a593Smuzhiyun		};
39*4882a593Smuzhiyun	};
40*4882a593Smuzhiyun
41*4882a593Smuzhiyun	apb@80000000 {
42*4882a593Smuzhiyun		compatible = "simple-bus";
43*4882a593Smuzhiyun		#address-cells = <1>;
44*4882a593Smuzhiyun		#size-cells = <1>;
45*4882a593Smuzhiyun		reg = <0x80000000 0x80000>;
46*4882a593Smuzhiyun		ranges;
47*4882a593Smuzhiyun
48*4882a593Smuzhiyun		apbh@80000000 {
49*4882a593Smuzhiyun			compatible = "simple-bus";
50*4882a593Smuzhiyun			#address-cells = <1>;
51*4882a593Smuzhiyun			#size-cells = <1>;
52*4882a593Smuzhiyun			reg = <0x80000000 0x40000>;
53*4882a593Smuzhiyun			ranges;
54*4882a593Smuzhiyun
55*4882a593Smuzhiyun			icoll: interrupt-controller@80000000 {
56*4882a593Smuzhiyun				compatible = "fsl,imx23-icoll", "fsl,icoll";
57*4882a593Smuzhiyun				interrupt-controller;
58*4882a593Smuzhiyun				#interrupt-cells = <1>;
59*4882a593Smuzhiyun				reg = <0x80000000 0x2000>;
60*4882a593Smuzhiyun			};
61*4882a593Smuzhiyun
62*4882a593Smuzhiyun			dma_apbh: dma-apbh@80004000 {
63*4882a593Smuzhiyun				compatible = "fsl,imx23-dma-apbh";
64*4882a593Smuzhiyun				reg = <0x80004000 0x2000>;
65*4882a593Smuzhiyun				interrupts = <0 14 20 0
66*4882a593Smuzhiyun					      13 13 13 13>;
67*4882a593Smuzhiyun				interrupt-names = "empty", "ssp0", "ssp1", "empty",
68*4882a593Smuzhiyun						  "gpmi0", "gpmi1", "gpmi2", "gpmi3";
69*4882a593Smuzhiyun				#dma-cells = <1>;
70*4882a593Smuzhiyun				dma-channels = <8>;
71*4882a593Smuzhiyun				clocks = <&clks 15>;
72*4882a593Smuzhiyun			};
73*4882a593Smuzhiyun
74*4882a593Smuzhiyun			ecc@80008000 {
75*4882a593Smuzhiyun				reg = <0x80008000 0x2000>;
76*4882a593Smuzhiyun				status = "disabled";
77*4882a593Smuzhiyun			};
78*4882a593Smuzhiyun
79*4882a593Smuzhiyun			nand-controller@8000c000 {
80*4882a593Smuzhiyun				compatible = "fsl,imx23-gpmi-nand";
81*4882a593Smuzhiyun				#address-cells = <1>;
82*4882a593Smuzhiyun				#size-cells = <1>;
83*4882a593Smuzhiyun				reg = <0x8000c000 0x2000>, <0x8000a000 0x2000>;
84*4882a593Smuzhiyun				reg-names = "gpmi-nand", "bch";
85*4882a593Smuzhiyun				interrupts = <56>;
86*4882a593Smuzhiyun				interrupt-names = "bch";
87*4882a593Smuzhiyun				clocks = <&clks 34>;
88*4882a593Smuzhiyun				clock-names = "gpmi_io";
89*4882a593Smuzhiyun				dmas = <&dma_apbh 4>;
90*4882a593Smuzhiyun				dma-names = "rx-tx";
91*4882a593Smuzhiyun				status = "disabled";
92*4882a593Smuzhiyun			};
93*4882a593Smuzhiyun
94*4882a593Smuzhiyun			ssp0: spi@80010000 {
95*4882a593Smuzhiyun				reg = <0x80010000 0x2000>;
96*4882a593Smuzhiyun				interrupts = <15>;
97*4882a593Smuzhiyun				clocks = <&clks 33>;
98*4882a593Smuzhiyun				dmas = <&dma_apbh 1>;
99*4882a593Smuzhiyun				dma-names = "rx-tx";
100*4882a593Smuzhiyun				status = "disabled";
101*4882a593Smuzhiyun			};
102*4882a593Smuzhiyun
103*4882a593Smuzhiyun			etm@80014000 {
104*4882a593Smuzhiyun				reg = <0x80014000 0x2000>;
105*4882a593Smuzhiyun				status = "disabled";
106*4882a593Smuzhiyun			};
107*4882a593Smuzhiyun
108*4882a593Smuzhiyun			pinctrl@80018000 {
109*4882a593Smuzhiyun				#address-cells = <1>;
110*4882a593Smuzhiyun				#size-cells = <0>;
111*4882a593Smuzhiyun				compatible = "fsl,imx23-pinctrl", "simple-bus";
112*4882a593Smuzhiyun				reg = <0x80018000 0x2000>;
113*4882a593Smuzhiyun
114*4882a593Smuzhiyun				gpio0: gpio@0 {
115*4882a593Smuzhiyun					compatible = "fsl,imx23-gpio", "fsl,mxs-gpio";
116*4882a593Smuzhiyun					reg = <0>;
117*4882a593Smuzhiyun					interrupts = <16>;
118*4882a593Smuzhiyun					gpio-controller;
119*4882a593Smuzhiyun					#gpio-cells = <2>;
120*4882a593Smuzhiyun					interrupt-controller;
121*4882a593Smuzhiyun					#interrupt-cells = <2>;
122*4882a593Smuzhiyun				};
123*4882a593Smuzhiyun
124*4882a593Smuzhiyun				gpio1: gpio@1 {
125*4882a593Smuzhiyun					compatible = "fsl,imx23-gpio", "fsl,mxs-gpio";
126*4882a593Smuzhiyun					reg = <1>;
127*4882a593Smuzhiyun					interrupts = <17>;
128*4882a593Smuzhiyun					gpio-controller;
129*4882a593Smuzhiyun					#gpio-cells = <2>;
130*4882a593Smuzhiyun					interrupt-controller;
131*4882a593Smuzhiyun					#interrupt-cells = <2>;
132*4882a593Smuzhiyun				};
133*4882a593Smuzhiyun
134*4882a593Smuzhiyun				gpio2: gpio@2 {
135*4882a593Smuzhiyun					compatible = "fsl,imx23-gpio", "fsl,mxs-gpio";
136*4882a593Smuzhiyun					reg = <2>;
137*4882a593Smuzhiyun					interrupts = <18>;
138*4882a593Smuzhiyun					gpio-controller;
139*4882a593Smuzhiyun					#gpio-cells = <2>;
140*4882a593Smuzhiyun					interrupt-controller;
141*4882a593Smuzhiyun					#interrupt-cells = <2>;
142*4882a593Smuzhiyun				};
143*4882a593Smuzhiyun
144*4882a593Smuzhiyun				duart_pins_a: duart@0 {
145*4882a593Smuzhiyun					reg = <0>;
146*4882a593Smuzhiyun					fsl,pinmux-ids = <
147*4882a593Smuzhiyun						MX23_PAD_PWM0__DUART_RX
148*4882a593Smuzhiyun						MX23_PAD_PWM1__DUART_TX
149*4882a593Smuzhiyun					>;
150*4882a593Smuzhiyun					fsl,drive-strength = <MXS_DRIVE_4mA>;
151*4882a593Smuzhiyun					fsl,voltage = <MXS_VOLTAGE_HIGH>;
152*4882a593Smuzhiyun					fsl,pull-up = <MXS_PULL_DISABLE>;
153*4882a593Smuzhiyun				};
154*4882a593Smuzhiyun
155*4882a593Smuzhiyun				auart0_pins_a: auart0@0 {
156*4882a593Smuzhiyun					reg = <0>;
157*4882a593Smuzhiyun					fsl,pinmux-ids = <
158*4882a593Smuzhiyun						MX23_PAD_AUART1_RX__AUART1_RX
159*4882a593Smuzhiyun						MX23_PAD_AUART1_TX__AUART1_TX
160*4882a593Smuzhiyun						MX23_PAD_AUART1_CTS__AUART1_CTS
161*4882a593Smuzhiyun						MX23_PAD_AUART1_RTS__AUART1_RTS
162*4882a593Smuzhiyun					>;
163*4882a593Smuzhiyun					fsl,drive-strength = <MXS_DRIVE_4mA>;
164*4882a593Smuzhiyun					fsl,voltage = <MXS_VOLTAGE_HIGH>;
165*4882a593Smuzhiyun					fsl,pull-up = <MXS_PULL_DISABLE>;
166*4882a593Smuzhiyun				};
167*4882a593Smuzhiyun
168*4882a593Smuzhiyun				auart0_2pins_a: auart0-2pins@0 {
169*4882a593Smuzhiyun					reg = <0>;
170*4882a593Smuzhiyun					fsl,pinmux-ids = <
171*4882a593Smuzhiyun						MX23_PAD_I2C_SCL__AUART1_TX
172*4882a593Smuzhiyun						MX23_PAD_I2C_SDA__AUART1_RX
173*4882a593Smuzhiyun					>;
174*4882a593Smuzhiyun					fsl,drive-strength = <MXS_DRIVE_4mA>;
175*4882a593Smuzhiyun					fsl,voltage = <MXS_VOLTAGE_HIGH>;
176*4882a593Smuzhiyun					fsl,pull-up = <MXS_PULL_DISABLE>;
177*4882a593Smuzhiyun				};
178*4882a593Smuzhiyun
179*4882a593Smuzhiyun				auart1_2pins_a: auart1-2pins@0 {
180*4882a593Smuzhiyun					reg = <0>;
181*4882a593Smuzhiyun					fsl,pinmux-ids = <
182*4882a593Smuzhiyun						MX23_PAD_GPMI_D14__AUART2_RX
183*4882a593Smuzhiyun						MX23_PAD_GPMI_D15__AUART2_TX
184*4882a593Smuzhiyun					>;
185*4882a593Smuzhiyun					fsl,drive-strength = <MXS_DRIVE_4mA>;
186*4882a593Smuzhiyun					fsl,voltage = <MXS_VOLTAGE_HIGH>;
187*4882a593Smuzhiyun					fsl,pull-up = <MXS_PULL_DISABLE>;
188*4882a593Smuzhiyun				};
189*4882a593Smuzhiyun
190*4882a593Smuzhiyun				gpmi_pins_a: gpmi-nand@0 {
191*4882a593Smuzhiyun					reg = <0>;
192*4882a593Smuzhiyun					fsl,pinmux-ids = <
193*4882a593Smuzhiyun						MX23_PAD_GPMI_D00__GPMI_D00
194*4882a593Smuzhiyun						MX23_PAD_GPMI_D01__GPMI_D01
195*4882a593Smuzhiyun						MX23_PAD_GPMI_D02__GPMI_D02
196*4882a593Smuzhiyun						MX23_PAD_GPMI_D03__GPMI_D03
197*4882a593Smuzhiyun						MX23_PAD_GPMI_D04__GPMI_D04
198*4882a593Smuzhiyun						MX23_PAD_GPMI_D05__GPMI_D05
199*4882a593Smuzhiyun						MX23_PAD_GPMI_D06__GPMI_D06
200*4882a593Smuzhiyun						MX23_PAD_GPMI_D07__GPMI_D07
201*4882a593Smuzhiyun						MX23_PAD_GPMI_CLE__GPMI_CLE
202*4882a593Smuzhiyun						MX23_PAD_GPMI_ALE__GPMI_ALE
203*4882a593Smuzhiyun						MX23_PAD_GPMI_RDY0__GPMI_RDY0
204*4882a593Smuzhiyun						MX23_PAD_GPMI_RDY1__GPMI_RDY1
205*4882a593Smuzhiyun						MX23_PAD_GPMI_WPN__GPMI_WPN
206*4882a593Smuzhiyun						MX23_PAD_GPMI_WRN__GPMI_WRN
207*4882a593Smuzhiyun						MX23_PAD_GPMI_RDN__GPMI_RDN
208*4882a593Smuzhiyun						MX23_PAD_GPMI_CE1N__GPMI_CE1N
209*4882a593Smuzhiyun						MX23_PAD_GPMI_CE0N__GPMI_CE0N
210*4882a593Smuzhiyun					>;
211*4882a593Smuzhiyun					fsl,drive-strength = <MXS_DRIVE_4mA>;
212*4882a593Smuzhiyun					fsl,voltage = <MXS_VOLTAGE_HIGH>;
213*4882a593Smuzhiyun					fsl,pull-up = <MXS_PULL_DISABLE>;
214*4882a593Smuzhiyun				};
215*4882a593Smuzhiyun
216*4882a593Smuzhiyun				gpmi_pins_fixup: gpmi-pins-fixup@0 {
217*4882a593Smuzhiyun					reg = <0>;
218*4882a593Smuzhiyun					fsl,pinmux-ids = <
219*4882a593Smuzhiyun						MX23_PAD_GPMI_WPN__GPMI_WPN
220*4882a593Smuzhiyun						MX23_PAD_GPMI_WRN__GPMI_WRN
221*4882a593Smuzhiyun						MX23_PAD_GPMI_RDN__GPMI_RDN
222*4882a593Smuzhiyun					>;
223*4882a593Smuzhiyun					fsl,drive-strength = <MXS_DRIVE_12mA>;
224*4882a593Smuzhiyun				};
225*4882a593Smuzhiyun
226*4882a593Smuzhiyun				mmc0_4bit_pins_a: mmc0-4bit@0 {
227*4882a593Smuzhiyun					reg = <0>;
228*4882a593Smuzhiyun					fsl,pinmux-ids = <
229*4882a593Smuzhiyun						MX23_PAD_SSP1_DATA0__SSP1_DATA0
230*4882a593Smuzhiyun						MX23_PAD_SSP1_DATA1__SSP1_DATA1
231*4882a593Smuzhiyun						MX23_PAD_SSP1_DATA2__SSP1_DATA2
232*4882a593Smuzhiyun						MX23_PAD_SSP1_DATA3__SSP1_DATA3
233*4882a593Smuzhiyun						MX23_PAD_SSP1_CMD__SSP1_CMD
234*4882a593Smuzhiyun						MX23_PAD_SSP1_SCK__SSP1_SCK
235*4882a593Smuzhiyun					>;
236*4882a593Smuzhiyun					fsl,drive-strength = <MXS_DRIVE_8mA>;
237*4882a593Smuzhiyun					fsl,voltage = <MXS_VOLTAGE_HIGH>;
238*4882a593Smuzhiyun					fsl,pull-up = <MXS_PULL_ENABLE>;
239*4882a593Smuzhiyun				};
240*4882a593Smuzhiyun
241*4882a593Smuzhiyun				mmc0_8bit_pins_a: mmc0-8bit@0 {
242*4882a593Smuzhiyun					reg = <0>;
243*4882a593Smuzhiyun					fsl,pinmux-ids = <
244*4882a593Smuzhiyun						MX23_PAD_SSP1_DATA0__SSP1_DATA0
245*4882a593Smuzhiyun						MX23_PAD_SSP1_DATA1__SSP1_DATA1
246*4882a593Smuzhiyun						MX23_PAD_SSP1_DATA2__SSP1_DATA2
247*4882a593Smuzhiyun						MX23_PAD_SSP1_DATA3__SSP1_DATA3
248*4882a593Smuzhiyun						MX23_PAD_GPMI_D08__SSP1_DATA4
249*4882a593Smuzhiyun						MX23_PAD_GPMI_D09__SSP1_DATA5
250*4882a593Smuzhiyun						MX23_PAD_GPMI_D10__SSP1_DATA6
251*4882a593Smuzhiyun						MX23_PAD_GPMI_D11__SSP1_DATA7
252*4882a593Smuzhiyun						MX23_PAD_SSP1_CMD__SSP1_CMD
253*4882a593Smuzhiyun						MX23_PAD_SSP1_DETECT__SSP1_DETECT
254*4882a593Smuzhiyun						MX23_PAD_SSP1_SCK__SSP1_SCK
255*4882a593Smuzhiyun					>;
256*4882a593Smuzhiyun					fsl,drive-strength = <MXS_DRIVE_8mA>;
257*4882a593Smuzhiyun					fsl,voltage = <MXS_VOLTAGE_HIGH>;
258*4882a593Smuzhiyun					fsl,pull-up = <MXS_PULL_ENABLE>;
259*4882a593Smuzhiyun				};
260*4882a593Smuzhiyun
261*4882a593Smuzhiyun				mmc0_pins_fixup: mmc0-pins-fixup@0 {
262*4882a593Smuzhiyun					reg = <0>;
263*4882a593Smuzhiyun					fsl,pinmux-ids = <
264*4882a593Smuzhiyun						MX23_PAD_SSP1_DETECT__SSP1_DETECT
265*4882a593Smuzhiyun						MX23_PAD_SSP1_SCK__SSP1_SCK
266*4882a593Smuzhiyun					>;
267*4882a593Smuzhiyun					fsl,pull-up = <MXS_PULL_DISABLE>;
268*4882a593Smuzhiyun				};
269*4882a593Smuzhiyun
270*4882a593Smuzhiyun				mmc0_sck_cfg: mmc0-sck-cfg@0 {
271*4882a593Smuzhiyun					reg = <0>;
272*4882a593Smuzhiyun					fsl,pinmux-ids = <
273*4882a593Smuzhiyun						MX23_PAD_SSP1_SCK__SSP1_SCK
274*4882a593Smuzhiyun					>;
275*4882a593Smuzhiyun					fsl,pull-up = <MXS_PULL_DISABLE>;
276*4882a593Smuzhiyun				};
277*4882a593Smuzhiyun
278*4882a593Smuzhiyun				mmc1_4bit_pins_a: mmc1-4bit@0 {
279*4882a593Smuzhiyun					reg = <0>;
280*4882a593Smuzhiyun					fsl,pinmux-ids = <
281*4882a593Smuzhiyun						MX23_PAD_GPMI_D00__SSP2_DATA0
282*4882a593Smuzhiyun						MX23_PAD_GPMI_D01__SSP2_DATA1
283*4882a593Smuzhiyun						MX23_PAD_GPMI_D02__SSP2_DATA2
284*4882a593Smuzhiyun						MX23_PAD_GPMI_D03__SSP2_DATA3
285*4882a593Smuzhiyun						MX23_PAD_GPMI_RDY1__SSP2_CMD
286*4882a593Smuzhiyun						MX23_PAD_GPMI_WRN__SSP2_SCK
287*4882a593Smuzhiyun					>;
288*4882a593Smuzhiyun					fsl,drive-strength = <MXS_DRIVE_8mA>;
289*4882a593Smuzhiyun					fsl,voltage = <MXS_VOLTAGE_HIGH>;
290*4882a593Smuzhiyun					fsl,pull-up = <MXS_PULL_ENABLE>;
291*4882a593Smuzhiyun				};
292*4882a593Smuzhiyun
293*4882a593Smuzhiyun				mmc1_8bit_pins_a: mmc1-8bit@0 {
294*4882a593Smuzhiyun					reg = <0>;
295*4882a593Smuzhiyun					fsl,pinmux-ids = <
296*4882a593Smuzhiyun						MX23_PAD_GPMI_D00__SSP2_DATA0
297*4882a593Smuzhiyun						MX23_PAD_GPMI_D01__SSP2_DATA1
298*4882a593Smuzhiyun						MX23_PAD_GPMI_D02__SSP2_DATA2
299*4882a593Smuzhiyun						MX23_PAD_GPMI_D03__SSP2_DATA3
300*4882a593Smuzhiyun						MX23_PAD_GPMI_D04__SSP2_DATA4
301*4882a593Smuzhiyun						MX23_PAD_GPMI_D05__SSP2_DATA5
302*4882a593Smuzhiyun						MX23_PAD_GPMI_D06__SSP2_DATA6
303*4882a593Smuzhiyun						MX23_PAD_GPMI_D07__SSP2_DATA7
304*4882a593Smuzhiyun						MX23_PAD_GPMI_RDY1__SSP2_CMD
305*4882a593Smuzhiyun						MX23_PAD_GPMI_WRN__SSP2_SCK
306*4882a593Smuzhiyun					>;
307*4882a593Smuzhiyun					fsl,drive-strength = <MXS_DRIVE_8mA>;
308*4882a593Smuzhiyun					fsl,voltage = <MXS_VOLTAGE_HIGH>;
309*4882a593Smuzhiyun					fsl,pull-up = <MXS_PULL_ENABLE>;
310*4882a593Smuzhiyun				};
311*4882a593Smuzhiyun
312*4882a593Smuzhiyun				pwm2_pins_a: pwm2@0 {
313*4882a593Smuzhiyun					reg = <0>;
314*4882a593Smuzhiyun					fsl,pinmux-ids = <
315*4882a593Smuzhiyun						MX23_PAD_PWM2__PWM2
316*4882a593Smuzhiyun					>;
317*4882a593Smuzhiyun					fsl,drive-strength = <MXS_DRIVE_4mA>;
318*4882a593Smuzhiyun					fsl,voltage = <MXS_VOLTAGE_HIGH>;
319*4882a593Smuzhiyun					fsl,pull-up = <MXS_PULL_DISABLE>;
320*4882a593Smuzhiyun				};
321*4882a593Smuzhiyun
322*4882a593Smuzhiyun				lcdif_24bit_pins_a: lcdif-24bit@0 {
323*4882a593Smuzhiyun					reg = <0>;
324*4882a593Smuzhiyun					fsl,pinmux-ids = <
325*4882a593Smuzhiyun						MX23_PAD_LCD_D00__LCD_D00
326*4882a593Smuzhiyun						MX23_PAD_LCD_D01__LCD_D01
327*4882a593Smuzhiyun						MX23_PAD_LCD_D02__LCD_D02
328*4882a593Smuzhiyun						MX23_PAD_LCD_D03__LCD_D03
329*4882a593Smuzhiyun						MX23_PAD_LCD_D04__LCD_D04
330*4882a593Smuzhiyun						MX23_PAD_LCD_D05__LCD_D05
331*4882a593Smuzhiyun						MX23_PAD_LCD_D06__LCD_D06
332*4882a593Smuzhiyun						MX23_PAD_LCD_D07__LCD_D07
333*4882a593Smuzhiyun						MX23_PAD_LCD_D08__LCD_D08
334*4882a593Smuzhiyun						MX23_PAD_LCD_D09__LCD_D09
335*4882a593Smuzhiyun						MX23_PAD_LCD_D10__LCD_D10
336*4882a593Smuzhiyun						MX23_PAD_LCD_D11__LCD_D11
337*4882a593Smuzhiyun						MX23_PAD_LCD_D12__LCD_D12
338*4882a593Smuzhiyun						MX23_PAD_LCD_D13__LCD_D13
339*4882a593Smuzhiyun						MX23_PAD_LCD_D14__LCD_D14
340*4882a593Smuzhiyun						MX23_PAD_LCD_D15__LCD_D15
341*4882a593Smuzhiyun						MX23_PAD_LCD_D16__LCD_D16
342*4882a593Smuzhiyun						MX23_PAD_LCD_D17__LCD_D17
343*4882a593Smuzhiyun						MX23_PAD_GPMI_D08__LCD_D18
344*4882a593Smuzhiyun						MX23_PAD_GPMI_D09__LCD_D19
345*4882a593Smuzhiyun						MX23_PAD_GPMI_D10__LCD_D20
346*4882a593Smuzhiyun						MX23_PAD_GPMI_D11__LCD_D21
347*4882a593Smuzhiyun						MX23_PAD_GPMI_D12__LCD_D22
348*4882a593Smuzhiyun						MX23_PAD_GPMI_D13__LCD_D23
349*4882a593Smuzhiyun						MX23_PAD_LCD_DOTCK__LCD_DOTCK
350*4882a593Smuzhiyun						MX23_PAD_LCD_ENABLE__LCD_ENABLE
351*4882a593Smuzhiyun						MX23_PAD_LCD_HSYNC__LCD_HSYNC
352*4882a593Smuzhiyun						MX23_PAD_LCD_VSYNC__LCD_VSYNC
353*4882a593Smuzhiyun					>;
354*4882a593Smuzhiyun					fsl,drive-strength = <MXS_DRIVE_4mA>;
355*4882a593Smuzhiyun					fsl,voltage = <MXS_VOLTAGE_HIGH>;
356*4882a593Smuzhiyun					fsl,pull-up = <MXS_PULL_DISABLE>;
357*4882a593Smuzhiyun				};
358*4882a593Smuzhiyun
359*4882a593Smuzhiyun				spi2_pins_a: spi2@0 {
360*4882a593Smuzhiyun					reg = <0>;
361*4882a593Smuzhiyun					fsl,pinmux-ids = <
362*4882a593Smuzhiyun						MX23_PAD_GPMI_WRN__SSP2_SCK
363*4882a593Smuzhiyun						MX23_PAD_GPMI_RDY1__SSP2_CMD
364*4882a593Smuzhiyun						MX23_PAD_GPMI_D00__SSP2_DATA0
365*4882a593Smuzhiyun						MX23_PAD_GPMI_D03__SSP2_DATA3
366*4882a593Smuzhiyun					>;
367*4882a593Smuzhiyun					fsl,drive-strength = <MXS_DRIVE_8mA>;
368*4882a593Smuzhiyun					fsl,voltage = <MXS_VOLTAGE_HIGH>;
369*4882a593Smuzhiyun					fsl,pull-up = <MXS_PULL_ENABLE>;
370*4882a593Smuzhiyun				};
371*4882a593Smuzhiyun
372*4882a593Smuzhiyun				i2c_pins_a: i2c@0 {
373*4882a593Smuzhiyun					reg = <0>;
374*4882a593Smuzhiyun					fsl,pinmux-ids = <
375*4882a593Smuzhiyun						MX23_PAD_I2C_SCL__I2C_SCL
376*4882a593Smuzhiyun						MX23_PAD_I2C_SDA__I2C_SDA
377*4882a593Smuzhiyun					>;
378*4882a593Smuzhiyun					fsl,drive-strength = <MXS_DRIVE_8mA>;
379*4882a593Smuzhiyun					fsl,voltage = <MXS_VOLTAGE_HIGH>;
380*4882a593Smuzhiyun					fsl,pull-up = <MXS_PULL_ENABLE>;
381*4882a593Smuzhiyun				};
382*4882a593Smuzhiyun
383*4882a593Smuzhiyun				i2c_pins_b: i2c@1 {
384*4882a593Smuzhiyun					reg = <1>;
385*4882a593Smuzhiyun					fsl,pinmux-ids = <
386*4882a593Smuzhiyun						MX23_PAD_LCD_ENABLE__I2C_SCL
387*4882a593Smuzhiyun						MX23_PAD_LCD_HSYNC__I2C_SDA
388*4882a593Smuzhiyun					>;
389*4882a593Smuzhiyun					fsl,drive-strength = <MXS_DRIVE_8mA>;
390*4882a593Smuzhiyun					fsl,voltage = <MXS_VOLTAGE_HIGH>;
391*4882a593Smuzhiyun					fsl,pull-up = <MXS_PULL_ENABLE>;
392*4882a593Smuzhiyun				};
393*4882a593Smuzhiyun
394*4882a593Smuzhiyun				i2c_pins_c: i2c@2 {
395*4882a593Smuzhiyun					reg = <2>;
396*4882a593Smuzhiyun					fsl,pinmux-ids = <
397*4882a593Smuzhiyun						MX23_PAD_SSP1_DATA1__I2C_SCL
398*4882a593Smuzhiyun						MX23_PAD_SSP1_DATA2__I2C_SDA
399*4882a593Smuzhiyun					>;
400*4882a593Smuzhiyun					fsl,drive-strength = <MXS_DRIVE_8mA>;
401*4882a593Smuzhiyun					fsl,voltage = <MXS_VOLTAGE_HIGH>;
402*4882a593Smuzhiyun					fsl,pull-up = <MXS_PULL_ENABLE>;
403*4882a593Smuzhiyun				};
404*4882a593Smuzhiyun			};
405*4882a593Smuzhiyun
406*4882a593Smuzhiyun			digctl@8001c000 {
407*4882a593Smuzhiyun				compatible = "fsl,imx23-digctl";
408*4882a593Smuzhiyun				reg = <0x8001c000 2000>;
409*4882a593Smuzhiyun				status = "disabled";
410*4882a593Smuzhiyun			};
411*4882a593Smuzhiyun
412*4882a593Smuzhiyun			emi@80020000 {
413*4882a593Smuzhiyun				reg = <0x80020000 0x2000>;
414*4882a593Smuzhiyun				status = "disabled";
415*4882a593Smuzhiyun			};
416*4882a593Smuzhiyun
417*4882a593Smuzhiyun			dma_apbx: dma-apbx@80024000 {
418*4882a593Smuzhiyun				compatible = "fsl,imx23-dma-apbx";
419*4882a593Smuzhiyun				reg = <0x80024000 0x2000>;
420*4882a593Smuzhiyun				interrupts = <7 5 9 26
421*4882a593Smuzhiyun					      19 0 25 23
422*4882a593Smuzhiyun					      60 58 9 0
423*4882a593Smuzhiyun					      0 0 0 0>;
424*4882a593Smuzhiyun				interrupt-names = "audio-adc", "audio-dac", "spdif-tx", "i2c",
425*4882a593Smuzhiyun						  "saif0", "empty", "auart0-rx", "auart0-tx",
426*4882a593Smuzhiyun						  "auart1-rx", "auart1-tx", "saif1", "empty",
427*4882a593Smuzhiyun						  "empty", "empty", "empty", "empty";
428*4882a593Smuzhiyun				#dma-cells = <1>;
429*4882a593Smuzhiyun				dma-channels = <16>;
430*4882a593Smuzhiyun				clocks = <&clks 16>;
431*4882a593Smuzhiyun			};
432*4882a593Smuzhiyun
433*4882a593Smuzhiyun			dcp: crypto@80028000 {
434*4882a593Smuzhiyun				compatible = "fsl,imx23-dcp";
435*4882a593Smuzhiyun				reg = <0x80028000 0x2000>;
436*4882a593Smuzhiyun				interrupts = <53 54>;
437*4882a593Smuzhiyun				status = "okay";
438*4882a593Smuzhiyun			};
439*4882a593Smuzhiyun
440*4882a593Smuzhiyun			pxp@8002a000 {
441*4882a593Smuzhiyun				reg = <0x8002a000 0x2000>;
442*4882a593Smuzhiyun				status = "disabled";
443*4882a593Smuzhiyun			};
444*4882a593Smuzhiyun
445*4882a593Smuzhiyun			efuse@8002c000 {
446*4882a593Smuzhiyun				compatible = "fsl,imx23-ocotp", "fsl,ocotp";
447*4882a593Smuzhiyun				#address-cells = <1>;
448*4882a593Smuzhiyun				#size-cells = <1>;
449*4882a593Smuzhiyun				reg = <0x8002c000 0x2000>;
450*4882a593Smuzhiyun				clocks = <&clks 15>;
451*4882a593Smuzhiyun			};
452*4882a593Smuzhiyun
453*4882a593Smuzhiyun			axi-ahb@8002e000 {
454*4882a593Smuzhiyun				reg = <0x8002e000 0x2000>;
455*4882a593Smuzhiyun				status = "disabled";
456*4882a593Smuzhiyun			};
457*4882a593Smuzhiyun
458*4882a593Smuzhiyun			lcdif@80030000 {
459*4882a593Smuzhiyun				compatible = "fsl,imx23-lcdif";
460*4882a593Smuzhiyun				reg = <0x80030000 2000>;
461*4882a593Smuzhiyun				interrupts = <46 45>;
462*4882a593Smuzhiyun				clocks = <&clks 38>;
463*4882a593Smuzhiyun				status = "disabled";
464*4882a593Smuzhiyun			};
465*4882a593Smuzhiyun
466*4882a593Smuzhiyun			ssp1: spi@80034000 {
467*4882a593Smuzhiyun				reg = <0x80034000 0x2000>;
468*4882a593Smuzhiyun				interrupts = <2>;
469*4882a593Smuzhiyun				clocks = <&clks 33>;
470*4882a593Smuzhiyun				dmas = <&dma_apbh 2>;
471*4882a593Smuzhiyun				dma-names = "rx-tx";
472*4882a593Smuzhiyun				status = "disabled";
473*4882a593Smuzhiyun			};
474*4882a593Smuzhiyun
475*4882a593Smuzhiyun			tvenc@80038000 {
476*4882a593Smuzhiyun				reg = <0x80038000 0x2000>;
477*4882a593Smuzhiyun				status = "disabled";
478*4882a593Smuzhiyun			};
479*4882a593Smuzhiyun		};
480*4882a593Smuzhiyun
481*4882a593Smuzhiyun		apbx@80040000 {
482*4882a593Smuzhiyun			compatible = "simple-bus";
483*4882a593Smuzhiyun			#address-cells = <1>;
484*4882a593Smuzhiyun			#size-cells = <1>;
485*4882a593Smuzhiyun			reg = <0x80040000 0x40000>;
486*4882a593Smuzhiyun			ranges;
487*4882a593Smuzhiyun
488*4882a593Smuzhiyun			clks: clkctrl@80040000 {
489*4882a593Smuzhiyun				compatible = "fsl,imx23-clkctrl", "fsl,clkctrl";
490*4882a593Smuzhiyun				reg = <0x80040000 0x2000>;
491*4882a593Smuzhiyun				#clock-cells = <1>;
492*4882a593Smuzhiyun			};
493*4882a593Smuzhiyun
494*4882a593Smuzhiyun			saif0: saif@80042000 {
495*4882a593Smuzhiyun				reg = <0x80042000 0x2000>;
496*4882a593Smuzhiyun				dmas = <&dma_apbx 4>;
497*4882a593Smuzhiyun				dma-names = "rx-tx";
498*4882a593Smuzhiyun				status = "disabled";
499*4882a593Smuzhiyun			};
500*4882a593Smuzhiyun
501*4882a593Smuzhiyun			power@80044000 {
502*4882a593Smuzhiyun				reg = <0x80044000 0x2000>;
503*4882a593Smuzhiyun				status = "disabled";
504*4882a593Smuzhiyun			};
505*4882a593Smuzhiyun
506*4882a593Smuzhiyun			saif1: saif@80046000 {
507*4882a593Smuzhiyun				reg = <0x80046000 0x2000>;
508*4882a593Smuzhiyun				dmas = <&dma_apbx 10>;
509*4882a593Smuzhiyun				dma-names = "rx-tx";
510*4882a593Smuzhiyun				status = "disabled";
511*4882a593Smuzhiyun			};
512*4882a593Smuzhiyun
513*4882a593Smuzhiyun			audio-out@80048000 {
514*4882a593Smuzhiyun				reg = <0x80048000 0x2000>;
515*4882a593Smuzhiyun				dmas = <&dma_apbx 1>;
516*4882a593Smuzhiyun				dma-names = "tx";
517*4882a593Smuzhiyun				status = "disabled";
518*4882a593Smuzhiyun			};
519*4882a593Smuzhiyun
520*4882a593Smuzhiyun			audio-in@8004c000 {
521*4882a593Smuzhiyun				reg = <0x8004c000 0x2000>;
522*4882a593Smuzhiyun				dmas = <&dma_apbx 0>;
523*4882a593Smuzhiyun				dma-names = "rx";
524*4882a593Smuzhiyun				status = "disabled";
525*4882a593Smuzhiyun			};
526*4882a593Smuzhiyun
527*4882a593Smuzhiyun			lradc: lradc@80050000 {
528*4882a593Smuzhiyun				compatible = "fsl,imx23-lradc";
529*4882a593Smuzhiyun				reg = <0x80050000 0x2000>;
530*4882a593Smuzhiyun				interrupts = <36 37 38 39 40 41 42 43 44>;
531*4882a593Smuzhiyun				status = "disabled";
532*4882a593Smuzhiyun				clocks = <&clks 26>;
533*4882a593Smuzhiyun				#io-channel-cells = <1>;
534*4882a593Smuzhiyun			};
535*4882a593Smuzhiyun
536*4882a593Smuzhiyun			spdif@80054000 {
537*4882a593Smuzhiyun				reg = <0x80054000 2000>;
538*4882a593Smuzhiyun				dmas = <&dma_apbx 2>;
539*4882a593Smuzhiyun				dma-names = "tx";
540*4882a593Smuzhiyun				status = "disabled";
541*4882a593Smuzhiyun			};
542*4882a593Smuzhiyun
543*4882a593Smuzhiyun			i2c: i2c@80058000 {
544*4882a593Smuzhiyun				#address-cells = <1>;
545*4882a593Smuzhiyun				#size-cells = <0>;
546*4882a593Smuzhiyun				compatible = "fsl,imx23-i2c";
547*4882a593Smuzhiyun				reg = <0x80058000 0x2000>;
548*4882a593Smuzhiyun				interrupts = <27>;
549*4882a593Smuzhiyun				clock-frequency = <100000>;
550*4882a593Smuzhiyun				dmas = <&dma_apbx 3>;
551*4882a593Smuzhiyun				dma-names = "rx-tx";
552*4882a593Smuzhiyun				status = "disabled";
553*4882a593Smuzhiyun			};
554*4882a593Smuzhiyun
555*4882a593Smuzhiyun			rtc@8005c000 {
556*4882a593Smuzhiyun				compatible = "fsl,imx23-rtc", "fsl,stmp3xxx-rtc";
557*4882a593Smuzhiyun				reg = <0x8005c000 0x2000>;
558*4882a593Smuzhiyun				interrupts = <22>;
559*4882a593Smuzhiyun			};
560*4882a593Smuzhiyun
561*4882a593Smuzhiyun			pwm: pwm@80064000 {
562*4882a593Smuzhiyun				compatible = "fsl,imx23-pwm";
563*4882a593Smuzhiyun				reg = <0x80064000 0x2000>;
564*4882a593Smuzhiyun				clocks = <&clks 30>;
565*4882a593Smuzhiyun				#pwm-cells = <2>;
566*4882a593Smuzhiyun				fsl,pwm-number = <5>;
567*4882a593Smuzhiyun				status = "disabled";
568*4882a593Smuzhiyun			};
569*4882a593Smuzhiyun
570*4882a593Smuzhiyun			timrot@80068000 {
571*4882a593Smuzhiyun				compatible = "fsl,imx23-timrot", "fsl,timrot";
572*4882a593Smuzhiyun				reg = <0x80068000 0x2000>;
573*4882a593Smuzhiyun				interrupts = <28 29 30 31>;
574*4882a593Smuzhiyun				clocks = <&clks 28>;
575*4882a593Smuzhiyun			};
576*4882a593Smuzhiyun
577*4882a593Smuzhiyun			auart0: serial@8006c000 {
578*4882a593Smuzhiyun				compatible = "fsl,imx23-auart";
579*4882a593Smuzhiyun				reg = <0x8006c000 0x2000>;
580*4882a593Smuzhiyun				interrupts = <24>;
581*4882a593Smuzhiyun				clocks = <&clks 32>;
582*4882a593Smuzhiyun				dmas = <&dma_apbx 6>, <&dma_apbx 7>;
583*4882a593Smuzhiyun				dma-names = "rx", "tx";
584*4882a593Smuzhiyun				status = "disabled";
585*4882a593Smuzhiyun			};
586*4882a593Smuzhiyun
587*4882a593Smuzhiyun			auart1: serial@8006e000 {
588*4882a593Smuzhiyun				compatible = "fsl,imx23-auart";
589*4882a593Smuzhiyun				reg = <0x8006e000 0x2000>;
590*4882a593Smuzhiyun				interrupts = <59>;
591*4882a593Smuzhiyun				clocks = <&clks 32>;
592*4882a593Smuzhiyun				dmas = <&dma_apbx 8>, <&dma_apbx 9>;
593*4882a593Smuzhiyun				dma-names = "rx", "tx";
594*4882a593Smuzhiyun				status = "disabled";
595*4882a593Smuzhiyun			};
596*4882a593Smuzhiyun
597*4882a593Smuzhiyun			duart: serial@80070000 {
598*4882a593Smuzhiyun				compatible = "arm,pl011", "arm,primecell";
599*4882a593Smuzhiyun				reg = <0x80070000 0x2000>;
600*4882a593Smuzhiyun				interrupts = <0>;
601*4882a593Smuzhiyun				clocks = <&clks 32>, <&clks 16>;
602*4882a593Smuzhiyun				clock-names = "uart", "apb_pclk";
603*4882a593Smuzhiyun				status = "disabled";
604*4882a593Smuzhiyun			};
605*4882a593Smuzhiyun
606*4882a593Smuzhiyun			usbphy0: usbphy@8007c000 {
607*4882a593Smuzhiyun				compatible = "fsl,imx23-usbphy";
608*4882a593Smuzhiyun				reg = <0x8007c000 0x2000>;
609*4882a593Smuzhiyun				clocks = <&clks 41>;
610*4882a593Smuzhiyun				status = "disabled";
611*4882a593Smuzhiyun			};
612*4882a593Smuzhiyun		};
613*4882a593Smuzhiyun	};
614*4882a593Smuzhiyun
615*4882a593Smuzhiyun	ahb@80080000 {
616*4882a593Smuzhiyun		compatible = "simple-bus";
617*4882a593Smuzhiyun		#address-cells = <1>;
618*4882a593Smuzhiyun		#size-cells = <1>;
619*4882a593Smuzhiyun		reg = <0x80080000 0x80000>;
620*4882a593Smuzhiyun		ranges;
621*4882a593Smuzhiyun
622*4882a593Smuzhiyun		usb0: usb@80080000 {
623*4882a593Smuzhiyun			compatible = "fsl,imx23-usb", "fsl,imx27-usb";
624*4882a593Smuzhiyun			reg = <0x80080000 0x40000>;
625*4882a593Smuzhiyun			interrupts = <11>;
626*4882a593Smuzhiyun			fsl,usbphy = <&usbphy0>;
627*4882a593Smuzhiyun			clocks = <&clks 40>;
628*4882a593Smuzhiyun			status = "disabled";
629*4882a593Smuzhiyun		};
630*4882a593Smuzhiyun	};
631*4882a593Smuzhiyun
632*4882a593Smuzhiyun	iio-hwmon {
633*4882a593Smuzhiyun		compatible = "iio-hwmon";
634*4882a593Smuzhiyun		io-channels = <&lradc 8>;
635*4882a593Smuzhiyun	};
636*4882a593Smuzhiyun};
637