1*4882a593Smuzhiyun// SPDX-License-Identifier: GPL-2.0-only 2*4882a593Smuzhiyun/* 3*4882a593Smuzhiyun * Copyright (C) 2013-2014 Linaro Ltd. 4*4882a593Smuzhiyun * Author: Haojian Zhuang <haojian.zhuang@linaro.org> 5*4882a593Smuzhiyun */ 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun/dts-v1/; 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun#include "hip04.dtsi" 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun/ { 12*4882a593Smuzhiyun /* memory bus is 64-bit */ 13*4882a593Smuzhiyun #address-cells = <2>; 14*4882a593Smuzhiyun #size-cells = <2>; 15*4882a593Smuzhiyun model = "Hisilicon D01 Development Board"; 16*4882a593Smuzhiyun compatible = "hisilicon,hip04-d01"; 17*4882a593Smuzhiyun 18*4882a593Smuzhiyun memory@0,10000000 { 19*4882a593Smuzhiyun device_type = "memory"; 20*4882a593Smuzhiyun reg = <0x00000000 0x10000000 0x00000000 0xc0000000>, 21*4882a593Smuzhiyun <0x00000004 0xc0000000 0x00000003 0x40000000>; 22*4882a593Smuzhiyun }; 23*4882a593Smuzhiyun 24*4882a593Smuzhiyun soc { 25*4882a593Smuzhiyun uart0: uart@4007000 { 26*4882a593Smuzhiyun status = "ok"; 27*4882a593Smuzhiyun }; 28*4882a593Smuzhiyun }; 29*4882a593Smuzhiyun}; 30