1*4882a593Smuzhiyun// SPDX-License-Identifier: GPL-2.0-only 2*4882a593Smuzhiyun/* 3*4882a593Smuzhiyun * Copyright (C) 2012-2013 Linaro Ltd. 4*4882a593Smuzhiyun * Author: Haojian Zhuang <haojian.zhuang@linaro.org> 5*4882a593Smuzhiyun */ 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun/dts-v1/; 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun#include "hi3620.dtsi" 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun/ { 12*4882a593Smuzhiyun model = "Hisilicon Hi4511 Development Board"; 13*4882a593Smuzhiyun compatible = "hisilicon,hi3620-hi4511"; 14*4882a593Smuzhiyun 15*4882a593Smuzhiyun chosen { 16*4882a593Smuzhiyun bootargs = "root=/dev/ram0"; 17*4882a593Smuzhiyun stdout-path = "serial0:115200n8"; 18*4882a593Smuzhiyun }; 19*4882a593Smuzhiyun 20*4882a593Smuzhiyun memory { 21*4882a593Smuzhiyun device_type = "memory"; 22*4882a593Smuzhiyun reg = <0x40000000 0x20000000>; 23*4882a593Smuzhiyun }; 24*4882a593Smuzhiyun 25*4882a593Smuzhiyun amba { 26*4882a593Smuzhiyun dual_timer0: dual_timer@800000 { 27*4882a593Smuzhiyun status = "ok"; 28*4882a593Smuzhiyun }; 29*4882a593Smuzhiyun 30*4882a593Smuzhiyun uart0: uart@b00000 { /* console */ 31*4882a593Smuzhiyun pinctrl-names = "default", "idle"; 32*4882a593Smuzhiyun pinctrl-0 = <&uart0_pmx_func &uart0_cfg_func>; 33*4882a593Smuzhiyun pinctrl-1 = <&uart0_pmx_idle &uart0_cfg_idle>; 34*4882a593Smuzhiyun status = "ok"; 35*4882a593Smuzhiyun }; 36*4882a593Smuzhiyun 37*4882a593Smuzhiyun uart1: uart@b01000 { /* modem */ 38*4882a593Smuzhiyun pinctrl-names = "default", "idle"; 39*4882a593Smuzhiyun pinctrl-0 = <&uart1_pmx_func &uart1_cfg_func>; 40*4882a593Smuzhiyun pinctrl-1 = <&uart1_pmx_idle &uart1_cfg_idle>; 41*4882a593Smuzhiyun status = "ok"; 42*4882a593Smuzhiyun }; 43*4882a593Smuzhiyun 44*4882a593Smuzhiyun uart2: uart@b02000 { /* audience */ 45*4882a593Smuzhiyun pinctrl-names = "default", "idle"; 46*4882a593Smuzhiyun pinctrl-0 = <&uart2_pmx_func &uart2_cfg_func>; 47*4882a593Smuzhiyun pinctrl-1 = <&uart2_pmx_idle &uart2_cfg_idle>; 48*4882a593Smuzhiyun status = "ok"; 49*4882a593Smuzhiyun }; 50*4882a593Smuzhiyun 51*4882a593Smuzhiyun uart3: uart@b03000 { 52*4882a593Smuzhiyun pinctrl-names = "default", "idle"; 53*4882a593Smuzhiyun pinctrl-0 = <&uart3_pmx_func &uart3_cfg_func>; 54*4882a593Smuzhiyun pinctrl-1 = <&uart3_pmx_idle &uart3_cfg_idle>; 55*4882a593Smuzhiyun status = "ok"; 56*4882a593Smuzhiyun }; 57*4882a593Smuzhiyun 58*4882a593Smuzhiyun uart4: uart@b04000 { 59*4882a593Smuzhiyun pinctrl-names = "default", "idle"; 60*4882a593Smuzhiyun pinctrl-0 = <&uart4_pmx_func &uart4_cfg_func>; 61*4882a593Smuzhiyun pinctrl-1 = <&uart4_pmx_idle &uart4_cfg_func>; 62*4882a593Smuzhiyun status = "ok"; 63*4882a593Smuzhiyun }; 64*4882a593Smuzhiyun 65*4882a593Smuzhiyun pmx0: pinmux@803000 { 66*4882a593Smuzhiyun pinctrl-names = "default"; 67*4882a593Smuzhiyun pinctrl-0 = <&board_pmx_pins>; 68*4882a593Smuzhiyun 69*4882a593Smuzhiyun board_pmx_pins: board_pmx_pins { 70*4882a593Smuzhiyun pinctrl-single,pins = < 71*4882a593Smuzhiyun 0x008 0x0 /* GPIO -- eFUSE_DOUT */ 72*4882a593Smuzhiyun 0x100 0x0 /* USIM_CLK & USIM_DATA (IOMG63) */ 73*4882a593Smuzhiyun >; 74*4882a593Smuzhiyun }; 75*4882a593Smuzhiyun uart0_pmx_func: uart0_pmx_func { 76*4882a593Smuzhiyun pinctrl-single,pins = < 77*4882a593Smuzhiyun 0x0f0 0x0 78*4882a593Smuzhiyun 0x0f4 0x0 /* UART0_RX & UART0_TX */ 79*4882a593Smuzhiyun >; 80*4882a593Smuzhiyun }; 81*4882a593Smuzhiyun uart0_pmx_idle: uart0_pmx_idle { 82*4882a593Smuzhiyun pinctrl-single,pins = < 83*4882a593Smuzhiyun /*0x0f0 0x1*/ /* UART0_CTS & UART0_RTS */ 84*4882a593Smuzhiyun 0x0f4 0x1 /* UART0_RX & UART0_TX */ 85*4882a593Smuzhiyun >; 86*4882a593Smuzhiyun }; 87*4882a593Smuzhiyun uart1_pmx_func: uart1_pmx_func { 88*4882a593Smuzhiyun pinctrl-single,pins = < 89*4882a593Smuzhiyun 0x0f8 0x0 /* UART1_CTS & UART1_RTS (IOMG61) */ 90*4882a593Smuzhiyun 0x0fc 0x0 /* UART1_RX & UART1_TX (IOMG62) */ 91*4882a593Smuzhiyun >; 92*4882a593Smuzhiyun }; 93*4882a593Smuzhiyun uart1_pmx_idle: uart1_pmx_idle { 94*4882a593Smuzhiyun pinctrl-single,pins = < 95*4882a593Smuzhiyun 0x0f8 0x1 /* GPIO (IOMG61) */ 96*4882a593Smuzhiyun 0x0fc 0x1 /* GPIO (IOMG62) */ 97*4882a593Smuzhiyun >; 98*4882a593Smuzhiyun }; 99*4882a593Smuzhiyun uart2_pmx_func: uart2_pmx_func { 100*4882a593Smuzhiyun pinctrl-single,pins = < 101*4882a593Smuzhiyun 0x104 0x2 /* UART2_RXD (IOMG96) */ 102*4882a593Smuzhiyun 0x108 0x2 /* UART2_TXD (IOMG64) */ 103*4882a593Smuzhiyun >; 104*4882a593Smuzhiyun }; 105*4882a593Smuzhiyun uart2_pmx_idle: uart2_pmx_idle { 106*4882a593Smuzhiyun pinctrl-single,pins = < 107*4882a593Smuzhiyun 0x104 0x1 /* GPIO (IOMG96) */ 108*4882a593Smuzhiyun 0x108 0x1 /* GPIO (IOMG64) */ 109*4882a593Smuzhiyun >; 110*4882a593Smuzhiyun }; 111*4882a593Smuzhiyun uart3_pmx_func: uart3_pmx_func { 112*4882a593Smuzhiyun pinctrl-single,pins = < 113*4882a593Smuzhiyun 0x160 0x2 /* UART3_CTS & UART3_RTS (IOMG85) */ 114*4882a593Smuzhiyun 0x164 0x2 /* UART3_RXD & UART3_TXD (IOMG86) */ 115*4882a593Smuzhiyun >; 116*4882a593Smuzhiyun }; 117*4882a593Smuzhiyun uart3_pmx_idle: uart3_pmx_idle { 118*4882a593Smuzhiyun pinctrl-single,pins = < 119*4882a593Smuzhiyun 0x160 0x1 /* GPIO (IOMG85) */ 120*4882a593Smuzhiyun 0x164 0x1 /* GPIO (IOMG86) */ 121*4882a593Smuzhiyun >; 122*4882a593Smuzhiyun }; 123*4882a593Smuzhiyun uart4_pmx_func: uart4_pmx_func { 124*4882a593Smuzhiyun pinctrl-single,pins = < 125*4882a593Smuzhiyun 0x168 0x0 /* UART4_CTS & UART4_RTS (IOMG87) */ 126*4882a593Smuzhiyun 0x16c 0x0 /* UART4_RXD (IOMG88) */ 127*4882a593Smuzhiyun 0x170 0x0 /* UART4_TXD (IOMG93) */ 128*4882a593Smuzhiyun >; 129*4882a593Smuzhiyun }; 130*4882a593Smuzhiyun uart4_pmx_idle: uart4_pmx_idle { 131*4882a593Smuzhiyun pinctrl-single,pins = < 132*4882a593Smuzhiyun 0x168 0x1 /* GPIO (IOMG87) */ 133*4882a593Smuzhiyun 0x16c 0x1 /* GPIO (IOMG88) */ 134*4882a593Smuzhiyun 0x170 0x1 /* GPIO (IOMG93) */ 135*4882a593Smuzhiyun >; 136*4882a593Smuzhiyun }; 137*4882a593Smuzhiyun i2c0_pmx_func: i2c0_pmx_func { 138*4882a593Smuzhiyun pinctrl-single,pins = < 139*4882a593Smuzhiyun 0x0b4 0x0 /* I2C0_SCL & I2C0_SDA (IOMG45) */ 140*4882a593Smuzhiyun >; 141*4882a593Smuzhiyun }; 142*4882a593Smuzhiyun i2c0_pmx_idle: i2c0_pmx_idle { 143*4882a593Smuzhiyun pinctrl-single,pins = < 144*4882a593Smuzhiyun 0x0b4 0x1 /* GPIO (IOMG45) */ 145*4882a593Smuzhiyun >; 146*4882a593Smuzhiyun }; 147*4882a593Smuzhiyun i2c1_pmx_func: i2c1_pmx_func { 148*4882a593Smuzhiyun pinctrl-single,pins = < 149*4882a593Smuzhiyun 0x0b8 0x0 /* I2C1_SCL & I2C1_SDA (IOMG46) */ 150*4882a593Smuzhiyun >; 151*4882a593Smuzhiyun }; 152*4882a593Smuzhiyun i2c1_pmx_idle: i2c1_pmx_idle { 153*4882a593Smuzhiyun pinctrl-single,pins = < 154*4882a593Smuzhiyun 0x0b8 0x1 /* GPIO (IOMG46) */ 155*4882a593Smuzhiyun >; 156*4882a593Smuzhiyun }; 157*4882a593Smuzhiyun i2c2_pmx_func: i2c2_pmx_func { 158*4882a593Smuzhiyun pinctrl-single,pins = < 159*4882a593Smuzhiyun 0x068 0x0 /* I2C2_SCL (IOMG26) */ 160*4882a593Smuzhiyun 0x06c 0x0 /* I2C2_SDA (IOMG27) */ 161*4882a593Smuzhiyun >; 162*4882a593Smuzhiyun }; 163*4882a593Smuzhiyun i2c2_pmx_idle: i2c2_pmx_idle { 164*4882a593Smuzhiyun pinctrl-single,pins = < 165*4882a593Smuzhiyun 0x068 0x1 /* GPIO (IOMG26) */ 166*4882a593Smuzhiyun 0x06c 0x1 /* GPIO (IOMG27) */ 167*4882a593Smuzhiyun >; 168*4882a593Smuzhiyun }; 169*4882a593Smuzhiyun i2c3_pmx_func: i2c3_pmx_func { 170*4882a593Smuzhiyun pinctrl-single,pins = < 171*4882a593Smuzhiyun 0x050 0x2 /* I2C3_SCL (IOMG20) */ 172*4882a593Smuzhiyun 0x054 0x2 /* I2C3_SDA (IOMG21) */ 173*4882a593Smuzhiyun >; 174*4882a593Smuzhiyun }; 175*4882a593Smuzhiyun i2c3_pmx_idle: i2c3_pmx_idle { 176*4882a593Smuzhiyun pinctrl-single,pins = < 177*4882a593Smuzhiyun 0x050 0x1 /* GPIO (IOMG20) */ 178*4882a593Smuzhiyun 0x054 0x1 /* GPIO (IOMG21) */ 179*4882a593Smuzhiyun >; 180*4882a593Smuzhiyun }; 181*4882a593Smuzhiyun spi0_pmx_func: spi0_pmx_func { 182*4882a593Smuzhiyun pinctrl-single,pins = < 183*4882a593Smuzhiyun 0x0d4 0x0 /* SPI0_CLK/SPI0_DI/SPI0_DO (IOMG53) */ 184*4882a593Smuzhiyun 0x0d8 0x0 /* SPI0_CS0 (IOMG54) */ 185*4882a593Smuzhiyun 0x0dc 0x0 /* SPI0_CS1 (IOMG55) */ 186*4882a593Smuzhiyun 0x0e0 0x0 /* SPI0_CS2 (IOMG56) */ 187*4882a593Smuzhiyun 0x0e4 0x0 /* SPI0_CS3 (IOMG57) */ 188*4882a593Smuzhiyun >; 189*4882a593Smuzhiyun }; 190*4882a593Smuzhiyun spi0_pmx_idle: spi0_pmx_idle { 191*4882a593Smuzhiyun pinctrl-single,pins = < 192*4882a593Smuzhiyun 0x0d4 0x1 /* GPIO (IOMG53) */ 193*4882a593Smuzhiyun 0x0d8 0x1 /* GPIO (IOMG54) */ 194*4882a593Smuzhiyun 0x0dc 0x1 /* GPIO (IOMG55) */ 195*4882a593Smuzhiyun 0x0e0 0x1 /* GPIO (IOMG56) */ 196*4882a593Smuzhiyun 0x0e4 0x1 /* GPIO (IOMG57) */ 197*4882a593Smuzhiyun >; 198*4882a593Smuzhiyun }; 199*4882a593Smuzhiyun spi1_pmx_func: spi1_pmx_func { 200*4882a593Smuzhiyun pinctrl-single,pins = < 201*4882a593Smuzhiyun 0x184 0x0 /* SPI1_CLK/SPI1_DI (IOMG98) */ 202*4882a593Smuzhiyun 0x0e8 0x0 /* SPI1_DO (IOMG58) */ 203*4882a593Smuzhiyun 0x0ec 0x0 /* SPI1_CS (IOMG95) */ 204*4882a593Smuzhiyun >; 205*4882a593Smuzhiyun }; 206*4882a593Smuzhiyun spi1_pmx_idle: spi1_pmx_idle { 207*4882a593Smuzhiyun pinctrl-single,pins = < 208*4882a593Smuzhiyun 0x184 0x1 /* GPIO (IOMG98) */ 209*4882a593Smuzhiyun 0x0e8 0x1 /* GPIO (IOMG58) */ 210*4882a593Smuzhiyun 0x0ec 0x1 /* GPIO (IOMG95) */ 211*4882a593Smuzhiyun >; 212*4882a593Smuzhiyun }; 213*4882a593Smuzhiyun kpc_pmx_func: kpc_pmx_func { 214*4882a593Smuzhiyun pinctrl-single,pins = < 215*4882a593Smuzhiyun 0x12c 0x0 /* KEY_IN0 (IOMG73) */ 216*4882a593Smuzhiyun 0x130 0x0 /* KEY_IN1 (IOMG74) */ 217*4882a593Smuzhiyun 0x134 0x0 /* KEY_IN2 (IOMG75) */ 218*4882a593Smuzhiyun 0x10c 0x0 /* KEY_OUT0 (IOMG65) */ 219*4882a593Smuzhiyun 0x110 0x0 /* KEY_OUT1 (IOMG66) */ 220*4882a593Smuzhiyun 0x114 0x0 /* KEY_OUT2 (IOMG67) */ 221*4882a593Smuzhiyun >; 222*4882a593Smuzhiyun }; 223*4882a593Smuzhiyun kpc_pmx_idle: kpc_pmx_idle { 224*4882a593Smuzhiyun pinctrl-single,pins = < 225*4882a593Smuzhiyun 0x12c 0x1 /* GPIO (IOMG73) */ 226*4882a593Smuzhiyun 0x130 0x1 /* GPIO (IOMG74) */ 227*4882a593Smuzhiyun 0x134 0x1 /* GPIO (IOMG75) */ 228*4882a593Smuzhiyun 0x10c 0x1 /* GPIO (IOMG65) */ 229*4882a593Smuzhiyun 0x110 0x1 /* GPIO (IOMG66) */ 230*4882a593Smuzhiyun 0x114 0x1 /* GPIO (IOMG67) */ 231*4882a593Smuzhiyun >; 232*4882a593Smuzhiyun }; 233*4882a593Smuzhiyun gpio_key_func: gpio_key_func { 234*4882a593Smuzhiyun pinctrl-single,pins = < 235*4882a593Smuzhiyun 0x10c 0x1 /* KEY_OUT0/GPIO (IOMG65) */ 236*4882a593Smuzhiyun 0x130 0x1 /* KEY_IN1/GPIO (IOMG74) */ 237*4882a593Smuzhiyun >; 238*4882a593Smuzhiyun }; 239*4882a593Smuzhiyun emmc_pmx_func: emmc_pmx_func { 240*4882a593Smuzhiyun pinctrl-single,pins = < 241*4882a593Smuzhiyun 0x030 0x2 /* eMMC_CMD/eMMC_CLK (IOMG12) */ 242*4882a593Smuzhiyun 0x018 0x0 /* NAND_CS3_N (IOMG6) */ 243*4882a593Smuzhiyun 0x024 0x0 /* NAND_BUSY2_N (IOMG8) */ 244*4882a593Smuzhiyun 0x028 0x0 /* NAND_BUSY3_N (IOMG9) */ 245*4882a593Smuzhiyun 0x02c 0x2 /* eMMC_DATA[0:7] (IOMG10) */ 246*4882a593Smuzhiyun >; 247*4882a593Smuzhiyun }; 248*4882a593Smuzhiyun emmc_pmx_idle: emmc_pmx_idle { 249*4882a593Smuzhiyun pinctrl-single,pins = < 250*4882a593Smuzhiyun 0x030 0x0 /* GPIO (IOMG12) */ 251*4882a593Smuzhiyun 0x018 0x1 /* GPIO (IOMG6) */ 252*4882a593Smuzhiyun 0x024 0x1 /* GPIO (IOMG8) */ 253*4882a593Smuzhiyun 0x028 0x1 /* GPIO (IOMG9) */ 254*4882a593Smuzhiyun 0x02c 0x1 /* GPIO (IOMG10) */ 255*4882a593Smuzhiyun >; 256*4882a593Smuzhiyun }; 257*4882a593Smuzhiyun sd_pmx_func: sd_pmx_func { 258*4882a593Smuzhiyun pinctrl-single,pins = < 259*4882a593Smuzhiyun 0x0bc 0x0 /* SD_CLK/SD_CMD/SD_DATA0/SD_DATA1/SD_DATA2 (IOMG47) */ 260*4882a593Smuzhiyun 0x0c0 0x0 /* SD_DATA3 (IOMG48) */ 261*4882a593Smuzhiyun >; 262*4882a593Smuzhiyun }; 263*4882a593Smuzhiyun sd_pmx_idle: sd_pmx_idle { 264*4882a593Smuzhiyun pinctrl-single,pins = < 265*4882a593Smuzhiyun 0x0bc 0x1 /* GPIO (IOMG47) */ 266*4882a593Smuzhiyun 0x0c0 0x1 /* GPIO (IOMG48) */ 267*4882a593Smuzhiyun >; 268*4882a593Smuzhiyun }; 269*4882a593Smuzhiyun nand_pmx_func: nand_pmx_func { 270*4882a593Smuzhiyun pinctrl-single,pins = < 271*4882a593Smuzhiyun 0x00c 0x0 /* NAND_ALE/NAND_CLE/.../NAND_DATA[0:7] (IOMG3) */ 272*4882a593Smuzhiyun 0x010 0x0 /* NAND_CS1_N (IOMG4) */ 273*4882a593Smuzhiyun 0x014 0x0 /* NAND_CS2_N (IOMG5) */ 274*4882a593Smuzhiyun 0x018 0x0 /* NAND_CS3_N (IOMG6) */ 275*4882a593Smuzhiyun 0x01c 0x0 /* NAND_BUSY0_N (IOMG94) */ 276*4882a593Smuzhiyun 0x020 0x0 /* NAND_BUSY1_N (IOMG7) */ 277*4882a593Smuzhiyun 0x024 0x0 /* NAND_BUSY2_N (IOMG8) */ 278*4882a593Smuzhiyun 0x028 0x0 /* NAND_BUSY3_N (IOMG9) */ 279*4882a593Smuzhiyun 0x02c 0x0 /* NAND_DATA[8:15] (IOMG10) */ 280*4882a593Smuzhiyun >; 281*4882a593Smuzhiyun }; 282*4882a593Smuzhiyun nand_pmx_idle: nand_pmx_idle { 283*4882a593Smuzhiyun pinctrl-single,pins = < 284*4882a593Smuzhiyun 0x00c 0x1 /* GPIO (IOMG3) */ 285*4882a593Smuzhiyun 0x010 0x1 /* GPIO (IOMG4) */ 286*4882a593Smuzhiyun 0x014 0x1 /* GPIO (IOMG5) */ 287*4882a593Smuzhiyun 0x018 0x1 /* GPIO (IOMG6) */ 288*4882a593Smuzhiyun 0x01c 0x1 /* GPIO (IOMG94) */ 289*4882a593Smuzhiyun 0x020 0x1 /* GPIO (IOMG7) */ 290*4882a593Smuzhiyun 0x024 0x1 /* GPIO (IOMG8) */ 291*4882a593Smuzhiyun 0x028 0x1 /* GPIO (IOMG9) */ 292*4882a593Smuzhiyun 0x02c 0x1 /* GPIO (IOMG10) */ 293*4882a593Smuzhiyun >; 294*4882a593Smuzhiyun }; 295*4882a593Smuzhiyun sdio_pmx_func: sdio_pmx_func { 296*4882a593Smuzhiyun pinctrl-single,pins = < 297*4882a593Smuzhiyun 0x0c4 0x0 /* SDIO_CLK/SDIO_CMD/SDIO_DATA[0:3] (IOMG49) */ 298*4882a593Smuzhiyun >; 299*4882a593Smuzhiyun }; 300*4882a593Smuzhiyun sdio_pmx_idle: sdio_pmx_idle { 301*4882a593Smuzhiyun pinctrl-single,pins = < 302*4882a593Smuzhiyun 0x0c4 0x1 /* GPIO (IOMG49) */ 303*4882a593Smuzhiyun >; 304*4882a593Smuzhiyun }; 305*4882a593Smuzhiyun audio_out_pmx_func: audio_out_pmx_func { 306*4882a593Smuzhiyun pinctrl-single,pins = < 307*4882a593Smuzhiyun 0x0f0 0x1 /* GPIO (IOMG59), audio spk & earphone */ 308*4882a593Smuzhiyun >; 309*4882a593Smuzhiyun }; 310*4882a593Smuzhiyun }; 311*4882a593Smuzhiyun 312*4882a593Smuzhiyun pmx1: pinmux@803800 { 313*4882a593Smuzhiyun pinctrl-names = "default"; 314*4882a593Smuzhiyun pinctrl-0 = < &board_pu_pins &board_pd_pins &board_pd_ps_pins 315*4882a593Smuzhiyun &board_np_pins &board_ps_pins &kpc_cfg_func 316*4882a593Smuzhiyun &audio_out_cfg_func>; 317*4882a593Smuzhiyun board_pu_pins: board_pu_pins { 318*4882a593Smuzhiyun pinctrl-single,pins = < 319*4882a593Smuzhiyun 0x014 0 /* GPIO_158 (IOCFG2) */ 320*4882a593Smuzhiyun 0x018 0 /* GPIO_159 (IOCFG3) */ 321*4882a593Smuzhiyun 0x01c 0 /* BOOT_MODE0 (IOCFG4) */ 322*4882a593Smuzhiyun 0x020 0 /* BOOT_MODE1 (IOCFG5) */ 323*4882a593Smuzhiyun >; 324*4882a593Smuzhiyun pinctrl-single,bias-pulldown = <0 2 0 2>; 325*4882a593Smuzhiyun pinctrl-single,bias-pullup = <1 1 0 1>; 326*4882a593Smuzhiyun }; 327*4882a593Smuzhiyun board_pd_pins: board_pd_pins { 328*4882a593Smuzhiyun pinctrl-single,pins = < 329*4882a593Smuzhiyun 0x038 0 /* eFUSE_DOUT (IOCFG11) */ 330*4882a593Smuzhiyun 0x150 0 /* ISP_GPIO8 (IOCFG93) */ 331*4882a593Smuzhiyun 0x154 0 /* ISP_GPIO9 (IOCFG94) */ 332*4882a593Smuzhiyun >; 333*4882a593Smuzhiyun pinctrl-single,bias-pulldown = <2 2 0 2>; 334*4882a593Smuzhiyun pinctrl-single,bias-pullup = <0 1 0 1>; 335*4882a593Smuzhiyun }; 336*4882a593Smuzhiyun board_pd_ps_pins: board_pd_ps_pins { 337*4882a593Smuzhiyun pinctrl-single,pins = < 338*4882a593Smuzhiyun 0x2d8 0 /* CLK_OUT0 (IOCFG190) */ 339*4882a593Smuzhiyun 0x004 0 /* PMU_SPI_DATA (IOCFG192) */ 340*4882a593Smuzhiyun >; 341*4882a593Smuzhiyun pinctrl-single,bias-pulldown = <2 2 0 2>; 342*4882a593Smuzhiyun pinctrl-single,bias-pullup = <0 1 0 1>; 343*4882a593Smuzhiyun pinctrl-single,drive-strength = <0x30 0xf0>; 344*4882a593Smuzhiyun }; 345*4882a593Smuzhiyun board_np_pins: board_np_pins { 346*4882a593Smuzhiyun pinctrl-single,pins = < 347*4882a593Smuzhiyun 0x24c 0 /* KEYPAD_OUT7 (IOCFG155) */ 348*4882a593Smuzhiyun >; 349*4882a593Smuzhiyun pinctrl-single,bias-pulldown = <0 2 0 2>; 350*4882a593Smuzhiyun pinctrl-single,bias-pullup = <0 1 0 1>; 351*4882a593Smuzhiyun }; 352*4882a593Smuzhiyun board_ps_pins: board_ps_pins { 353*4882a593Smuzhiyun pinctrl-single,pins = < 354*4882a593Smuzhiyun 0x000 0 /* PMU_SPI_CLK (IOCFG191) */ 355*4882a593Smuzhiyun 0x008 0 /* PMU_SPI_CS_N (IOCFG193) */ 356*4882a593Smuzhiyun >; 357*4882a593Smuzhiyun pinctrl-single,drive-strength = <0x30 0xf0>; 358*4882a593Smuzhiyun }; 359*4882a593Smuzhiyun uart0_cfg_func: uart0_cfg_func { 360*4882a593Smuzhiyun pinctrl-single,pins = < 361*4882a593Smuzhiyun 0x208 0 /* UART0_RXD (IOCFG138) */ 362*4882a593Smuzhiyun 0x20c 0 /* UART0_TXD (IOCFG139) */ 363*4882a593Smuzhiyun >; 364*4882a593Smuzhiyun pinctrl-single,bias-pulldown = <0 2 0 2>; 365*4882a593Smuzhiyun pinctrl-single,bias-pullup = <0 1 0 1>; 366*4882a593Smuzhiyun }; 367*4882a593Smuzhiyun uart0_cfg_idle: uart0_cfg_idle { 368*4882a593Smuzhiyun pinctrl-single,pins = < 369*4882a593Smuzhiyun 0x208 0 /* UART0_RXD (IOCFG138) */ 370*4882a593Smuzhiyun 0x20c 0 /* UART0_TXD (IOCFG139) */ 371*4882a593Smuzhiyun >; 372*4882a593Smuzhiyun pinctrl-single,bias-pulldown = <2 2 0 2>; 373*4882a593Smuzhiyun pinctrl-single,bias-pullup = <0 1 0 1>; 374*4882a593Smuzhiyun }; 375*4882a593Smuzhiyun uart1_cfg_func: uart1_cfg_func { 376*4882a593Smuzhiyun pinctrl-single,pins = < 377*4882a593Smuzhiyun 0x210 0 /* UART1_CTS (IOCFG140) */ 378*4882a593Smuzhiyun 0x214 0 /* UART1_RTS (IOCFG141) */ 379*4882a593Smuzhiyun 0x218 0 /* UART1_RXD (IOCFG142) */ 380*4882a593Smuzhiyun 0x21c 0 /* UART1_TXD (IOCFG143) */ 381*4882a593Smuzhiyun >; 382*4882a593Smuzhiyun pinctrl-single,bias-pulldown = <0 2 0 2>; 383*4882a593Smuzhiyun pinctrl-single,bias-pullup = <0 1 0 1>; 384*4882a593Smuzhiyun }; 385*4882a593Smuzhiyun uart1_cfg_idle: uart1_cfg_idle { 386*4882a593Smuzhiyun pinctrl-single,pins = < 387*4882a593Smuzhiyun 0x210 0 /* UART1_CTS (IOCFG140) */ 388*4882a593Smuzhiyun 0x214 0 /* UART1_RTS (IOCFG141) */ 389*4882a593Smuzhiyun 0x218 0 /* UART1_RXD (IOCFG142) */ 390*4882a593Smuzhiyun 0x21c 0 /* UART1_TXD (IOCFG143) */ 391*4882a593Smuzhiyun >; 392*4882a593Smuzhiyun pinctrl-single,bias-pulldown = <2 2 0 2>; 393*4882a593Smuzhiyun pinctrl-single,bias-pullup = <0 1 0 1>; 394*4882a593Smuzhiyun }; 395*4882a593Smuzhiyun uart2_cfg_func: uart2_cfg_func { 396*4882a593Smuzhiyun pinctrl-single,pins = < 397*4882a593Smuzhiyun 0x220 0 /* UART2_CTS (IOCFG144) */ 398*4882a593Smuzhiyun 0x224 0 /* UART2_RTS (IOCFG145) */ 399*4882a593Smuzhiyun 0x228 0 /* UART2_RXD (IOCFG146) */ 400*4882a593Smuzhiyun 0x22c 0 /* UART2_TXD (IOCFG147) */ 401*4882a593Smuzhiyun >; 402*4882a593Smuzhiyun pinctrl-single,bias-pulldown = <0 2 0 2>; 403*4882a593Smuzhiyun pinctrl-single,bias-pullup = <0 1 0 1>; 404*4882a593Smuzhiyun }; 405*4882a593Smuzhiyun uart2_cfg_idle: uart2_cfg_idle { 406*4882a593Smuzhiyun pinctrl-single,pins = < 407*4882a593Smuzhiyun 0x220 0 /* GPIO (IOCFG144) */ 408*4882a593Smuzhiyun 0x224 0 /* GPIO (IOCFG145) */ 409*4882a593Smuzhiyun 0x228 0 /* GPIO (IOCFG146) */ 410*4882a593Smuzhiyun 0x22c 0 /* GPIO (IOCFG147) */ 411*4882a593Smuzhiyun >; 412*4882a593Smuzhiyun pinctrl-single,bias-pulldown = <2 2 0 2>; 413*4882a593Smuzhiyun pinctrl-single,bias-pullup = <0 1 0 1>; 414*4882a593Smuzhiyun }; 415*4882a593Smuzhiyun uart3_cfg_func: uart3_cfg_func { 416*4882a593Smuzhiyun pinctrl-single,pins = < 417*4882a593Smuzhiyun 0x294 0 /* UART3_CTS (IOCFG173) */ 418*4882a593Smuzhiyun 0x298 0 /* UART3_RTS (IOCFG174) */ 419*4882a593Smuzhiyun 0x29c 0 /* UART3_RXD (IOCFG175) */ 420*4882a593Smuzhiyun 0x2a0 0 /* UART3_TXD (IOCFG176) */ 421*4882a593Smuzhiyun >; 422*4882a593Smuzhiyun pinctrl-single,bias-pulldown = <0 2 0 2>; 423*4882a593Smuzhiyun pinctrl-single,bias-pullup = <0 1 0 1>; 424*4882a593Smuzhiyun }; 425*4882a593Smuzhiyun uart3_cfg_idle: uart3_cfg_idle { 426*4882a593Smuzhiyun pinctrl-single,pins = < 427*4882a593Smuzhiyun 0x294 0 /* UART3_CTS (IOCFG173) */ 428*4882a593Smuzhiyun 0x298 0 /* UART3_RTS (IOCFG174) */ 429*4882a593Smuzhiyun 0x29c 0 /* UART3_RXD (IOCFG175) */ 430*4882a593Smuzhiyun 0x2a0 0 /* UART3_TXD (IOCFG176) */ 431*4882a593Smuzhiyun >; 432*4882a593Smuzhiyun pinctrl-single,bias-pulldown = <2 2 0 2>; 433*4882a593Smuzhiyun pinctrl-single,bias-pullup = <0 1 0 1>; 434*4882a593Smuzhiyun }; 435*4882a593Smuzhiyun uart4_cfg_func: uart4_cfg_func { 436*4882a593Smuzhiyun pinctrl-single,pins = < 437*4882a593Smuzhiyun 0x2a4 0 /* UART4_CTS (IOCFG177) */ 438*4882a593Smuzhiyun 0x2a8 0 /* UART4_RTS (IOCFG178) */ 439*4882a593Smuzhiyun 0x2ac 0 /* UART4_RXD (IOCFG179) */ 440*4882a593Smuzhiyun 0x2b0 0 /* UART4_TXD (IOCFG180) */ 441*4882a593Smuzhiyun >; 442*4882a593Smuzhiyun pinctrl-single,bias-pulldown = <0 2 0 2>; 443*4882a593Smuzhiyun pinctrl-single,bias-pullup = <0 1 0 1>; 444*4882a593Smuzhiyun }; 445*4882a593Smuzhiyun i2c0_cfg_func: i2c0_cfg_func { 446*4882a593Smuzhiyun pinctrl-single,pins = < 447*4882a593Smuzhiyun 0x17c 0 /* I2C0_SCL (IOCFG103) */ 448*4882a593Smuzhiyun 0x180 0 /* I2C0_SDA (IOCFG104) */ 449*4882a593Smuzhiyun >; 450*4882a593Smuzhiyun pinctrl-single,bias-pulldown = <0 2 0 2>; 451*4882a593Smuzhiyun pinctrl-single,bias-pullup = <0 1 0 1>; 452*4882a593Smuzhiyun pinctrl-single,drive-strength = <0x30 0xf0>; 453*4882a593Smuzhiyun }; 454*4882a593Smuzhiyun i2c1_cfg_func: i2c1_cfg_func { 455*4882a593Smuzhiyun pinctrl-single,pins = < 456*4882a593Smuzhiyun 0x184 0 /* I2C1_SCL (IOCFG105) */ 457*4882a593Smuzhiyun 0x188 0 /* I2C1_SDA (IOCFG106) */ 458*4882a593Smuzhiyun >; 459*4882a593Smuzhiyun pinctrl-single,bias-pulldown = <0 2 0 2>; 460*4882a593Smuzhiyun pinctrl-single,bias-pullup = <0 1 0 1>; 461*4882a593Smuzhiyun pinctrl-single,drive-strength = <0x30 0xf0>; 462*4882a593Smuzhiyun }; 463*4882a593Smuzhiyun i2c2_cfg_func: i2c2_cfg_func { 464*4882a593Smuzhiyun pinctrl-single,pins = < 465*4882a593Smuzhiyun 0x118 0 /* I2C2_SCL (IOCFG79) */ 466*4882a593Smuzhiyun 0x11c 0 /* I2C2_SDA (IOCFG80) */ 467*4882a593Smuzhiyun >; 468*4882a593Smuzhiyun pinctrl-single,bias-pulldown = <0 2 0 2>; 469*4882a593Smuzhiyun pinctrl-single,bias-pullup = <0 1 0 1>; 470*4882a593Smuzhiyun pinctrl-single,drive-strength = <0x30 0xf0>; 471*4882a593Smuzhiyun }; 472*4882a593Smuzhiyun i2c3_cfg_func: i2c3_cfg_func { 473*4882a593Smuzhiyun pinctrl-single,pins = < 474*4882a593Smuzhiyun 0x100 0 /* I2C3_SCL (IOCFG73) */ 475*4882a593Smuzhiyun 0x104 0 /* I2C3_SDA (IOCFG74) */ 476*4882a593Smuzhiyun >; 477*4882a593Smuzhiyun pinctrl-single,bias-pulldown = <0 2 0 2>; 478*4882a593Smuzhiyun pinctrl-single,bias-pullup = <0 1 0 1>; 479*4882a593Smuzhiyun pinctrl-single,drive-strength = <0x30 0xf0>; 480*4882a593Smuzhiyun }; 481*4882a593Smuzhiyun spi0_cfg_func1: spi0_cfg_func1 { 482*4882a593Smuzhiyun pinctrl-single,pins = < 483*4882a593Smuzhiyun 0x1d4 0 /* SPI0_CLK (IOCFG125) */ 484*4882a593Smuzhiyun 0x1d8 0 /* SPI0_DI (IOCFG126) */ 485*4882a593Smuzhiyun 0x1dc 0 /* SPI0_DO (IOCFG127) */ 486*4882a593Smuzhiyun >; 487*4882a593Smuzhiyun pinctrl-single,bias-pulldown = <2 2 0 2>; 488*4882a593Smuzhiyun pinctrl-single,bias-pullup = <0 1 0 1>; 489*4882a593Smuzhiyun pinctrl-single,drive-strength = <0x30 0xf0>; 490*4882a593Smuzhiyun }; 491*4882a593Smuzhiyun spi0_cfg_func2: spi0_cfg_func2 { 492*4882a593Smuzhiyun pinctrl-single,pins = < 493*4882a593Smuzhiyun 0x1e0 0 /* SPI0_CS0 (IOCFG128) */ 494*4882a593Smuzhiyun 0x1e4 0 /* SPI0_CS1 (IOCFG129) */ 495*4882a593Smuzhiyun 0x1e8 0 /* SPI0_CS2 (IOCFG130 */ 496*4882a593Smuzhiyun 0x1ec 0 /* SPI0_CS3 (IOCFG131) */ 497*4882a593Smuzhiyun >; 498*4882a593Smuzhiyun pinctrl-single,bias-pulldown = <0 2 0 2>; 499*4882a593Smuzhiyun pinctrl-single,bias-pullup = <1 1 0 1>; 500*4882a593Smuzhiyun pinctrl-single,drive-strength = <0x30 0xf0>; 501*4882a593Smuzhiyun }; 502*4882a593Smuzhiyun spi1_cfg_func1: spi1_cfg_func1 { 503*4882a593Smuzhiyun pinctrl-single,pins = < 504*4882a593Smuzhiyun 0x1f0 0 /* SPI1_CLK (IOCFG132) */ 505*4882a593Smuzhiyun 0x1f4 0 /* SPI1_DI (IOCFG133) */ 506*4882a593Smuzhiyun 0x1f8 0 /* SPI1_DO (IOCFG134) */ 507*4882a593Smuzhiyun >; 508*4882a593Smuzhiyun pinctrl-single,bias-pulldown = <2 2 0 2>; 509*4882a593Smuzhiyun pinctrl-single,bias-pullup = <0 1 0 1>; 510*4882a593Smuzhiyun pinctrl-single,drive-strength = <0x30 0xf0>; 511*4882a593Smuzhiyun }; 512*4882a593Smuzhiyun spi1_cfg_func2: spi1_cfg_func2 { 513*4882a593Smuzhiyun pinctrl-single,pins = < 514*4882a593Smuzhiyun 0x1fc 0 /* SPI1_CS (IOCFG135) */ 515*4882a593Smuzhiyun >; 516*4882a593Smuzhiyun pinctrl-single,bias-pulldown = <0 2 0 2>; 517*4882a593Smuzhiyun pinctrl-single,bias-pullup = <1 1 0 1>; 518*4882a593Smuzhiyun pinctrl-single,drive-strength = <0x30 0xf0>; 519*4882a593Smuzhiyun }; 520*4882a593Smuzhiyun kpc_cfg_func: kpc_cfg_func { 521*4882a593Smuzhiyun pinctrl-single,pins = < 522*4882a593Smuzhiyun 0x250 0 /* KEY_IN0 (IOCFG156) */ 523*4882a593Smuzhiyun 0x254 0 /* KEY_IN1 (IOCFG157) */ 524*4882a593Smuzhiyun 0x258 0 /* KEY_IN2 (IOCFG158) */ 525*4882a593Smuzhiyun 0x230 0 /* KEY_OUT0 (IOCFG148) */ 526*4882a593Smuzhiyun 0x234 0 /* KEY_OUT1 (IOCFG149) */ 527*4882a593Smuzhiyun 0x238 0 /* KEY_OUT2 (IOCFG150) */ 528*4882a593Smuzhiyun >; 529*4882a593Smuzhiyun pinctrl-single,bias-pulldown = <2 2 0 2>; 530*4882a593Smuzhiyun pinctrl-single,bias-pullup = <0 1 0 1>; 531*4882a593Smuzhiyun }; 532*4882a593Smuzhiyun emmc_cfg_func: emmc_cfg_func { 533*4882a593Smuzhiyun pinctrl-single,pins = < 534*4882a593Smuzhiyun 0x0ac 0 /* eMMC_CMD (IOCFG40) */ 535*4882a593Smuzhiyun 0x0b0 0 /* eMMC_CLK (IOCFG41) */ 536*4882a593Smuzhiyun 0x058 0 /* NAND_CS3_N (IOCFG19) */ 537*4882a593Smuzhiyun 0x064 0 /* NAND_BUSY2_N (IOCFG22) */ 538*4882a593Smuzhiyun 0x068 0 /* NAND_BUSY3_N (IOCFG23) */ 539*4882a593Smuzhiyun 0x08c 0 /* NAND_DATA8 (IOCFG32) */ 540*4882a593Smuzhiyun 0x090 0 /* NAND_DATA9 (IOCFG33) */ 541*4882a593Smuzhiyun 0x094 0 /* NAND_DATA10 (IOCFG34) */ 542*4882a593Smuzhiyun 0x098 0 /* NAND_DATA11 (IOCFG35) */ 543*4882a593Smuzhiyun 0x09c 0 /* NAND_DATA12 (IOCFG36) */ 544*4882a593Smuzhiyun 0x0a0 0 /* NAND_DATA13 (IOCFG37) */ 545*4882a593Smuzhiyun 0x0a4 0 /* NAND_DATA14 (IOCFG38) */ 546*4882a593Smuzhiyun 0x0a8 0 /* NAND_DATA15 (IOCFG39) */ 547*4882a593Smuzhiyun >; 548*4882a593Smuzhiyun pinctrl-single,bias-pulldown = <0 2 0 2>; 549*4882a593Smuzhiyun pinctrl-single,bias-pullup = <1 1 0 1>; 550*4882a593Smuzhiyun pinctrl-single,drive-strength = <0x30 0xf0>; 551*4882a593Smuzhiyun }; 552*4882a593Smuzhiyun sd_cfg_func1: sd_cfg_func1 { 553*4882a593Smuzhiyun pinctrl-single,pins = < 554*4882a593Smuzhiyun 0x18c 0 /* SD_CLK (IOCFG107) */ 555*4882a593Smuzhiyun 0x190 0 /* SD_CMD (IOCFG108) */ 556*4882a593Smuzhiyun >; 557*4882a593Smuzhiyun pinctrl-single,bias-pulldown = <2 2 0 2>; 558*4882a593Smuzhiyun pinctrl-single,bias-pullup = <0 1 0 1>; 559*4882a593Smuzhiyun pinctrl-single,drive-strength = <0x30 0xf0>; 560*4882a593Smuzhiyun }; 561*4882a593Smuzhiyun sd_cfg_func2: sd_cfg_func2 { 562*4882a593Smuzhiyun pinctrl-single,pins = < 563*4882a593Smuzhiyun 0x194 0 /* SD_DATA0 (IOCFG109) */ 564*4882a593Smuzhiyun 0x198 0 /* SD_DATA1 (IOCFG110) */ 565*4882a593Smuzhiyun 0x19c 0 /* SD_DATA2 (IOCFG111) */ 566*4882a593Smuzhiyun 0x1a0 0 /* SD_DATA3 (IOCFG112) */ 567*4882a593Smuzhiyun >; 568*4882a593Smuzhiyun pinctrl-single,bias-pulldown = <2 2 0 2>; 569*4882a593Smuzhiyun pinctrl-single,bias-pullup = <0 1 0 1>; 570*4882a593Smuzhiyun pinctrl-single,drive-strength = <0x70 0xf0>; 571*4882a593Smuzhiyun }; 572*4882a593Smuzhiyun nand_cfg_func1: nand_cfg_func1 { 573*4882a593Smuzhiyun pinctrl-single,pins = < 574*4882a593Smuzhiyun 0x03c 0 /* NAND_ALE (IOCFG12) */ 575*4882a593Smuzhiyun 0x040 0 /* NAND_CLE (IOCFG13) */ 576*4882a593Smuzhiyun 0x06c 0 /* NAND_DATA0 (IOCFG24) */ 577*4882a593Smuzhiyun 0x070 0 /* NAND_DATA1 (IOCFG25) */ 578*4882a593Smuzhiyun 0x074 0 /* NAND_DATA2 (IOCFG26) */ 579*4882a593Smuzhiyun 0x078 0 /* NAND_DATA3 (IOCFG27) */ 580*4882a593Smuzhiyun 0x07c 0 /* NAND_DATA4 (IOCFG28) */ 581*4882a593Smuzhiyun 0x080 0 /* NAND_DATA5 (IOCFG29) */ 582*4882a593Smuzhiyun 0x084 0 /* NAND_DATA6 (IOCFG30) */ 583*4882a593Smuzhiyun 0x088 0 /* NAND_DATA7 (IOCFG31) */ 584*4882a593Smuzhiyun 0x08c 0 /* NAND_DATA8 (IOCFG32) */ 585*4882a593Smuzhiyun 0x090 0 /* NAND_DATA9 (IOCFG33) */ 586*4882a593Smuzhiyun 0x094 0 /* NAND_DATA10 (IOCFG34) */ 587*4882a593Smuzhiyun 0x098 0 /* NAND_DATA11 (IOCFG35) */ 588*4882a593Smuzhiyun 0x09c 0 /* NAND_DATA12 (IOCFG36) */ 589*4882a593Smuzhiyun 0x0a0 0 /* NAND_DATA13 (IOCFG37) */ 590*4882a593Smuzhiyun 0x0a4 0 /* NAND_DATA14 (IOCFG38) */ 591*4882a593Smuzhiyun 0x0a8 0 /* NAND_DATA15 (IOCFG39) */ 592*4882a593Smuzhiyun >; 593*4882a593Smuzhiyun pinctrl-single,bias-pulldown = <2 2 0 2>; 594*4882a593Smuzhiyun pinctrl-single,bias-pullup = <0 1 0 1>; 595*4882a593Smuzhiyun pinctrl-single,drive-strength = <0x30 0xf0>; 596*4882a593Smuzhiyun }; 597*4882a593Smuzhiyun nand_cfg_func2: nand_cfg_func2 { 598*4882a593Smuzhiyun pinctrl-single,pins = < 599*4882a593Smuzhiyun 0x044 0 /* NAND_RE_N (IOCFG14) */ 600*4882a593Smuzhiyun 0x048 0 /* NAND_WE_N (IOCFG15) */ 601*4882a593Smuzhiyun 0x04c 0 /* NAND_CS0_N (IOCFG16) */ 602*4882a593Smuzhiyun 0x050 0 /* NAND_CS1_N (IOCFG17) */ 603*4882a593Smuzhiyun 0x054 0 /* NAND_CS2_N (IOCFG18) */ 604*4882a593Smuzhiyun 0x058 0 /* NAND_CS3_N (IOCFG19) */ 605*4882a593Smuzhiyun 0x05c 0 /* NAND_BUSY0_N (IOCFG20) */ 606*4882a593Smuzhiyun 0x060 0 /* NAND_BUSY1_N (IOCFG21) */ 607*4882a593Smuzhiyun 0x064 0 /* NAND_BUSY2_N (IOCFG22) */ 608*4882a593Smuzhiyun 0x068 0 /* NAND_BUSY3_N (IOCFG23) */ 609*4882a593Smuzhiyun >; 610*4882a593Smuzhiyun pinctrl-single,bias-pulldown = <0 2 0 2>; 611*4882a593Smuzhiyun pinctrl-single,bias-pullup = <1 1 0 1>; 612*4882a593Smuzhiyun pinctrl-single,drive-strength = <0x30 0xf0>; 613*4882a593Smuzhiyun }; 614*4882a593Smuzhiyun sdio_cfg_func: sdio_cfg_func { 615*4882a593Smuzhiyun pinctrl-single,pins = < 616*4882a593Smuzhiyun 0x1a4 0 /* SDIO0_CLK (IOCG113) */ 617*4882a593Smuzhiyun 0x1a8 0 /* SDIO0_CMD (IOCG114) */ 618*4882a593Smuzhiyun 0x1ac 0 /* SDIO0_DATA0 (IOCG115) */ 619*4882a593Smuzhiyun 0x1b0 0 /* SDIO0_DATA1 (IOCG116) */ 620*4882a593Smuzhiyun 0x1b4 0 /* SDIO0_DATA2 (IOCG117) */ 621*4882a593Smuzhiyun 0x1b8 0 /* SDIO0_DATA3 (IOCG118) */ 622*4882a593Smuzhiyun >; 623*4882a593Smuzhiyun pinctrl-single,bias-pulldown = <2 2 0 2>; 624*4882a593Smuzhiyun pinctrl-single,bias-pullup = <0 1 0 1>; 625*4882a593Smuzhiyun pinctrl-single,drive-strength = <0x30 0xf0>; 626*4882a593Smuzhiyun }; 627*4882a593Smuzhiyun audio_out_cfg_func: audio_out_cfg_func { 628*4882a593Smuzhiyun pinctrl-single,pins = < 629*4882a593Smuzhiyun 0x200 0 /* GPIO (IOCFG136) */ 630*4882a593Smuzhiyun 0x204 0 /* GPIO (IOCFG137) */ 631*4882a593Smuzhiyun >; 632*4882a593Smuzhiyun pinctrl-single,bias-pulldown = <2 2 0 2>; 633*4882a593Smuzhiyun pinctrl-single,bias-pullup = <0 1 0 1>; 634*4882a593Smuzhiyun }; 635*4882a593Smuzhiyun }; 636*4882a593Smuzhiyun }; 637*4882a593Smuzhiyun 638*4882a593Smuzhiyun gpio-keys { 639*4882a593Smuzhiyun compatible = "gpio-keys"; 640*4882a593Smuzhiyun 641*4882a593Smuzhiyun call { 642*4882a593Smuzhiyun label = "call"; 643*4882a593Smuzhiyun gpios = <&gpio17 2 0>; 644*4882a593Smuzhiyun linux,code = <169>; /* KEY_PHONE */ 645*4882a593Smuzhiyun }; 646*4882a593Smuzhiyun }; 647*4882a593Smuzhiyun}; 648