1*4882a593Smuzhiyun// SPDX-License-Identifier: GPL-2.0 2*4882a593Smuzhiyun// Copyright (c) 2018 Texas Instruments 3*4882a593Smuzhiyun// MMC IOdelay values for TI's DRA76x and AM576x SoCs. 4*4882a593Smuzhiyun// Author: Sekhar Nori <nsekhar@ti.com> 5*4882a593Smuzhiyun 6*4882a593Smuzhiyun/* 7*4882a593Smuzhiyun * Rules for modifying this file: 8*4882a593Smuzhiyun * a) Update of this file should typically correspond to a datamanual revision. 9*4882a593Smuzhiyun * Datamanual revision that was used should be updated in comment below. 10*4882a593Smuzhiyun * If there is no update to datamanual, do not update the values. If you 11*4882a593Smuzhiyun * need to use values different from that recommended by the datamanual 12*4882a593Smuzhiyun * for your design, then you should consider adding values to the device- 13*4882a593Smuzhiyun * -tree file for your board directly. 14*4882a593Smuzhiyun * b) We keep the mode names as close to the datamanual as possible. So 15*4882a593Smuzhiyun * if the manual calls a mode, DDR50, or DDR or DDR 1.8v or DDR 3.3v, 16*4882a593Smuzhiyun * we follow that in code too. 17*4882a593Smuzhiyun * c) If the values change between multiple revisions of silicon, we add 18*4882a593Smuzhiyun * a revision tag to both the new and old entry. Use 'rev11' for PG 1.1, 19*4882a593Smuzhiyun * 'rev20' for PG 2.0 and so on. 20*4882a593Smuzhiyun * d) The node name and node label should be the exact same string. This is 21*4882a593Smuzhiyun * to curb naming creativity and achieve consistency. 22*4882a593Smuzhiyun * 23*4882a593Smuzhiyun * Datamanual Revisions: 24*4882a593Smuzhiyun * 25*4882a593Smuzhiyun * DRA76x Silicon Revision 1.0: SPRS993E, Revised December 2018 26*4882a593Smuzhiyun * 27*4882a593Smuzhiyun */ 28*4882a593Smuzhiyun 29*4882a593Smuzhiyun&dra7_pmx_core { 30*4882a593Smuzhiyun mmc1_pins_default: mmc1_pins_default { 31*4882a593Smuzhiyun pinctrl-single,pins = < 32*4882a593Smuzhiyun DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_clk.clk */ 33*4882a593Smuzhiyun DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_cmd.cmd */ 34*4882a593Smuzhiyun DRA7XX_CORE_IOPAD(0x375c, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat0.dat0 */ 35*4882a593Smuzhiyun DRA7XX_CORE_IOPAD(0x3760, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat1.dat1 */ 36*4882a593Smuzhiyun DRA7XX_CORE_IOPAD(0x3764, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat2.dat2 */ 37*4882a593Smuzhiyun DRA7XX_CORE_IOPAD(0x3768, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat3.dat3 */ 38*4882a593Smuzhiyun >; 39*4882a593Smuzhiyun }; 40*4882a593Smuzhiyun 41*4882a593Smuzhiyun mmc1_pins_hs: mmc1_pins_hs { 42*4882a593Smuzhiyun pinctrl-single,pins = < 43*4882a593Smuzhiyun DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0) /* mmc1_clk.clk */ 44*4882a593Smuzhiyun DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0) /* mmc1_cmd.cmd */ 45*4882a593Smuzhiyun DRA7XX_CORE_IOPAD(0x375c, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0) /* mmc1_dat0.dat0 */ 46*4882a593Smuzhiyun DRA7XX_CORE_IOPAD(0x3760, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0) /* mmc1_dat1.dat1 */ 47*4882a593Smuzhiyun DRA7XX_CORE_IOPAD(0x3764, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0) /* mmc1_dat2.dat2 */ 48*4882a593Smuzhiyun DRA7XX_CORE_IOPAD(0x3768, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0) /* mmc1_dat3.dat3 */ 49*4882a593Smuzhiyun >; 50*4882a593Smuzhiyun }; 51*4882a593Smuzhiyun 52*4882a593Smuzhiyun mmc1_pins_sdr50: mmc1_pins_sdr50 { 53*4882a593Smuzhiyun pinctrl-single,pins = < 54*4882a593Smuzhiyun DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE10 | MUX_MODE0) /* mmc1_clk.clk */ 55*4882a593Smuzhiyun DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE10 | MUX_MODE0) /* mmc1_cmd.cmd */ 56*4882a593Smuzhiyun DRA7XX_CORE_IOPAD(0x375c, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE10 | MUX_MODE0) /* mmc1_dat0.dat0 */ 57*4882a593Smuzhiyun DRA7XX_CORE_IOPAD(0x3760, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE10 | MUX_MODE0) /* mmc1_dat1.dat1 */ 58*4882a593Smuzhiyun DRA7XX_CORE_IOPAD(0x3764, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE10 | MUX_MODE0) /* mmc1_dat2.dat2 */ 59*4882a593Smuzhiyun DRA7XX_CORE_IOPAD(0x3768, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE10 | MUX_MODE0) /* mmc1_dat3.dat3 */ 60*4882a593Smuzhiyun >; 61*4882a593Smuzhiyun }; 62*4882a593Smuzhiyun 63*4882a593Smuzhiyun mmc1_pins_ddr50: mmc1_pins_ddr50 { 64*4882a593Smuzhiyun pinctrl-single,pins = < 65*4882a593Smuzhiyun DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0) /* mmc1_clk.clk */ 66*4882a593Smuzhiyun DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0) /* mmc1_cmd.cmd */ 67*4882a593Smuzhiyun DRA7XX_CORE_IOPAD(0x375c, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0) /* mmc1_dat0.dat0 */ 68*4882a593Smuzhiyun DRA7XX_CORE_IOPAD(0x3760, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0) /* mmc1_dat1.dat1 */ 69*4882a593Smuzhiyun DRA7XX_CORE_IOPAD(0x3764, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0) /* mmc1_dat2.dat2 */ 70*4882a593Smuzhiyun DRA7XX_CORE_IOPAD(0x3768, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0) /* mmc1_dat3.dat3 */ 71*4882a593Smuzhiyun >; 72*4882a593Smuzhiyun }; 73*4882a593Smuzhiyun 74*4882a593Smuzhiyun mmc2_pins_default: mmc2_pins_default { 75*4882a593Smuzhiyun pinctrl-single,pins = < 76*4882a593Smuzhiyun DRA7XX_CORE_IOPAD(0x349c, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a23.mmc2_clk */ 77*4882a593Smuzhiyun DRA7XX_CORE_IOPAD(0x34b0, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_cs1.mmc2_cmd */ 78*4882a593Smuzhiyun DRA7XX_CORE_IOPAD(0x34a0, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a24.mmc2_dat0 */ 79*4882a593Smuzhiyun DRA7XX_CORE_IOPAD(0x34a4, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a25.mmc2_dat1 */ 80*4882a593Smuzhiyun DRA7XX_CORE_IOPAD(0x34a8, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a26.mmc2_dat2 */ 81*4882a593Smuzhiyun DRA7XX_CORE_IOPAD(0x34ac, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a27.mmc2_dat3 */ 82*4882a593Smuzhiyun DRA7XX_CORE_IOPAD(0x348c, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a19.mmc2_dat4 */ 83*4882a593Smuzhiyun DRA7XX_CORE_IOPAD(0x3490, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a20.mmc2_dat5 */ 84*4882a593Smuzhiyun DRA7XX_CORE_IOPAD(0x3494, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a21.mmc2_dat6 */ 85*4882a593Smuzhiyun DRA7XX_CORE_IOPAD(0x3498, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a22.mmc2_dat7 */ 86*4882a593Smuzhiyun >; 87*4882a593Smuzhiyun }; 88*4882a593Smuzhiyun 89*4882a593Smuzhiyun mmc2_pins_hs200: mmc2_pins_hs200 { 90*4882a593Smuzhiyun pinctrl-single,pins = < 91*4882a593Smuzhiyun DRA7XX_CORE_IOPAD(0x349c, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a23.mmc2_clk */ 92*4882a593Smuzhiyun DRA7XX_CORE_IOPAD(0x34b0, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_cs1.mmc2_cmd */ 93*4882a593Smuzhiyun DRA7XX_CORE_IOPAD(0x34a0, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a24.mmc2_dat0 */ 94*4882a593Smuzhiyun DRA7XX_CORE_IOPAD(0x34a4, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a25.mmc2_dat1 */ 95*4882a593Smuzhiyun DRA7XX_CORE_IOPAD(0x34a8, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a26.mmc2_dat2 */ 96*4882a593Smuzhiyun DRA7XX_CORE_IOPAD(0x34ac, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a27.mmc2_dat3 */ 97*4882a593Smuzhiyun DRA7XX_CORE_IOPAD(0x348c, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a19.mmc2_dat4 */ 98*4882a593Smuzhiyun DRA7XX_CORE_IOPAD(0x3490, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a20.mmc2_dat5 */ 99*4882a593Smuzhiyun DRA7XX_CORE_IOPAD(0x3494, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a21.mmc2_dat6 */ 100*4882a593Smuzhiyun DRA7XX_CORE_IOPAD(0x3498, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a22.mmc2_dat7 */ 101*4882a593Smuzhiyun >; 102*4882a593Smuzhiyun }; 103*4882a593Smuzhiyun 104*4882a593Smuzhiyun mmc3_pins_default: mmc3_pins_default { 105*4882a593Smuzhiyun pinctrl-single,pins = < 106*4882a593Smuzhiyun DRA7XX_CORE_IOPAD(0x377c, (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)) /* mmc3_clk.mmc3_clk */ 107*4882a593Smuzhiyun DRA7XX_CORE_IOPAD(0x3780, (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)) /* mmc3_cmd.mmc3_cmd */ 108*4882a593Smuzhiyun DRA7XX_CORE_IOPAD(0x3784, (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)) /* mmc3_dat0.mmc3_dat0 */ 109*4882a593Smuzhiyun DRA7XX_CORE_IOPAD(0x3788, (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)) /* mmc3_dat1.mmc3_dat1 */ 110*4882a593Smuzhiyun DRA7XX_CORE_IOPAD(0x378c, (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)) /* mmc3_dat2.mmc3_dat2 */ 111*4882a593Smuzhiyun DRA7XX_CORE_IOPAD(0x3790, (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)) /* mmc3_dat3.mmc3_dat3 */ 112*4882a593Smuzhiyun >; 113*4882a593Smuzhiyun }; 114*4882a593Smuzhiyun 115*4882a593Smuzhiyun mmc4_pins_hs: mmc4_pins_hs { 116*4882a593Smuzhiyun pinctrl-single,pins = < 117*4882a593Smuzhiyun DRA7XX_CORE_IOPAD(0x37e8, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart1_ctsn.mmc4_clk */ 118*4882a593Smuzhiyun DRA7XX_CORE_IOPAD(0x37ec, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart1_rtsn.mmc4_cmd */ 119*4882a593Smuzhiyun DRA7XX_CORE_IOPAD(0x37f0, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart2_rxd.mmc4_dat0 */ 120*4882a593Smuzhiyun DRA7XX_CORE_IOPAD(0x37f4, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart2_txd.mmc4_dat1 */ 121*4882a593Smuzhiyun DRA7XX_CORE_IOPAD(0x37f8, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart2_ctsn.mmc4_dat2 */ 122*4882a593Smuzhiyun DRA7XX_CORE_IOPAD(0x37fc, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart2_rtsn.mmc4_dat3 */ 123*4882a593Smuzhiyun >; 124*4882a593Smuzhiyun }; 125*4882a593Smuzhiyun}; 126*4882a593Smuzhiyun 127*4882a593Smuzhiyun&dra7_iodelay_core { 128*4882a593Smuzhiyun 129*4882a593Smuzhiyun /* Corresponds to MMC1_DDR_MANUAL1 in datamanual */ 130*4882a593Smuzhiyun mmc1_iodelay_ddr_conf: mmc1_iodelay_ddr_conf { 131*4882a593Smuzhiyun pinctrl-pin-array = < 132*4882a593Smuzhiyun 0x618 A_DELAY_PS(489) G_DELAY_PS(0) /* CFG_MMC1_CLK_IN */ 133*4882a593Smuzhiyun 0x624 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_CMD_IN */ 134*4882a593Smuzhiyun 0x630 A_DELAY_PS(374) G_DELAY_PS(0) /* CFG_MMC1_DAT0_IN */ 135*4882a593Smuzhiyun 0x63c A_DELAY_PS(31) G_DELAY_PS(0) /* CFG_MMC1_DAT1_IN */ 136*4882a593Smuzhiyun 0x648 A_DELAY_PS(56) G_DELAY_PS(0) /* CFG_MMC1_DAT2_IN */ 137*4882a593Smuzhiyun 0x654 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT3_IN */ 138*4882a593Smuzhiyun 0x620 A_DELAY_PS(1355) G_DELAY_PS(0) /* CFG_MMC1_CLK_OUT */ 139*4882a593Smuzhiyun 0x628 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_CMD_OEN */ 140*4882a593Smuzhiyun 0x62c A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_CMD_OUT */ 141*4882a593Smuzhiyun 0x634 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT0_OEN */ 142*4882a593Smuzhiyun 0x638 A_DELAY_PS(0) G_DELAY_PS(4) /* CFG_MMC1_DAT0_OUT */ 143*4882a593Smuzhiyun 0x640 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT1_OEN */ 144*4882a593Smuzhiyun 0x644 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT1_OUT */ 145*4882a593Smuzhiyun 0x64c A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT2_OEN */ 146*4882a593Smuzhiyun 0x650 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT2_OUT */ 147*4882a593Smuzhiyun 0x658 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT3_OEN */ 148*4882a593Smuzhiyun 0x65c A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT3_OUT */ 149*4882a593Smuzhiyun >; 150*4882a593Smuzhiyun }; 151*4882a593Smuzhiyun 152*4882a593Smuzhiyun /* Corresponds to MMC1_SDR104_MANUAL1 in datamanual */ 153*4882a593Smuzhiyun mmc1_iodelay_sdr104_conf: mmc1_iodelay_sdr104_conf { 154*4882a593Smuzhiyun pinctrl-pin-array = < 155*4882a593Smuzhiyun 0x620 A_DELAY_PS(892) G_DELAY_PS(0) /* CFG_MMC1_CLK_OUT */ 156*4882a593Smuzhiyun 0x628 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_CMD_OEN */ 157*4882a593Smuzhiyun 0x62c A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_CMD_OUT */ 158*4882a593Smuzhiyun 0x634 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT0_OEN */ 159*4882a593Smuzhiyun 0x638 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT0_OUT */ 160*4882a593Smuzhiyun 0x640 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT1_OEN */ 161*4882a593Smuzhiyun 0x644 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT1_OUT */ 162*4882a593Smuzhiyun 0x64c A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT2_OEN */ 163*4882a593Smuzhiyun 0x650 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT2_OUT */ 164*4882a593Smuzhiyun 0x658 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT3_OEN */ 165*4882a593Smuzhiyun 0x65c A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT3_OUT */ 166*4882a593Smuzhiyun >; 167*4882a593Smuzhiyun }; 168*4882a593Smuzhiyun 169*4882a593Smuzhiyun /* Corresponds to MMC2_HS200_MANUAL1 in datamanual */ 170*4882a593Smuzhiyun mmc2_iodelay_hs200_conf: mmc2_iodelay_hs200_conf { 171*4882a593Smuzhiyun pinctrl-pin-array = < 172*4882a593Smuzhiyun 0x190 A_DELAY_PS(384) G_DELAY_PS(0) /* CFG_GPMC_A19_OEN */ 173*4882a593Smuzhiyun 0x194 A_DELAY_PS(350) G_DELAY_PS(174) /* CFG_GPMC_A19_OUT */ 174*4882a593Smuzhiyun 0x1a8 A_DELAY_PS(410) G_DELAY_PS(0) /* CFG_GPMC_A20_OEN */ 175*4882a593Smuzhiyun 0x1ac A_DELAY_PS(335) G_DELAY_PS(0) /* CFG_GPMC_A20_OUT */ 176*4882a593Smuzhiyun 0x1b4 A_DELAY_PS(468) G_DELAY_PS(0) /* CFG_GPMC_A21_OEN */ 177*4882a593Smuzhiyun 0x1b8 A_DELAY_PS(339) G_DELAY_PS(0) /* CFG_GPMC_A21_OUT */ 178*4882a593Smuzhiyun 0x1c0 A_DELAY_PS(676) G_DELAY_PS(0) /* CFG_GPMC_A22_OEN */ 179*4882a593Smuzhiyun 0x1c4 A_DELAY_PS(219) G_DELAY_PS(0) /* CFG_GPMC_A22_OUT */ 180*4882a593Smuzhiyun 0x1d0 A_DELAY_PS(1062) G_DELAY_PS(154) /* CFG_GPMC_A23_OUT */ 181*4882a593Smuzhiyun 0x1d8 A_DELAY_PS(640) G_DELAY_PS(0) /* CFG_GPMC_A24_OEN */ 182*4882a593Smuzhiyun 0x1dc A_DELAY_PS(150) G_DELAY_PS(0) /* CFG_GPMC_A24_OUT */ 183*4882a593Smuzhiyun 0x1e4 A_DELAY_PS(356) G_DELAY_PS(0) /* CFG_GPMC_A25_OEN */ 184*4882a593Smuzhiyun 0x1e8 A_DELAY_PS(150) G_DELAY_PS(0) /* CFG_GPMC_A25_OUT */ 185*4882a593Smuzhiyun 0x1f0 A_DELAY_PS(579) G_DELAY_PS(0) /* CFG_GPMC_A26_OEN */ 186*4882a593Smuzhiyun 0x1f4 A_DELAY_PS(200) G_DELAY_PS(0) /* CFG_GPMC_A26_OUT */ 187*4882a593Smuzhiyun 0x1fc A_DELAY_PS(435) G_DELAY_PS(0) /* CFG_GPMC_A27_OEN */ 188*4882a593Smuzhiyun 0x200 A_DELAY_PS(236) G_DELAY_PS(0) /* CFG_GPMC_A27_OUT */ 189*4882a593Smuzhiyun 0x364 A_DELAY_PS(759) G_DELAY_PS(0) /* CFG_GPMC_CS1_OEN */ 190*4882a593Smuzhiyun 0x368 A_DELAY_PS(372) G_DELAY_PS(0) /* CFG_GPMC_CS1_OUT */ 191*4882a593Smuzhiyun >; 192*4882a593Smuzhiyun }; 193*4882a593Smuzhiyun 194*4882a593Smuzhiyun /* Corresponds to MMC3_MANUAL1 in datamanual */ 195*4882a593Smuzhiyun mmc3_iodelay_manual1_conf: mmc3_iodelay_manual1_conf { 196*4882a593Smuzhiyun pinctrl-pin-array = < 197*4882a593Smuzhiyun 0x678 A_DELAY_PS(0) G_DELAY_PS(386) /* CFG_MMC3_CLK_IN */ 198*4882a593Smuzhiyun 0x680 A_DELAY_PS(605) G_DELAY_PS(0) /* CFG_MMC3_CLK_OUT */ 199*4882a593Smuzhiyun 0x684 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC3_CMD_IN */ 200*4882a593Smuzhiyun 0x688 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC3_CMD_OEN */ 201*4882a593Smuzhiyun 0x68c A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC3_CMD_OUT */ 202*4882a593Smuzhiyun 0x690 A_DELAY_PS(171) G_DELAY_PS(0) /* CFG_MMC3_DAT0_IN */ 203*4882a593Smuzhiyun 0x694 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC3_DAT0_OEN */ 204*4882a593Smuzhiyun 0x698 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC3_DAT0_OUT */ 205*4882a593Smuzhiyun 0x69c A_DELAY_PS(221) G_DELAY_PS(0) /* CFG_MMC3_DAT1_IN */ 206*4882a593Smuzhiyun 0x6a0 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC3_DAT1_OEN */ 207*4882a593Smuzhiyun 0x6a4 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC3_DAT1_OUT */ 208*4882a593Smuzhiyun 0x6a8 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC3_DAT2_IN */ 209*4882a593Smuzhiyun 0x6ac A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC3_DAT2_OEN */ 210*4882a593Smuzhiyun 0x6b0 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC3_DAT2_OUT */ 211*4882a593Smuzhiyun 0x6b4 A_DELAY_PS(474) G_DELAY_PS(0) /* CFG_MMC3_DAT3_IN */ 212*4882a593Smuzhiyun 0x6b8 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC3_DAT3_OEN */ 213*4882a593Smuzhiyun 0x6bc A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC3_DAT3_OUT */ 214*4882a593Smuzhiyun >; 215*4882a593Smuzhiyun }; 216*4882a593Smuzhiyun 217*4882a593Smuzhiyun /* Corresponds to MMC3_MANUAL2 in datamanual */ 218*4882a593Smuzhiyun mmc3_iodelay_sdr50_conf: mmc3_iodelay_sdr50_conf { 219*4882a593Smuzhiyun pinctrl-pin-array = < 220*4882a593Smuzhiyun 0x678 A_DELAY_PS(852) G_DELAY_PS(0) /* CFG_MMC3_CLK_IN */ 221*4882a593Smuzhiyun 0x680 A_DELAY_PS(94) G_DELAY_PS(0) /* CFG_MMC3_CLK_OUT */ 222*4882a593Smuzhiyun 0x684 A_DELAY_PS(122) G_DELAY_PS(0) /* CFG_MMC3_CMD_IN */ 223*4882a593Smuzhiyun 0x688 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC3_CMD_OEN */ 224*4882a593Smuzhiyun 0x68c A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC3_CMD_OUT */ 225*4882a593Smuzhiyun 0x690 A_DELAY_PS(91) G_DELAY_PS(0) /* CFG_MMC3_DAT0_IN */ 226*4882a593Smuzhiyun 0x694 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC3_DAT0_OEN */ 227*4882a593Smuzhiyun 0x698 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC3_DAT0_OUT */ 228*4882a593Smuzhiyun 0x69c A_DELAY_PS(57) G_DELAY_PS(0) /* CFG_MMC3_DAT1_IN */ 229*4882a593Smuzhiyun 0x6a0 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC3_DAT1_OEN */ 230*4882a593Smuzhiyun 0x6a4 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC3_DAT1_OUT */ 231*4882a593Smuzhiyun 0x6a8 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC3_DAT2_IN */ 232*4882a593Smuzhiyun 0x6ac A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC3_DAT2_OEN */ 233*4882a593Smuzhiyun 0x6b0 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC3_DAT2_OUT */ 234*4882a593Smuzhiyun 0x6b4 A_DELAY_PS(375) G_DELAY_PS(0) /* CFG_MMC3_DAT3_IN */ 235*4882a593Smuzhiyun 0x6b8 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC3_DAT3_OEN */ 236*4882a593Smuzhiyun 0x6bc A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC3_DAT3_OUT */ 237*4882a593Smuzhiyun >; 238*4882a593Smuzhiyun }; 239*4882a593Smuzhiyun 240*4882a593Smuzhiyun /* Corresponds to MMC4_MANUAL1 in datamanual */ 241*4882a593Smuzhiyun mmc4_iodelay_manual1_conf: mmc4_iodelay_manual1_conf { 242*4882a593Smuzhiyun pinctrl-pin-array = < 243*4882a593Smuzhiyun 0x840 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART1_CTSN_IN */ 244*4882a593Smuzhiyun 0x848 A_DELAY_PS(1147) G_DELAY_PS(0) /* CFG_UART1_CTSN_OUT */ 245*4882a593Smuzhiyun 0x84c A_DELAY_PS(1834) G_DELAY_PS(0) /* CFG_UART1_RTSN_IN */ 246*4882a593Smuzhiyun 0x850 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART1_RTSN_OEN */ 247*4882a593Smuzhiyun 0x854 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART1_RTSN_OUT */ 248*4882a593Smuzhiyun 0x870 A_DELAY_PS(2165) G_DELAY_PS(0) /* CFG_UART2_CTSN_IN */ 249*4882a593Smuzhiyun 0x874 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART2_CTSN_OEN */ 250*4882a593Smuzhiyun 0x878 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART2_CTSN_OUT */ 251*4882a593Smuzhiyun 0x87c A_DELAY_PS(1929) G_DELAY_PS(64) /* CFG_UART2_RTSN_IN */ 252*4882a593Smuzhiyun 0x880 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART2_RTSN_OEN */ 253*4882a593Smuzhiyun 0x884 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART2_RTSN_OUT */ 254*4882a593Smuzhiyun 0x888 A_DELAY_PS(1935) G_DELAY_PS(128) /* CFG_UART2_RXD_IN */ 255*4882a593Smuzhiyun 0x88c A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART2_RXD_OEN */ 256*4882a593Smuzhiyun 0x890 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART2_RXD_OUT */ 257*4882a593Smuzhiyun 0x894 A_DELAY_PS(2172) G_DELAY_PS(44) /* CFG_UART2_TXD_IN */ 258*4882a593Smuzhiyun 0x898 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART2_TXD_OEN */ 259*4882a593Smuzhiyun 0x89c A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART2_TXD_OUT */ 260*4882a593Smuzhiyun >; 261*4882a593Smuzhiyun }; 262*4882a593Smuzhiyun 263*4882a593Smuzhiyun /* Corresponds to MMC4_DS_MANUAL1 in datamanual */ 264*4882a593Smuzhiyun mmc4_iodelay_default_conf: mmc4_iodelay_default_conf { 265*4882a593Smuzhiyun pinctrl-pin-array = < 266*4882a593Smuzhiyun 0x840 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART1_CTSN_IN */ 267*4882a593Smuzhiyun 0x848 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART1_CTSN_OUT */ 268*4882a593Smuzhiyun 0x84c A_DELAY_PS(307) G_DELAY_PS(0) /* CFG_UART1_RTSN_IN */ 269*4882a593Smuzhiyun 0x850 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART1_RTSN_OEN */ 270*4882a593Smuzhiyun 0x854 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART1_RTSN_OUT */ 271*4882a593Smuzhiyun 0x870 A_DELAY_PS(785) G_DELAY_PS(0) /* CFG_UART2_CTSN_IN */ 272*4882a593Smuzhiyun 0x874 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART2_CTSN_OEN */ 273*4882a593Smuzhiyun 0x878 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART2_CTSN_OUT */ 274*4882a593Smuzhiyun 0x87c A_DELAY_PS(613) G_DELAY_PS(0) /* CFG_UART2_RTSN_IN */ 275*4882a593Smuzhiyun 0x880 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART2_RTSN_OEN */ 276*4882a593Smuzhiyun 0x884 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART2_RTSN_OUT */ 277*4882a593Smuzhiyun 0x888 A_DELAY_PS(683) G_DELAY_PS(0) /* CFG_UART2_RXD_IN */ 278*4882a593Smuzhiyun 0x88c A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART2_RXD_OEN */ 279*4882a593Smuzhiyun 0x890 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART2_RXD_OUT */ 280*4882a593Smuzhiyun 0x894 A_DELAY_PS(835) G_DELAY_PS(0) /* CFG_UART2_TXD_IN */ 281*4882a593Smuzhiyun 0x898 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART2_TXD_OEN */ 282*4882a593Smuzhiyun 0x89c A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART2_TXD_OUT */ 283*4882a593Smuzhiyun >; 284*4882a593Smuzhiyun }; 285*4882a593Smuzhiyun}; 286