1*4882a593Smuzhiyun// SPDX-License-Identifier: GPL-2.0-or-later 2*4882a593Smuzhiyun/* 3*4882a593Smuzhiyun * Device Tree for AM1808 EnBW CMC board 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Copyright 2012 DENX Software Engineering GmbH 6*4882a593Smuzhiyun * Heiko Schocher <hs@denx.de> 7*4882a593Smuzhiyun */ 8*4882a593Smuzhiyun/dts-v1/; 9*4882a593Smuzhiyun#include "da850.dtsi" 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun/ { 12*4882a593Smuzhiyun compatible = "enbw,cmc", "ti,da850"; 13*4882a593Smuzhiyun model = "EnBW CMC"; 14*4882a593Smuzhiyun 15*4882a593Smuzhiyun soc@1c00000 { 16*4882a593Smuzhiyun serial0: serial@42000 { 17*4882a593Smuzhiyun status = "okay"; 18*4882a593Smuzhiyun }; 19*4882a593Smuzhiyun serial1: serial@10c000 { 20*4882a593Smuzhiyun status = "okay"; 21*4882a593Smuzhiyun }; 22*4882a593Smuzhiyun serial2: serial@10d000 { 23*4882a593Smuzhiyun status = "okay"; 24*4882a593Smuzhiyun }; 25*4882a593Smuzhiyun mdio: mdio@224000 { 26*4882a593Smuzhiyun status = "okay"; 27*4882a593Smuzhiyun }; 28*4882a593Smuzhiyun eth0: ethernet@220000 { 29*4882a593Smuzhiyun status = "okay"; 30*4882a593Smuzhiyun }; 31*4882a593Smuzhiyun }; 32*4882a593Smuzhiyun}; 33*4882a593Smuzhiyun 34*4882a593Smuzhiyun&ref_clk { 35*4882a593Smuzhiyun clock-frequency = <24000000>; 36*4882a593Smuzhiyun}; 37*4882a593Smuzhiyun 38*4882a593Smuzhiyun&edma0 { 39*4882a593Smuzhiyun ti,edma-reserved-slot-ranges = <32 50>; 40*4882a593Smuzhiyun}; 41*4882a593Smuzhiyun 42*4882a593Smuzhiyun&edma1 { 43*4882a593Smuzhiyun ti,edma-reserved-slot-ranges = <32 90>; 44*4882a593Smuzhiyun}; 45