1*4882a593Smuzhiyun// SPDX-License-Identifier: GPL-2.0-or-later 2*4882a593Smuzhiyun/* 3*4882a593Smuzhiyun * at91-cosino.dtsi - Device Tree file for Cosino core module 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Copyright (C) 2013 - Rodolfo Giometti <giometti@linux.it> 6*4882a593Smuzhiyun * HCE Engineering 7*4882a593Smuzhiyun * 8*4882a593Smuzhiyun * Derived from at91sam9x5ek.dtsi by: 9*4882a593Smuzhiyun * Copyright (C) 2012 Atmel, 10*4882a593Smuzhiyun * 2012 Nicolas Ferre <nicolas.ferre@atmel.com> 11*4882a593Smuzhiyun */ 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun#include "at91sam9g35.dtsi" 14*4882a593Smuzhiyun 15*4882a593Smuzhiyun/ { 16*4882a593Smuzhiyun model = "HCE Cosino core module"; 17*4882a593Smuzhiyun compatible = "hce,cosino", "atmel,at91sam9x5", "atmel,at91sam9"; 18*4882a593Smuzhiyun 19*4882a593Smuzhiyun chosen { 20*4882a593Smuzhiyun bootargs = "console=ttyS0,115200 root=/dev/mmcblk0p2 rw rootfstype=ext3 rootwait"; 21*4882a593Smuzhiyun }; 22*4882a593Smuzhiyun 23*4882a593Smuzhiyun memory@20000000 { 24*4882a593Smuzhiyun reg = <0x20000000 0x8000000>; 25*4882a593Smuzhiyun }; 26*4882a593Smuzhiyun 27*4882a593Smuzhiyun clocks { 28*4882a593Smuzhiyun slow_xtal { 29*4882a593Smuzhiyun clock-frequency = <32768>; 30*4882a593Smuzhiyun }; 31*4882a593Smuzhiyun 32*4882a593Smuzhiyun main_xtal { 33*4882a593Smuzhiyun clock-frequency = <12000000>; 34*4882a593Smuzhiyun }; 35*4882a593Smuzhiyun }; 36*4882a593Smuzhiyun}; 37*4882a593Smuzhiyun 38*4882a593Smuzhiyun&adc0 { 39*4882a593Smuzhiyun atmel,adc-ts-wires = <4>; 40*4882a593Smuzhiyun atmel,adc-ts-pressure-threshold = <10000>; 41*4882a593Smuzhiyun status = "okay"; 42*4882a593Smuzhiyun}; 43*4882a593Smuzhiyun 44*4882a593Smuzhiyun&dbgu { 45*4882a593Smuzhiyun status = "okay"; 46*4882a593Smuzhiyun}; 47*4882a593Smuzhiyun 48*4882a593Smuzhiyun&ebi { 49*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_ebi_addr_nand 50*4882a593Smuzhiyun &pinctrl_ebi_data_0_7>; 51*4882a593Smuzhiyun pinctrl-names = "default"; 52*4882a593Smuzhiyun status = "okay"; 53*4882a593Smuzhiyun 54*4882a593Smuzhiyun nand-controller { 55*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_nand_oe_we 56*4882a593Smuzhiyun &pinctrl_nand_cs 57*4882a593Smuzhiyun &pinctrl_nand_rb>; 58*4882a593Smuzhiyun pinctrl-names = "default"; 59*4882a593Smuzhiyun status = "okay"; 60*4882a593Smuzhiyun 61*4882a593Smuzhiyun nand@3 { 62*4882a593Smuzhiyun reg = <0x3 0x0 0x800000>; 63*4882a593Smuzhiyun rb-gpios = <&pioD 5 GPIO_ACTIVE_HIGH>; 64*4882a593Smuzhiyun cs-gpios = <&pioD 4 GPIO_ACTIVE_HIGH>; 65*4882a593Smuzhiyun nand-bus-width = <8>; 66*4882a593Smuzhiyun nand-ecc-mode = "hw"; 67*4882a593Smuzhiyun nand-ecc-strength = <4>; 68*4882a593Smuzhiyun nand-ecc-step-size = <512>; 69*4882a593Smuzhiyun nand-on-flash-bbt; 70*4882a593Smuzhiyun label = "atmel_nand"; 71*4882a593Smuzhiyun 72*4882a593Smuzhiyun partitions { 73*4882a593Smuzhiyun compatible = "fixed-partitions"; 74*4882a593Smuzhiyun #address-cells = <1>; 75*4882a593Smuzhiyun #size-cells = <1>; 76*4882a593Smuzhiyun 77*4882a593Smuzhiyun at91bootstrap@0 { 78*4882a593Smuzhiyun label = "at91bootstrap"; 79*4882a593Smuzhiyun reg = <0x0 0x40000>; 80*4882a593Smuzhiyun }; 81*4882a593Smuzhiyun 82*4882a593Smuzhiyun uboot@40000 { 83*4882a593Smuzhiyun label = "u-boot"; 84*4882a593Smuzhiyun reg = <0x40000 0x80000>; 85*4882a593Smuzhiyun }; 86*4882a593Smuzhiyun 87*4882a593Smuzhiyun ubootenv@c0000 { 88*4882a593Smuzhiyun label = "U-Boot Env"; 89*4882a593Smuzhiyun reg = <0xc0000 0x140000>; 90*4882a593Smuzhiyun }; 91*4882a593Smuzhiyun 92*4882a593Smuzhiyun kernel@200000 { 93*4882a593Smuzhiyun label = "kernel"; 94*4882a593Smuzhiyun reg = <0x200000 0x600000>; 95*4882a593Smuzhiyun }; 96*4882a593Smuzhiyun 97*4882a593Smuzhiyun rootfs@800000 { 98*4882a593Smuzhiyun label = "rootfs"; 99*4882a593Smuzhiyun reg = <0x800000 0x0f800000>; 100*4882a593Smuzhiyun }; 101*4882a593Smuzhiyun }; 102*4882a593Smuzhiyun }; 103*4882a593Smuzhiyun }; 104*4882a593Smuzhiyun}; 105*4882a593Smuzhiyun 106*4882a593Smuzhiyun&i2c0 { 107*4882a593Smuzhiyun status = "okay"; 108*4882a593Smuzhiyun}; 109*4882a593Smuzhiyun 110*4882a593Smuzhiyun&mmc0 { 111*4882a593Smuzhiyun pinctrl-0 = < 112*4882a593Smuzhiyun &pinctrl_board_mmc0 113*4882a593Smuzhiyun &pinctrl_mmc0_slot0_clk_cmd_dat0 114*4882a593Smuzhiyun &pinctrl_mmc0_slot0_dat1_3>; 115*4882a593Smuzhiyun pinctrl-names = "default"; 116*4882a593Smuzhiyun status = "okay"; 117*4882a593Smuzhiyun 118*4882a593Smuzhiyun slot@0 { 119*4882a593Smuzhiyun reg = <0>; 120*4882a593Smuzhiyun bus-width = <4>; 121*4882a593Smuzhiyun cd-gpios = <&pioD 15 GPIO_ACTIVE_HIGH>; 122*4882a593Smuzhiyun }; 123*4882a593Smuzhiyun}; 124*4882a593Smuzhiyun 125*4882a593Smuzhiyun&pinctrl { 126*4882a593Smuzhiyun mmc0 { 127*4882a593Smuzhiyun pinctrl_board_mmc0: mmc0-board { 128*4882a593Smuzhiyun atmel,pins = 129*4882a593Smuzhiyun <AT91_PIOD 15 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP_DEGLITCH>; /* PD15 gpio CD pin pull up and deglitch */ 130*4882a593Smuzhiyun }; 131*4882a593Smuzhiyun }; 132*4882a593Smuzhiyun}; 133*4882a593Smuzhiyun 134*4882a593Smuzhiyun&tcb0 { 135*4882a593Smuzhiyun timer@0 { 136*4882a593Smuzhiyun compatible = "atmel,tcb-timer"; 137*4882a593Smuzhiyun reg = <0>; 138*4882a593Smuzhiyun }; 139*4882a593Smuzhiyun 140*4882a593Smuzhiyun timer@1 { 141*4882a593Smuzhiyun compatible = "atmel,tcb-timer"; 142*4882a593Smuzhiyun reg = <1>; 143*4882a593Smuzhiyun }; 144*4882a593Smuzhiyun}; 145*4882a593Smuzhiyun 146*4882a593Smuzhiyun&usart0 { 147*4882a593Smuzhiyun status = "okay"; 148*4882a593Smuzhiyun}; 149*4882a593Smuzhiyun 150*4882a593Smuzhiyun&watchdog { 151*4882a593Smuzhiyun status = "okay"; 152*4882a593Smuzhiyun}; 153