xref: /OK3568_Linux_fs/kernel/scripts/dtc/include-prefixes/arm/armada-385-clearfog-gtr-s4.dts (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun// SPDX-License-Identifier: (GPL-2.0 OR MIT)
2*4882a593Smuzhiyun
3*4882a593Smuzhiyun#include "armada-385-clearfog-gtr.dtsi"
4*4882a593Smuzhiyun
5*4882a593Smuzhiyun/ {
6*4882a593Smuzhiyun	model = "SolidRun Clearfog GTR S4";
7*4882a593Smuzhiyun};
8*4882a593Smuzhiyun
9*4882a593Smuzhiyun&sfp0 {
10*4882a593Smuzhiyun	tx-fault-gpio = <&gpio0 24 GPIO_ACTIVE_HIGH>;
11*4882a593Smuzhiyun};
12*4882a593Smuzhiyun
13*4882a593Smuzhiyun&mdio {
14*4882a593Smuzhiyun	switch0: switch0@4 {
15*4882a593Smuzhiyun		compatible = "marvell,mv88e6085";
16*4882a593Smuzhiyun		reg = <4>;
17*4882a593Smuzhiyun		pinctrl-names = "default";
18*4882a593Smuzhiyun		pinctrl-0 = <&cf_gtr_switch_reset_pins>;
19*4882a593Smuzhiyun		reset-gpios = <&gpio0 18 GPIO_ACTIVE_LOW>;
20*4882a593Smuzhiyun
21*4882a593Smuzhiyun		ports {
22*4882a593Smuzhiyun			#address-cells = <1>;
23*4882a593Smuzhiyun			#size-cells = <0>;
24*4882a593Smuzhiyun
25*4882a593Smuzhiyun			port@1 {
26*4882a593Smuzhiyun				reg = <1>;
27*4882a593Smuzhiyun				label = "lan2";
28*4882a593Smuzhiyun				phy-handle = <&switch0phy0>;
29*4882a593Smuzhiyun			};
30*4882a593Smuzhiyun
31*4882a593Smuzhiyun			port@2 {
32*4882a593Smuzhiyun				reg = <2>;
33*4882a593Smuzhiyun				label = "lan1";
34*4882a593Smuzhiyun				phy-handle = <&switch0phy1>;
35*4882a593Smuzhiyun			};
36*4882a593Smuzhiyun
37*4882a593Smuzhiyun			port@3 {
38*4882a593Smuzhiyun				reg = <3>;
39*4882a593Smuzhiyun				label = "lan4";
40*4882a593Smuzhiyun				phy-handle = <&switch0phy2>;
41*4882a593Smuzhiyun			};
42*4882a593Smuzhiyun
43*4882a593Smuzhiyun			port@4 {
44*4882a593Smuzhiyun				reg = <4>;
45*4882a593Smuzhiyun				label = "lan3";
46*4882a593Smuzhiyun				phy-handle = <&switch0phy3>;
47*4882a593Smuzhiyun			};
48*4882a593Smuzhiyun
49*4882a593Smuzhiyun			port@5 {
50*4882a593Smuzhiyun				reg = <5>;
51*4882a593Smuzhiyun				label = "cpu";
52*4882a593Smuzhiyun				ethernet = <&eth1>;
53*4882a593Smuzhiyun			};
54*4882a593Smuzhiyun
55*4882a593Smuzhiyun		};
56*4882a593Smuzhiyun
57*4882a593Smuzhiyun		mdio {
58*4882a593Smuzhiyun			#address-cells = <1>;
59*4882a593Smuzhiyun			#size-cells = <0>;
60*4882a593Smuzhiyun
61*4882a593Smuzhiyun			switch0phy0: switch0phy0@11 {
62*4882a593Smuzhiyun				reg = <0x11>;
63*4882a593Smuzhiyun			};
64*4882a593Smuzhiyun
65*4882a593Smuzhiyun			switch0phy1: switch0phy1@12 {
66*4882a593Smuzhiyun				reg = <0x12>;
67*4882a593Smuzhiyun			};
68*4882a593Smuzhiyun
69*4882a593Smuzhiyun			switch0phy2: switch0phy2@13 {
70*4882a593Smuzhiyun				reg = <0x13>;
71*4882a593Smuzhiyun			};
72*4882a593Smuzhiyun
73*4882a593Smuzhiyun			switch0phy3: switch0phy3@14 {
74*4882a593Smuzhiyun				reg = <0x14>;
75*4882a593Smuzhiyun			};
76*4882a593Smuzhiyun		};
77*4882a593Smuzhiyun
78*4882a593Smuzhiyun	};
79*4882a593Smuzhiyun};
80