xref: /OK3568_Linux_fs/kernel/scripts/dtc/include-prefixes/arm/armada-370-rd.dts (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2*4882a593Smuzhiyun/*
3*4882a593Smuzhiyun * Device Tree file for Marvell Armada 370 Reference Design board
4*4882a593Smuzhiyun * (RD-88F6710-A1)
5*4882a593Smuzhiyun *
6*4882a593Smuzhiyun *  Copied from arch/arm/boot/dts/armada-370-db.dts
7*4882a593Smuzhiyun *
8*4882a593Smuzhiyun *  Copyright (C) 2013 Florian Fainelli <florian@openwrt.org>
9*4882a593Smuzhiyun *
10*4882a593Smuzhiyun * Note: this Device Tree assumes that the bootloader has remapped the
11*4882a593Smuzhiyun * internal registers to 0xf1000000 (instead of the default
12*4882a593Smuzhiyun * 0xd0000000). The 0xf1000000 is the default used by the recent,
13*4882a593Smuzhiyun * DT-capable, U-Boot bootloaders provided by Marvell. Some earlier
14*4882a593Smuzhiyun * boards were delivered with an older version of the bootloader that
15*4882a593Smuzhiyun * left internal registers mapped at 0xd0000000. If you are in this
16*4882a593Smuzhiyun * situation, you should either update your bootloader (preferred
17*4882a593Smuzhiyun * solution) or the below Device Tree should be adjusted.
18*4882a593Smuzhiyun */
19*4882a593Smuzhiyun
20*4882a593Smuzhiyun/dts-v1/;
21*4882a593Smuzhiyun#include <dt-bindings/input/input.h>
22*4882a593Smuzhiyun#include <dt-bindings/interrupt-controller/irq.h>
23*4882a593Smuzhiyun#include <dt-bindings/gpio/gpio.h>
24*4882a593Smuzhiyun#include "armada-370.dtsi"
25*4882a593Smuzhiyun
26*4882a593Smuzhiyun/ {
27*4882a593Smuzhiyun	model = "Marvell Armada 370 Reference Design";
28*4882a593Smuzhiyun	compatible = "marvell,a370-rd", "marvell,armada370", "marvell,armada-370-xp";
29*4882a593Smuzhiyun
30*4882a593Smuzhiyun	chosen {
31*4882a593Smuzhiyun		stdout-path = "serial0:115200n8";
32*4882a593Smuzhiyun	};
33*4882a593Smuzhiyun
34*4882a593Smuzhiyun	memory@0 {
35*4882a593Smuzhiyun		device_type = "memory";
36*4882a593Smuzhiyun		reg = <0x00000000 0x20000000>; /* 512 MB */
37*4882a593Smuzhiyun	};
38*4882a593Smuzhiyun
39*4882a593Smuzhiyun	soc {
40*4882a593Smuzhiyun		ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000
41*4882a593Smuzhiyun			  MBUS_ID(0x01, 0xe0) 0 0xfff00000 0x100000
42*4882a593Smuzhiyun			  MBUS_ID(0x09, 0x01) 0 0xf1100000 0x10000>;
43*4882a593Smuzhiyun
44*4882a593Smuzhiyun		internal-regs {
45*4882a593Smuzhiyun			serial@12000 {
46*4882a593Smuzhiyun				status = "okay";
47*4882a593Smuzhiyun			};
48*4882a593Smuzhiyun			sata@a0000 {
49*4882a593Smuzhiyun				nr-ports = <2>;
50*4882a593Smuzhiyun				status = "okay";
51*4882a593Smuzhiyun			};
52*4882a593Smuzhiyun
53*4882a593Smuzhiyun			ethernet@70000 {
54*4882a593Smuzhiyun				status = "okay";
55*4882a593Smuzhiyun				phy = <&phy0>;
56*4882a593Smuzhiyun				phy-mode = "sgmii";
57*4882a593Smuzhiyun			};
58*4882a593Smuzhiyun			ethernet@74000 {
59*4882a593Smuzhiyun				pinctrl-0 = <&ge1_rgmii_pins>;
60*4882a593Smuzhiyun				pinctrl-names = "default";
61*4882a593Smuzhiyun				status = "okay";
62*4882a593Smuzhiyun				phy-mode = "rgmii-id";
63*4882a593Smuzhiyun				fixed-link {
64*4882a593Smuzhiyun					   speed = <1000>;
65*4882a593Smuzhiyun					   full-duplex;
66*4882a593Smuzhiyun				};
67*4882a593Smuzhiyun			};
68*4882a593Smuzhiyun
69*4882a593Smuzhiyun			mvsdio@d4000 {
70*4882a593Smuzhiyun				pinctrl-0 = <&sdio_pins1>;
71*4882a593Smuzhiyun				pinctrl-names = "default";
72*4882a593Smuzhiyun				status = "okay";
73*4882a593Smuzhiyun				/* No CD or WP GPIOs */
74*4882a593Smuzhiyun				broken-cd;
75*4882a593Smuzhiyun			};
76*4882a593Smuzhiyun
77*4882a593Smuzhiyun			usb@50000 {
78*4882a593Smuzhiyun				status = "okay";
79*4882a593Smuzhiyun			};
80*4882a593Smuzhiyun
81*4882a593Smuzhiyun			usb@51000 {
82*4882a593Smuzhiyun				status = "okay";
83*4882a593Smuzhiyun			};
84*4882a593Smuzhiyun
85*4882a593Smuzhiyun			gpio-keys {
86*4882a593Smuzhiyun				compatible = "gpio-keys";
87*4882a593Smuzhiyun				#address-cells = <1>;
88*4882a593Smuzhiyun				#size-cells = <0>;
89*4882a593Smuzhiyun				button {
90*4882a593Smuzhiyun					label = "Software Button";
91*4882a593Smuzhiyun					linux,code = <KEY_POWER>;
92*4882a593Smuzhiyun					gpios = <&gpio0 6 GPIO_ACTIVE_LOW>;
93*4882a593Smuzhiyun				};
94*4882a593Smuzhiyun			};
95*4882a593Smuzhiyun
96*4882a593Smuzhiyun			gpio-fan {
97*4882a593Smuzhiyun				compatible = "gpio-fan";
98*4882a593Smuzhiyun				gpios = <&gpio0 8 GPIO_ACTIVE_HIGH>;
99*4882a593Smuzhiyun				gpio-fan,speed-map = <0 0 3000 1>;
100*4882a593Smuzhiyun				pinctrl-0 = <&fan_pins>;
101*4882a593Smuzhiyun				pinctrl-names = "default";
102*4882a593Smuzhiyun			};
103*4882a593Smuzhiyun
104*4882a593Smuzhiyun			gpio_leds {
105*4882a593Smuzhiyun				compatible = "gpio-leds";
106*4882a593Smuzhiyun				pinctrl-names = "default";
107*4882a593Smuzhiyun				pinctrl-0 = <&led_pins>;
108*4882a593Smuzhiyun
109*4882a593Smuzhiyun				sw_led {
110*4882a593Smuzhiyun					label = "370rd:green:sw";
111*4882a593Smuzhiyun					gpios = <&gpio1 0 GPIO_ACTIVE_LOW>;
112*4882a593Smuzhiyun					default-state = "keep";
113*4882a593Smuzhiyun				};
114*4882a593Smuzhiyun			};
115*4882a593Smuzhiyun		};
116*4882a593Smuzhiyun	};
117*4882a593Smuzhiyun};
118*4882a593Smuzhiyun
119*4882a593Smuzhiyun&pciec {
120*4882a593Smuzhiyun	status = "okay";
121*4882a593Smuzhiyun
122*4882a593Smuzhiyun	/* Internal mini-PCIe connector */
123*4882a593Smuzhiyun	pcie@1,0 {
124*4882a593Smuzhiyun		/* Port 0, Lane 0 */
125*4882a593Smuzhiyun		status = "okay";
126*4882a593Smuzhiyun	};
127*4882a593Smuzhiyun
128*4882a593Smuzhiyun	/* Internal mini-PCIe connector */
129*4882a593Smuzhiyun	pcie@2,0 {
130*4882a593Smuzhiyun		/* Port 1, Lane 0 */
131*4882a593Smuzhiyun		status = "okay";
132*4882a593Smuzhiyun	};
133*4882a593Smuzhiyun};
134*4882a593Smuzhiyun
135*4882a593Smuzhiyun&mdio {
136*4882a593Smuzhiyun	pinctrl-0 = <&mdio_pins>;
137*4882a593Smuzhiyun	pinctrl-names = "default";
138*4882a593Smuzhiyun	phy0: ethernet-phy@0 {
139*4882a593Smuzhiyun		reg = <0>;
140*4882a593Smuzhiyun	};
141*4882a593Smuzhiyun
142*4882a593Smuzhiyun	switch: switch@10 {
143*4882a593Smuzhiyun		compatible = "marvell,mv88e6085";
144*4882a593Smuzhiyun		#address-cells = <1>;
145*4882a593Smuzhiyun		#size-cells = <0>;
146*4882a593Smuzhiyun		reg = <0x10>;
147*4882a593Smuzhiyun		interrupt-controller;
148*4882a593Smuzhiyun		#interrupt-cells = <2>;
149*4882a593Smuzhiyun
150*4882a593Smuzhiyun		ports {
151*4882a593Smuzhiyun			#address-cells = <1>;
152*4882a593Smuzhiyun			#size-cells = <0>;
153*4882a593Smuzhiyun
154*4882a593Smuzhiyun			port@0 {
155*4882a593Smuzhiyun				reg = <0>;
156*4882a593Smuzhiyun				label = "lan0";
157*4882a593Smuzhiyun			};
158*4882a593Smuzhiyun
159*4882a593Smuzhiyun			port@1 {
160*4882a593Smuzhiyun			       reg = <1>;
161*4882a593Smuzhiyun			       label = "lan1";
162*4882a593Smuzhiyun			};
163*4882a593Smuzhiyun
164*4882a593Smuzhiyun			port@2 {
165*4882a593Smuzhiyun			       reg = <2>;
166*4882a593Smuzhiyun			       label = "lan2";
167*4882a593Smuzhiyun			};
168*4882a593Smuzhiyun
169*4882a593Smuzhiyun			port@3 {
170*4882a593Smuzhiyun			       reg = <3>;
171*4882a593Smuzhiyun			       label = "lan3";
172*4882a593Smuzhiyun			};
173*4882a593Smuzhiyun
174*4882a593Smuzhiyun			port@5 {
175*4882a593Smuzhiyun				reg = <5>;
176*4882a593Smuzhiyun				label = "cpu";
177*4882a593Smuzhiyun				ethernet = <&eth1>;
178*4882a593Smuzhiyun				fixed-link {
179*4882a593Smuzhiyun					speed = <1000>;
180*4882a593Smuzhiyun					full-duplex;
181*4882a593Smuzhiyun				};
182*4882a593Smuzhiyun			};
183*4882a593Smuzhiyun		};
184*4882a593Smuzhiyun
185*4882a593Smuzhiyun		mdio {
186*4882a593Smuzhiyun			#address-cells = <1>;
187*4882a593Smuzhiyun			#size-cells = <0>;
188*4882a593Smuzhiyun
189*4882a593Smuzhiyun			switchphy0: switchphy@0 {
190*4882a593Smuzhiyun				reg = <0>;
191*4882a593Smuzhiyun				interrupt-parent = <&switch>;
192*4882a593Smuzhiyun				interrupts = <0 IRQ_TYPE_LEVEL_HIGH>;
193*4882a593Smuzhiyun			};
194*4882a593Smuzhiyun
195*4882a593Smuzhiyun			switchphy1: switchphy@1 {
196*4882a593Smuzhiyun				reg = <1>;
197*4882a593Smuzhiyun				interrupt-parent = <&switch>;
198*4882a593Smuzhiyun				interrupts = <1 IRQ_TYPE_LEVEL_HIGH>;
199*4882a593Smuzhiyun			};
200*4882a593Smuzhiyun
201*4882a593Smuzhiyun			switchphy2: switchphy@2 {
202*4882a593Smuzhiyun				reg = <2>;
203*4882a593Smuzhiyun				interrupt-parent = <&switch>;
204*4882a593Smuzhiyun				interrupts = <2 IRQ_TYPE_LEVEL_HIGH>;
205*4882a593Smuzhiyun			};
206*4882a593Smuzhiyun
207*4882a593Smuzhiyun			switchphy3: switchphy@3 {
208*4882a593Smuzhiyun				reg = <3>;
209*4882a593Smuzhiyun				interrupt-parent = <&switch>;
210*4882a593Smuzhiyun				interrupts = <3 IRQ_TYPE_LEVEL_HIGH>;
211*4882a593Smuzhiyun			};
212*4882a593Smuzhiyun		};
213*4882a593Smuzhiyun	};
214*4882a593Smuzhiyun};
215*4882a593Smuzhiyun
216*4882a593Smuzhiyun
217*4882a593Smuzhiyun&pinctrl {
218*4882a593Smuzhiyun	fan_pins: fan-pins {
219*4882a593Smuzhiyun		marvell,pins = "mpp8";
220*4882a593Smuzhiyun		marvell,function = "gpio";
221*4882a593Smuzhiyun	};
222*4882a593Smuzhiyun
223*4882a593Smuzhiyun	led_pins: led-pins {
224*4882a593Smuzhiyun		marvell,pins = "mpp32";
225*4882a593Smuzhiyun		marvell,function = "gpio";
226*4882a593Smuzhiyun	};
227*4882a593Smuzhiyun};
228*4882a593Smuzhiyun
229*4882a593Smuzhiyun&nand_controller {
230*4882a593Smuzhiyun	status = "okay";
231*4882a593Smuzhiyun
232*4882a593Smuzhiyun	nand@0 {
233*4882a593Smuzhiyun		reg = <0>;
234*4882a593Smuzhiyun		label = "pxa3xx_nand-0";
235*4882a593Smuzhiyun		nand-rb = <0>;
236*4882a593Smuzhiyun		marvell,nand-keep-config;
237*4882a593Smuzhiyun		nand-on-flash-bbt;
238*4882a593Smuzhiyun
239*4882a593Smuzhiyun		partitions {
240*4882a593Smuzhiyun			compatible = "fixed-partitions";
241*4882a593Smuzhiyun			#address-cells = <1>;
242*4882a593Smuzhiyun			#size-cells = <1>;
243*4882a593Smuzhiyun
244*4882a593Smuzhiyun			partition@0 {
245*4882a593Smuzhiyun				label = "U-Boot";
246*4882a593Smuzhiyun				reg = <0 0x800000>;
247*4882a593Smuzhiyun			};
248*4882a593Smuzhiyun			partition@800000 {
249*4882a593Smuzhiyun				label = "Linux";
250*4882a593Smuzhiyun				reg = <0x800000 0x800000>;
251*4882a593Smuzhiyun			};
252*4882a593Smuzhiyun			partition@1000000 {
253*4882a593Smuzhiyun				label = "Filesystem";
254*4882a593Smuzhiyun				reg = <0x1000000 0x3f000000>;
255*4882a593Smuzhiyun			};
256*4882a593Smuzhiyun		};
257*4882a593Smuzhiyun	};
258*4882a593Smuzhiyun};
259