1*4882a593Smuzhiyun// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2*4882a593Smuzhiyun/* 3*4882a593Smuzhiyun * Device Tree file for D-Link DNS-327L 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Copyright (C) 2015, Andrew Andrianov <andrew@ncrmnt.org> 6*4882a593Smuzhiyun */ 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun/* Remaining unsolved: 9*4882a593Smuzhiyun * There's still some unknown device on i2c address 0x13 10*4882a593Smuzhiyun */ 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun/dts-v1/; 13*4882a593Smuzhiyun 14*4882a593Smuzhiyun#include <dt-bindings/input/input.h> 15*4882a593Smuzhiyun#include <dt-bindings/gpio/gpio.h> 16*4882a593Smuzhiyun#include "armada-370.dtsi" 17*4882a593Smuzhiyun 18*4882a593Smuzhiyun/ { 19*4882a593Smuzhiyun model = "D-Link DNS-327L"; 20*4882a593Smuzhiyun compatible = "dlink,dns327l", 21*4882a593Smuzhiyun "marvell,armada370", 22*4882a593Smuzhiyun "marvell,armada-370-xp"; 23*4882a593Smuzhiyun 24*4882a593Smuzhiyun chosen { 25*4882a593Smuzhiyun stdout-path = &uart0; 26*4882a593Smuzhiyun }; 27*4882a593Smuzhiyun 28*4882a593Smuzhiyun memory@0 { 29*4882a593Smuzhiyun device_type = "memory"; 30*4882a593Smuzhiyun reg = <0x00000000 0x20000000>; /* 512 MiB */ 31*4882a593Smuzhiyun }; 32*4882a593Smuzhiyun 33*4882a593Smuzhiyun soc { 34*4882a593Smuzhiyun ranges = <MBUS_ID(0xf0, 0x01) 0 0xd0000000 0x100000 35*4882a593Smuzhiyun MBUS_ID(0x01, 0xe0) 0 0xfff00000 0x100000 36*4882a593Smuzhiyun MBUS_ID(0x09, 0x01) 0 0xf1100000 0x10000>; 37*4882a593Smuzhiyun 38*4882a593Smuzhiyun internal-regs { 39*4882a593Smuzhiyun sata@a0000 { 40*4882a593Smuzhiyun nr-ports = <2>; 41*4882a593Smuzhiyun status = "okay"; 42*4882a593Smuzhiyun }; 43*4882a593Smuzhiyun 44*4882a593Smuzhiyun usb@50000 { 45*4882a593Smuzhiyun status = "okay"; 46*4882a593Smuzhiyun }; 47*4882a593Smuzhiyun }; 48*4882a593Smuzhiyun }; 49*4882a593Smuzhiyun 50*4882a593Smuzhiyun gpio-keys { 51*4882a593Smuzhiyun compatible = "gpio-keys"; 52*4882a593Smuzhiyun pinctrl-0 = < 53*4882a593Smuzhiyun &backup_button_pin 54*4882a593Smuzhiyun &power_button_pin 55*4882a593Smuzhiyun &reset_button_pin>; 56*4882a593Smuzhiyun pinctrl-names = "default"; 57*4882a593Smuzhiyun 58*4882a593Smuzhiyun power-button { 59*4882a593Smuzhiyun label = "Power Button"; 60*4882a593Smuzhiyun linux,code = <KEY_POWER>; 61*4882a593Smuzhiyun gpios = <&gpio2 1 GPIO_ACTIVE_LOW>; 62*4882a593Smuzhiyun }; 63*4882a593Smuzhiyun 64*4882a593Smuzhiyun backup-button { 65*4882a593Smuzhiyun label = "Backup Button"; 66*4882a593Smuzhiyun linux,code = <KEY_COPY>; 67*4882a593Smuzhiyun gpios = <&gpio1 31 GPIO_ACTIVE_LOW>; 68*4882a593Smuzhiyun }; 69*4882a593Smuzhiyun 70*4882a593Smuzhiyun reset-button { 71*4882a593Smuzhiyun label = "Reset Button"; 72*4882a593Smuzhiyun linux,code = <KEY_RESTART>; 73*4882a593Smuzhiyun gpios = <&gpio2 0 GPIO_ACTIVE_LOW>; 74*4882a593Smuzhiyun }; 75*4882a593Smuzhiyun }; 76*4882a593Smuzhiyun 77*4882a593Smuzhiyun gpio-leds { 78*4882a593Smuzhiyun compatible = "gpio-leds"; 79*4882a593Smuzhiyun pinctrl-0 = < 80*4882a593Smuzhiyun &sata_l_amber_pin 81*4882a593Smuzhiyun &sata_r_amber_pin 82*4882a593Smuzhiyun &backup_led_pin 83*4882a593Smuzhiyun /* Ensure these are managed by hardware */ 84*4882a593Smuzhiyun &sata_l_white_pin 85*4882a593Smuzhiyun &sata_r_white_pin>; 86*4882a593Smuzhiyun 87*4882a593Smuzhiyun pinctrl-names = "default"; 88*4882a593Smuzhiyun 89*4882a593Smuzhiyun sata-r-amber-pin { 90*4882a593Smuzhiyun label = "dns327l:amber:sata-r"; 91*4882a593Smuzhiyun gpios = <&gpio1 20 GPIO_ACTIVE_HIGH>; 92*4882a593Smuzhiyun default-state = "keep"; 93*4882a593Smuzhiyun }; 94*4882a593Smuzhiyun 95*4882a593Smuzhiyun sata-l-amber-pin { 96*4882a593Smuzhiyun label = "dns327l:amber:sata-l"; 97*4882a593Smuzhiyun gpios = <&gpio1 21 GPIO_ACTIVE_HIGH>; 98*4882a593Smuzhiyun default-state = "keep"; 99*4882a593Smuzhiyun }; 100*4882a593Smuzhiyun 101*4882a593Smuzhiyun backup-led-pin { 102*4882a593Smuzhiyun label = "dns327l:white:usb"; 103*4882a593Smuzhiyun gpios = <&gpio1 29 GPIO_ACTIVE_HIGH>; 104*4882a593Smuzhiyun default-state = "keep"; 105*4882a593Smuzhiyun }; 106*4882a593Smuzhiyun }; 107*4882a593Smuzhiyun 108*4882a593Smuzhiyun regulators { 109*4882a593Smuzhiyun compatible = "simple-bus"; 110*4882a593Smuzhiyun #address-cells = <1>; 111*4882a593Smuzhiyun #size-cells = <0>; 112*4882a593Smuzhiyun 113*4882a593Smuzhiyun usb_power: regulator@1 { 114*4882a593Smuzhiyun compatible = "regulator-fixed"; 115*4882a593Smuzhiyun reg = <1>; 116*4882a593Smuzhiyun pinctrl-0 = <&xhci_pwr_pin>; 117*4882a593Smuzhiyun pinctrl-names = "default"; 118*4882a593Smuzhiyun regulator-name = "USB3.0 Port Power"; 119*4882a593Smuzhiyun regulator-min-microvolt = <5000000>; 120*4882a593Smuzhiyun regulator-max-microvolt = <5000000>; 121*4882a593Smuzhiyun enable-active-high; 122*4882a593Smuzhiyun regulator-boot-on; 123*4882a593Smuzhiyun regulator-always-on; 124*4882a593Smuzhiyun gpio = <&gpio0 13 GPIO_ACTIVE_HIGH>; 125*4882a593Smuzhiyun }; 126*4882a593Smuzhiyun 127*4882a593Smuzhiyun sata_r_power: regulator@2 { 128*4882a593Smuzhiyun compatible = "regulator-fixed"; 129*4882a593Smuzhiyun reg = <2>; 130*4882a593Smuzhiyun pinctrl-0 = <&sata_r_pwr_pin>; 131*4882a593Smuzhiyun pinctrl-names = "default"; 132*4882a593Smuzhiyun regulator-name = "SATA-R Power"; 133*4882a593Smuzhiyun regulator-min-microvolt = <5000000>; 134*4882a593Smuzhiyun regulator-max-microvolt = <5000000>; 135*4882a593Smuzhiyun startup-delay-us = <2000000>; 136*4882a593Smuzhiyun enable-active-high; 137*4882a593Smuzhiyun regulator-always-on; 138*4882a593Smuzhiyun regulator-boot-on; 139*4882a593Smuzhiyun gpio = <&gpio1 22 GPIO_ACTIVE_HIGH>; 140*4882a593Smuzhiyun }; 141*4882a593Smuzhiyun 142*4882a593Smuzhiyun sata_l_power: regulator@3 { 143*4882a593Smuzhiyun compatible = "regulator-fixed"; 144*4882a593Smuzhiyun reg = <3>; 145*4882a593Smuzhiyun pinctrl-0 = <&sata_l_pwr_pin>; 146*4882a593Smuzhiyun pinctrl-names = "default"; 147*4882a593Smuzhiyun regulator-name = "SATA-L Power"; 148*4882a593Smuzhiyun regulator-min-microvolt = <5000000>; 149*4882a593Smuzhiyun regulator-max-microvolt = <5000000>; 150*4882a593Smuzhiyun startup-delay-us = <4000000>; 151*4882a593Smuzhiyun enable-active-high; 152*4882a593Smuzhiyun regulator-always-on; 153*4882a593Smuzhiyun regulator-boot-on; 154*4882a593Smuzhiyun gpio = <&gpio1 24 GPIO_ACTIVE_HIGH>; 155*4882a593Smuzhiyun }; 156*4882a593Smuzhiyun }; 157*4882a593Smuzhiyun}; 158*4882a593Smuzhiyun 159*4882a593Smuzhiyun&pciec { 160*4882a593Smuzhiyun status = "okay"; 161*4882a593Smuzhiyun 162*4882a593Smuzhiyun pcie@1,0 { 163*4882a593Smuzhiyun /* Port 0, Lane 0 */ 164*4882a593Smuzhiyun status = "okay"; 165*4882a593Smuzhiyun }; 166*4882a593Smuzhiyun 167*4882a593Smuzhiyun pcie@2,0 { 168*4882a593Smuzhiyun /* Port 1, Lane 0 */ 169*4882a593Smuzhiyun status = "okay"; 170*4882a593Smuzhiyun }; 171*4882a593Smuzhiyun}; 172*4882a593Smuzhiyun 173*4882a593Smuzhiyun&pinctrl { 174*4882a593Smuzhiyun sata_l_white_pin: sata-l-white-pin { 175*4882a593Smuzhiyun marvell,pins = "mpp57"; 176*4882a593Smuzhiyun marvell,function = "sata0"; 177*4882a593Smuzhiyun }; 178*4882a593Smuzhiyun 179*4882a593Smuzhiyun sata_r_white_pin: sata-r-white-pin { 180*4882a593Smuzhiyun marvell,pins = "mpp55"; 181*4882a593Smuzhiyun marvell,function = "sata1"; 182*4882a593Smuzhiyun }; 183*4882a593Smuzhiyun 184*4882a593Smuzhiyun sata_r_amber_pin: sata-r-amber-pin { 185*4882a593Smuzhiyun marvell,pins = "mpp52"; 186*4882a593Smuzhiyun marvell,function = "gpio"; 187*4882a593Smuzhiyun }; 188*4882a593Smuzhiyun 189*4882a593Smuzhiyun sata_l_amber_pin: sata-l-amber-pin { 190*4882a593Smuzhiyun marvell,pins = "mpp53"; 191*4882a593Smuzhiyun marvell,function = "gpio"; 192*4882a593Smuzhiyun }; 193*4882a593Smuzhiyun 194*4882a593Smuzhiyun backup_led_pin: backup-led-pin { 195*4882a593Smuzhiyun marvell,pins = "mpp61"; 196*4882a593Smuzhiyun marvell,function = "gpo"; 197*4882a593Smuzhiyun }; 198*4882a593Smuzhiyun 199*4882a593Smuzhiyun xhci_pwr_pin: xhci-pwr-pin { 200*4882a593Smuzhiyun marvell,pins = "mpp13"; 201*4882a593Smuzhiyun marvell,function = "gpio"; 202*4882a593Smuzhiyun }; 203*4882a593Smuzhiyun 204*4882a593Smuzhiyun sata_r_pwr_pin: sata-r-pwr-pin { 205*4882a593Smuzhiyun marvell,pins = "mpp54"; 206*4882a593Smuzhiyun marvell,function = "gpio"; 207*4882a593Smuzhiyun }; 208*4882a593Smuzhiyun 209*4882a593Smuzhiyun sata_l_pwr_pin: sata-l-pwr-pin { 210*4882a593Smuzhiyun marvell,pins = "mpp56"; 211*4882a593Smuzhiyun marvell,function = "gpio"; 212*4882a593Smuzhiyun }; 213*4882a593Smuzhiyun 214*4882a593Smuzhiyun uart1_pins: uart1-pins { 215*4882a593Smuzhiyun marvell,pins = "mpp60", "mpp61"; 216*4882a593Smuzhiyun marvell,function = "uart1"; 217*4882a593Smuzhiyun }; 218*4882a593Smuzhiyun 219*4882a593Smuzhiyun power_button_pin: power-button-pin { 220*4882a593Smuzhiyun marvell,pins = "mpp65"; 221*4882a593Smuzhiyun marvell,function = "gpio"; 222*4882a593Smuzhiyun }; 223*4882a593Smuzhiyun 224*4882a593Smuzhiyun backup_button_pin: backup-button-pin { 225*4882a593Smuzhiyun marvell,pins = "mpp63"; 226*4882a593Smuzhiyun marvell,function = "gpio"; 227*4882a593Smuzhiyun }; 228*4882a593Smuzhiyun 229*4882a593Smuzhiyun reset_button_pin: reset-button-pin { 230*4882a593Smuzhiyun marvell,pins = "mpp64"; 231*4882a593Smuzhiyun marvell,function = "gpio"; 232*4882a593Smuzhiyun }; 233*4882a593Smuzhiyun}; 234*4882a593Smuzhiyun 235*4882a593Smuzhiyun/* Serial console */ 236*4882a593Smuzhiyun&uart0 { 237*4882a593Smuzhiyun status = "okay"; 238*4882a593Smuzhiyun}; 239*4882a593Smuzhiyun 240*4882a593Smuzhiyun/* Connected to Weltrend MCU */ 241*4882a593Smuzhiyun&uart1 { 242*4882a593Smuzhiyun pinctrl-0 = <&uart1_pins>; 243*4882a593Smuzhiyun pinctrl-names = "default"; 244*4882a593Smuzhiyun status = "okay"; 245*4882a593Smuzhiyun}; 246*4882a593Smuzhiyun 247*4882a593Smuzhiyun&mdio { 248*4882a593Smuzhiyun phy0: ethernet-phy@0 { /* Marvell 88E1318 */ 249*4882a593Smuzhiyun reg = <0>; 250*4882a593Smuzhiyun marvell,reg-init = <0x2 0x19 0x0 0x0077>, 251*4882a593Smuzhiyun <0x2 0x18 0x0 0x5747>; 252*4882a593Smuzhiyun }; 253*4882a593Smuzhiyun}; 254*4882a593Smuzhiyun 255*4882a593Smuzhiyunð1 { 256*4882a593Smuzhiyun phy = <&phy0>; 257*4882a593Smuzhiyun phy-mode = "rgmii-id"; 258*4882a593Smuzhiyun status = "okay"; 259*4882a593Smuzhiyun}; 260*4882a593Smuzhiyun 261*4882a593Smuzhiyun&i2c0 { 262*4882a593Smuzhiyun compatible = "marvell,mv64xxx-i2c"; 263*4882a593Smuzhiyun clock-frequency = <100000>; 264*4882a593Smuzhiyun status = "okay"; 265*4882a593Smuzhiyun}; 266*4882a593Smuzhiyun 267*4882a593Smuzhiyun&nand_controller { 268*4882a593Smuzhiyun status = "okay"; 269*4882a593Smuzhiyun 270*4882a593Smuzhiyun nand@0 { 271*4882a593Smuzhiyun reg = <0>; 272*4882a593Smuzhiyun label = "pxa3xx_nand-0"; 273*4882a593Smuzhiyun nand-rb = <0>; 274*4882a593Smuzhiyun marvell,nand-keep-config; 275*4882a593Smuzhiyun nand-on-flash-bbt; 276*4882a593Smuzhiyun nand-ecc-strength = <4>; 277*4882a593Smuzhiyun nand-ecc-step-size = <512>; 278*4882a593Smuzhiyun 279*4882a593Smuzhiyun partitions { 280*4882a593Smuzhiyun compatible = "fixed-partitions"; 281*4882a593Smuzhiyun #address-cells = <1>; 282*4882a593Smuzhiyun #size-cells = <1>; 283*4882a593Smuzhiyun 284*4882a593Smuzhiyun partition@0 { 285*4882a593Smuzhiyun label = "u-boot"; 286*4882a593Smuzhiyun /* 1.0 MiB */ 287*4882a593Smuzhiyun reg = <0x0000000 0x100000>; 288*4882a593Smuzhiyun read-only; 289*4882a593Smuzhiyun }; 290*4882a593Smuzhiyun 291*4882a593Smuzhiyun partition@100000 { 292*4882a593Smuzhiyun label = "u-boot-env"; 293*4882a593Smuzhiyun /* 128 KiB */ 294*4882a593Smuzhiyun reg = <0x100000 0x20000>; 295*4882a593Smuzhiyun read-only; 296*4882a593Smuzhiyun }; 297*4882a593Smuzhiyun 298*4882a593Smuzhiyun partition@120000 { 299*4882a593Smuzhiyun label = "uImage"; 300*4882a593Smuzhiyun /* 7 MiB */ 301*4882a593Smuzhiyun reg = <0x120000 0x700000>; 302*4882a593Smuzhiyun }; 303*4882a593Smuzhiyun 304*4882a593Smuzhiyun partition@820000 { 305*4882a593Smuzhiyun label = "ubifs"; 306*4882a593Smuzhiyun /* ~ 84 MiB */ 307*4882a593Smuzhiyun reg = <0x820000 0x54e0000>; 308*4882a593Smuzhiyun }; 309*4882a593Smuzhiyun 310*4882a593Smuzhiyun /* Hardcoded into stock bootloader */ 311*4882a593Smuzhiyun partition@5d00000 { 312*4882a593Smuzhiyun label = "failsafe-uImage"; 313*4882a593Smuzhiyun /* 5 MiB */ 314*4882a593Smuzhiyun reg = <0x5d00000 0x500000>; 315*4882a593Smuzhiyun }; 316*4882a593Smuzhiyun 317*4882a593Smuzhiyun partition@6200000 { 318*4882a593Smuzhiyun label = "failsafe-fs"; 319*4882a593Smuzhiyun /* 29 MiB */ 320*4882a593Smuzhiyun reg = <0x6200000 0x1d00000>; 321*4882a593Smuzhiyun }; 322*4882a593Smuzhiyun 323*4882a593Smuzhiyun partition@7f00000 { 324*4882a593Smuzhiyun label = "bbt"; 325*4882a593Smuzhiyun /* 1 MiB for BBT */ 326*4882a593Smuzhiyun reg = <0x7f00000 0x100000>; 327*4882a593Smuzhiyun }; 328*4882a593Smuzhiyun }; 329*4882a593Smuzhiyun }; 330*4882a593Smuzhiyun}; 331