1*4882a593Smuzhiyun/* 2*4882a593Smuzhiyun * Copyright 2016 Linaro Ltd 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * Permission is hereby granted, free of charge, to any person obtaining a copy 5*4882a593Smuzhiyun * of this software and associated documentation files (the "Software"), to deal 6*4882a593Smuzhiyun * in the Software without restriction, including without limitation the rights 7*4882a593Smuzhiyun * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 8*4882a593Smuzhiyun * copies of the Software, and to permit persons to whom the Software is 9*4882a593Smuzhiyun * furnished to do so, subject to the following conditions: 10*4882a593Smuzhiyun * 11*4882a593Smuzhiyun * The above copyright notice and this permission notice shall be included in 12*4882a593Smuzhiyun * all copies or substantial portions of the Software. 13*4882a593Smuzhiyun * 14*4882a593Smuzhiyun * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15*4882a593Smuzhiyun * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16*4882a593Smuzhiyun * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17*4882a593Smuzhiyun * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 18*4882a593Smuzhiyun * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 19*4882a593Smuzhiyun * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 20*4882a593Smuzhiyun * THE SOFTWARE. 21*4882a593Smuzhiyun */ 22*4882a593Smuzhiyun 23*4882a593Smuzhiyun/dts-v1/; 24*4882a593Smuzhiyun#include "arm-realview-pbx.dtsi" 25*4882a593Smuzhiyun 26*4882a593Smuzhiyun/ { 27*4882a593Smuzhiyun model = "ARM RealView Platform Baseboard for Cortex-A8"; 28*4882a593Smuzhiyun compatible = "arm,realview-pba8"; 29*4882a593Smuzhiyun arm,hbi = <0x178>; 30*4882a593Smuzhiyun 31*4882a593Smuzhiyun cpus { 32*4882a593Smuzhiyun #address-cells = <1>; 33*4882a593Smuzhiyun #size-cells = <0>; 34*4882a593Smuzhiyun enable-method = "arm,realview-smp"; 35*4882a593Smuzhiyun 36*4882a593Smuzhiyun cpu0: cpu@0 { 37*4882a593Smuzhiyun device_type = "cpu"; 38*4882a593Smuzhiyun compatible = "arm,cortex-a8"; 39*4882a593Smuzhiyun reg = <0>; 40*4882a593Smuzhiyun }; 41*4882a593Smuzhiyun }; 42*4882a593Smuzhiyun 43*4882a593Smuzhiyun pmu: pmu@0 { 44*4882a593Smuzhiyun compatible = "arm,cortex-a8-pmu"; 45*4882a593Smuzhiyun interrupt-parent = <&intc>; 46*4882a593Smuzhiyun interrupts = <0 47 IRQ_TYPE_LEVEL_HIGH>; 47*4882a593Smuzhiyun interrupt-affinity = <&cpu0>; 48*4882a593Smuzhiyun }; 49*4882a593Smuzhiyun 50*4882a593Smuzhiyun /* Primary GIC PL390 interrupt controller in the test chip */ 51*4882a593Smuzhiyun intc: interrupt-controller@1e000000 { 52*4882a593Smuzhiyun compatible = "arm,pl390"; 53*4882a593Smuzhiyun #interrupt-cells = <3>; 54*4882a593Smuzhiyun #address-cells = <1>; 55*4882a593Smuzhiyun interrupt-controller; 56*4882a593Smuzhiyun reg = <0x1e001000 0x1000>, 57*4882a593Smuzhiyun <0x1e000000 0x100>; 58*4882a593Smuzhiyun }; 59*4882a593Smuzhiyun}; 60*4882a593Smuzhiyun 61*4882a593Smuzhiyunðernet { 62*4882a593Smuzhiyun interrupt-parent = <&intc>; 63*4882a593Smuzhiyun interrupts = <0 28 IRQ_TYPE_LEVEL_HIGH>; 64*4882a593Smuzhiyun}; 65*4882a593Smuzhiyun 66*4882a593Smuzhiyun&usb { 67*4882a593Smuzhiyun interrupt-parent = <&intc>; 68*4882a593Smuzhiyun interrupts = <0 29 IRQ_TYPE_LEVEL_HIGH>; 69*4882a593Smuzhiyun}; 70*4882a593Smuzhiyun 71*4882a593Smuzhiyun&soc { 72*4882a593Smuzhiyun compatible = "arm,realview-pba8-soc", "simple-bus"; 73*4882a593Smuzhiyun}; 74*4882a593Smuzhiyun 75*4882a593Smuzhiyun&syscon { 76*4882a593Smuzhiyun compatible = "arm,realview-pba8-syscon", "syscon", "simple-mfd"; 77*4882a593Smuzhiyun}; 78*4882a593Smuzhiyun 79*4882a593Smuzhiyun&serial0 { 80*4882a593Smuzhiyun interrupt-parent = <&intc>; 81*4882a593Smuzhiyun interrupts = <0 12 IRQ_TYPE_LEVEL_HIGH>; 82*4882a593Smuzhiyun}; 83*4882a593Smuzhiyun 84*4882a593Smuzhiyun&serial1 { 85*4882a593Smuzhiyun interrupt-parent = <&intc>; 86*4882a593Smuzhiyun interrupts = <0 13 IRQ_TYPE_LEVEL_HIGH>; 87*4882a593Smuzhiyun}; 88*4882a593Smuzhiyun 89*4882a593Smuzhiyun&serial2 { 90*4882a593Smuzhiyun interrupt-parent = <&intc>; 91*4882a593Smuzhiyun interrupts = <0 14 IRQ_TYPE_LEVEL_HIGH>; 92*4882a593Smuzhiyun}; 93*4882a593Smuzhiyun 94*4882a593Smuzhiyun&serial3 { 95*4882a593Smuzhiyun interrupt-parent = <&intc>; 96*4882a593Smuzhiyun interrupts = <0 15 IRQ_TYPE_LEVEL_HIGH>; 97*4882a593Smuzhiyun}; 98*4882a593Smuzhiyun 99*4882a593Smuzhiyun&ssp { 100*4882a593Smuzhiyun interrupt-parent = <&intc>; 101*4882a593Smuzhiyun interrupts = <0 11 IRQ_TYPE_LEVEL_HIGH>; 102*4882a593Smuzhiyun}; 103*4882a593Smuzhiyun 104*4882a593Smuzhiyun&wdog0 { 105*4882a593Smuzhiyun interrupt-parent = <&intc>; 106*4882a593Smuzhiyun interrupts = <0 0 IRQ_TYPE_LEVEL_HIGH>; 107*4882a593Smuzhiyun}; 108*4882a593Smuzhiyun 109*4882a593Smuzhiyun&wdog1 { 110*4882a593Smuzhiyun interrupt-parent = <&intc>; 111*4882a593Smuzhiyun interrupts = <0 40 IRQ_TYPE_LEVEL_HIGH>; 112*4882a593Smuzhiyun}; 113*4882a593Smuzhiyun 114*4882a593Smuzhiyun&timer01 { 115*4882a593Smuzhiyun interrupt-parent = <&intc>; 116*4882a593Smuzhiyun interrupts = <0 4 IRQ_TYPE_LEVEL_HIGH>; 117*4882a593Smuzhiyun}; 118*4882a593Smuzhiyun 119*4882a593Smuzhiyun&timer23 { 120*4882a593Smuzhiyun interrupt-parent = <&intc>; 121*4882a593Smuzhiyun interrupts = <0 5 IRQ_TYPE_LEVEL_HIGH>; 122*4882a593Smuzhiyun}; 123*4882a593Smuzhiyun 124*4882a593Smuzhiyun&gpio0 { 125*4882a593Smuzhiyun interrupt-parent = <&intc>; 126*4882a593Smuzhiyun interrupts = <0 6 IRQ_TYPE_LEVEL_HIGH>; 127*4882a593Smuzhiyun}; 128*4882a593Smuzhiyun 129*4882a593Smuzhiyun&gpio1 { 130*4882a593Smuzhiyun interrupt-parent = <&intc>; 131*4882a593Smuzhiyun interrupts = <0 7 IRQ_TYPE_LEVEL_HIGH>; 132*4882a593Smuzhiyun}; 133*4882a593Smuzhiyun 134*4882a593Smuzhiyun&gpio2 { 135*4882a593Smuzhiyun interrupt-parent = <&intc>; 136*4882a593Smuzhiyun interrupts = <0 8 IRQ_TYPE_LEVEL_HIGH>; 137*4882a593Smuzhiyun}; 138*4882a593Smuzhiyun 139*4882a593Smuzhiyun&rtc { 140*4882a593Smuzhiyun interrupt-parent = <&intc>; 141*4882a593Smuzhiyun interrupts = <0 10 IRQ_TYPE_LEVEL_HIGH>; 142*4882a593Smuzhiyun}; 143*4882a593Smuzhiyun 144*4882a593Smuzhiyun&timer45 { 145*4882a593Smuzhiyun interrupt-parent = <&intc>; 146*4882a593Smuzhiyun interrupts = <0 41 IRQ_TYPE_LEVEL_HIGH>; 147*4882a593Smuzhiyun}; 148*4882a593Smuzhiyun 149*4882a593Smuzhiyun&timer67 { 150*4882a593Smuzhiyun interrupt-parent = <&intc>; 151*4882a593Smuzhiyun interrupts = <0 42 IRQ_TYPE_LEVEL_HIGH>; 152*4882a593Smuzhiyun}; 153*4882a593Smuzhiyun 154*4882a593Smuzhiyun&aaci { 155*4882a593Smuzhiyun interrupt-parent = <&intc>; 156*4882a593Smuzhiyun interrupts = <0 19 IRQ_TYPE_LEVEL_HIGH>; 157*4882a593Smuzhiyun}; 158*4882a593Smuzhiyun 159*4882a593Smuzhiyun&mmc { 160*4882a593Smuzhiyun interrupt-parent = <&intc>; 161*4882a593Smuzhiyun interrupts = <0 17 IRQ_TYPE_LEVEL_HIGH>, 162*4882a593Smuzhiyun <0 18 IRQ_TYPE_LEVEL_HIGH>; 163*4882a593Smuzhiyun}; 164*4882a593Smuzhiyun 165*4882a593Smuzhiyun&kmi0 { 166*4882a593Smuzhiyun interrupt-parent = <&intc>; 167*4882a593Smuzhiyun interrupts = <0 20 IRQ_TYPE_LEVEL_HIGH>; 168*4882a593Smuzhiyun}; 169*4882a593Smuzhiyun 170*4882a593Smuzhiyun&kmi1 { 171*4882a593Smuzhiyun interrupt-parent = <&intc>; 172*4882a593Smuzhiyun interrupts = <0 21 IRQ_TYPE_LEVEL_HIGH>; 173*4882a593Smuzhiyun}; 174*4882a593Smuzhiyun 175*4882a593Smuzhiyun&clcd { 176*4882a593Smuzhiyun interrupt-parent = <&intc>; 177*4882a593Smuzhiyun interrupts = <0 23 IRQ_TYPE_LEVEL_HIGH>; 178*4882a593Smuzhiyun}; 179