1*4882a593Smuzhiyun// SPDX-License-Identifier: GPL-2.0-only 2*4882a593Smuzhiyun/* 3*4882a593Smuzhiyun * Copyright (C) 2013 Texas Instruments Incorporated - https://www.ti.com/ 4*4882a593Smuzhiyun */ 5*4882a593Smuzhiyun 6*4882a593Smuzhiyun/* AM43x EPOS EVM */ 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun/dts-v1/; 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun#include "am4372.dtsi" 11*4882a593Smuzhiyun#include <dt-bindings/pinctrl/am43xx.h> 12*4882a593Smuzhiyun#include <dt-bindings/gpio/gpio.h> 13*4882a593Smuzhiyun#include <dt-bindings/pwm/pwm.h> 14*4882a593Smuzhiyun#include <dt-bindings/sound/tlv320aic31xx-micbias.h> 15*4882a593Smuzhiyun 16*4882a593Smuzhiyun/ { 17*4882a593Smuzhiyun model = "TI AM43x EPOS EVM"; 18*4882a593Smuzhiyun compatible = "ti,am43x-epos-evm","ti,am438x","ti,am43"; 19*4882a593Smuzhiyun 20*4882a593Smuzhiyun aliases { 21*4882a593Smuzhiyun display0 = &lcd0; 22*4882a593Smuzhiyun }; 23*4882a593Smuzhiyun 24*4882a593Smuzhiyun chosen { 25*4882a593Smuzhiyun stdout-path = &uart0; 26*4882a593Smuzhiyun }; 27*4882a593Smuzhiyun 28*4882a593Smuzhiyun vmmcsd_fixed: fixedregulator-sd { 29*4882a593Smuzhiyun compatible = "regulator-fixed"; 30*4882a593Smuzhiyun regulator-name = "vmmcsd_fixed"; 31*4882a593Smuzhiyun regulator-min-microvolt = <3300000>; 32*4882a593Smuzhiyun regulator-max-microvolt = <3300000>; 33*4882a593Smuzhiyun enable-active-high; 34*4882a593Smuzhiyun }; 35*4882a593Smuzhiyun 36*4882a593Smuzhiyun vbat: fixedregulator0 { 37*4882a593Smuzhiyun compatible = "regulator-fixed"; 38*4882a593Smuzhiyun regulator-name = "vbat"; 39*4882a593Smuzhiyun regulator-min-microvolt = <5000000>; 40*4882a593Smuzhiyun regulator-max-microvolt = <5000000>; 41*4882a593Smuzhiyun regulator-boot-on; 42*4882a593Smuzhiyun }; 43*4882a593Smuzhiyun 44*4882a593Smuzhiyun lcd0: display { 45*4882a593Smuzhiyun compatible = "osddisplays,osd070t1718-19ts", "panel-dpi"; 46*4882a593Smuzhiyun label = "lcd"; 47*4882a593Smuzhiyun 48*4882a593Smuzhiyun backlight = <&lcd_bl>; 49*4882a593Smuzhiyun 50*4882a593Smuzhiyun port { 51*4882a593Smuzhiyun lcd_in: endpoint { 52*4882a593Smuzhiyun remote-endpoint = <&dpi_out>; 53*4882a593Smuzhiyun }; 54*4882a593Smuzhiyun }; 55*4882a593Smuzhiyun }; 56*4882a593Smuzhiyun 57*4882a593Smuzhiyun matrix_keypad: matrix_keypad0 { 58*4882a593Smuzhiyun compatible = "gpio-matrix-keypad"; 59*4882a593Smuzhiyun debounce-delay-ms = <5>; 60*4882a593Smuzhiyun col-scan-delay-us = <2>; 61*4882a593Smuzhiyun pinctrl-names = "default", "sleep"; 62*4882a593Smuzhiyun pinctrl-0 = <&matrix_keypad_default>; 63*4882a593Smuzhiyun pinctrl-1 = <&matrix_keypad_sleep>; 64*4882a593Smuzhiyun wakeup-source; 65*4882a593Smuzhiyun 66*4882a593Smuzhiyun row-gpios = <&gpio0 12 GPIO_ACTIVE_HIGH /* Bank0, pin12 */ 67*4882a593Smuzhiyun &gpio0 13 GPIO_ACTIVE_HIGH /* Bank0, pin13 */ 68*4882a593Smuzhiyun &gpio0 14 GPIO_ACTIVE_HIGH /* Bank0, pin14 */ 69*4882a593Smuzhiyun &gpio0 15 GPIO_ACTIVE_HIGH>; /* Bank0, pin15 */ 70*4882a593Smuzhiyun 71*4882a593Smuzhiyun col-gpios = <&gpio3 9 GPIO_ACTIVE_HIGH /* Bank3, pin9 */ 72*4882a593Smuzhiyun &gpio3 10 GPIO_ACTIVE_HIGH /* Bank3, pin10 */ 73*4882a593Smuzhiyun &gpio2 18 GPIO_ACTIVE_HIGH /* Bank2, pin18 */ 74*4882a593Smuzhiyun &gpio2 19 GPIO_ACTIVE_HIGH>; /* Bank2, pin19 */ 75*4882a593Smuzhiyun 76*4882a593Smuzhiyun linux,keymap = <0x00000201 /* P1 */ 77*4882a593Smuzhiyun 0x01000204 /* P4 */ 78*4882a593Smuzhiyun 0x02000207 /* P7 */ 79*4882a593Smuzhiyun 0x0300020a /* NUMERIC_STAR */ 80*4882a593Smuzhiyun 0x00010202 /* P2 */ 81*4882a593Smuzhiyun 0x01010205 /* P5 */ 82*4882a593Smuzhiyun 0x02010208 /* P8 */ 83*4882a593Smuzhiyun 0x03010200 /* P0 */ 84*4882a593Smuzhiyun 0x00020203 /* P3 */ 85*4882a593Smuzhiyun 0x01020206 /* P6 */ 86*4882a593Smuzhiyun 0x02020209 /* P9 */ 87*4882a593Smuzhiyun 0x0302020b /* NUMERIC_POUND */ 88*4882a593Smuzhiyun 0x00030067 /* UP */ 89*4882a593Smuzhiyun 0x0103006a /* RIGHT */ 90*4882a593Smuzhiyun 0x0203006c /* DOWN */ 91*4882a593Smuzhiyun 0x03030069>; /* LEFT */ 92*4882a593Smuzhiyun }; 93*4882a593Smuzhiyun 94*4882a593Smuzhiyun lcd_bl: backlight { 95*4882a593Smuzhiyun compatible = "pwm-backlight"; 96*4882a593Smuzhiyun pwms = <&ecap0 0 50000 PWM_POLARITY_INVERTED>; 97*4882a593Smuzhiyun brightness-levels = <0 51 53 56 62 75 101 152 255>; 98*4882a593Smuzhiyun default-brightness-level = <8>; 99*4882a593Smuzhiyun }; 100*4882a593Smuzhiyun 101*4882a593Smuzhiyun sound0: sound0 { 102*4882a593Smuzhiyun compatible = "simple-audio-card"; 103*4882a593Smuzhiyun simple-audio-card,name = "AM43-EPOS-EVM"; 104*4882a593Smuzhiyun simple-audio-card,widgets = 105*4882a593Smuzhiyun "Microphone", "Microphone Jack", 106*4882a593Smuzhiyun "Headphone", "Headphone Jack", 107*4882a593Smuzhiyun "Speaker", "Speaker"; 108*4882a593Smuzhiyun simple-audio-card,routing = 109*4882a593Smuzhiyun "MIC1LP", "Microphone Jack", 110*4882a593Smuzhiyun "MIC1RP", "Microphone Jack", 111*4882a593Smuzhiyun "MIC1LP", "MICBIAS", 112*4882a593Smuzhiyun "MIC1RP", "MICBIAS", 113*4882a593Smuzhiyun "Headphone Jack", "HPL", 114*4882a593Smuzhiyun "Headphone Jack", "HPR", 115*4882a593Smuzhiyun "Speaker", "SPL", 116*4882a593Smuzhiyun "Speaker", "SPR"; 117*4882a593Smuzhiyun simple-audio-card,format = "dsp_b"; 118*4882a593Smuzhiyun simple-audio-card,bitclock-master = <&sound0_master>; 119*4882a593Smuzhiyun simple-audio-card,frame-master = <&sound0_master>; 120*4882a593Smuzhiyun simple-audio-card,bitclock-inversion; 121*4882a593Smuzhiyun 122*4882a593Smuzhiyun simple-audio-card,cpu { 123*4882a593Smuzhiyun sound-dai = <&mcasp1>; 124*4882a593Smuzhiyun system-clock-frequency = <12000000>; 125*4882a593Smuzhiyun }; 126*4882a593Smuzhiyun 127*4882a593Smuzhiyun sound0_master: simple-audio-card,codec { 128*4882a593Smuzhiyun sound-dai = <&tlv320aic3111>; 129*4882a593Smuzhiyun system-clock-frequency = <12000000>; 130*4882a593Smuzhiyun }; 131*4882a593Smuzhiyun }; 132*4882a593Smuzhiyun 133*4882a593Smuzhiyun audio_mstrclk: clock { 134*4882a593Smuzhiyun compatible = "fixed-clock"; 135*4882a593Smuzhiyun #clock-cells = <0>; 136*4882a593Smuzhiyun clock-frequency = <12000000>; 137*4882a593Smuzhiyun }; 138*4882a593Smuzhiyun}; 139*4882a593Smuzhiyun 140*4882a593Smuzhiyun&am43xx_pinmux { 141*4882a593Smuzhiyun pinctrl-names = "default"; 142*4882a593Smuzhiyun pinctrl-0 = <&unused_pins>; 143*4882a593Smuzhiyun 144*4882a593Smuzhiyun unused_pins: unused_pins { 145*4882a593Smuzhiyun pinctrl-single,pins = < 146*4882a593Smuzhiyun AM4372_IOPAD(0x848, DS0_PIN_OUTPUT_PULLUP | PIN_OUTPUT_PULLUP | MUX_MODE7) 147*4882a593Smuzhiyun AM4372_IOPAD(0x850, DS0_PIN_INPUT | PIN_INPUT_PULLDOWN | MUX_MODE7) 148*4882a593Smuzhiyun AM4372_IOPAD(0x858, DS0_PIN_INPUT | PIN_INPUT_PULLDOWN | MUX_MODE7) 149*4882a593Smuzhiyun AM4372_IOPAD(0x860, DS0_PIN_INPUT | PIN_INPUT_PULLDOWN | MUX_MODE7) 150*4882a593Smuzhiyun AM4372_IOPAD(0x864, DS0_PIN_INPUT | PIN_INPUT_PULLDOWN | MUX_MODE7) 151*4882a593Smuzhiyun AM4372_IOPAD(0x868, DS0_PIN_INPUT | PIN_INPUT_PULLDOWN | MUX_MODE7) 152*4882a593Smuzhiyun AM4372_IOPAD(0x86c, DS0_PIN_INPUT | PIN_INPUT_PULLDOWN | MUX_MODE7) 153*4882a593Smuzhiyun AM4372_IOPAD(0x878, DS0_PIN_OUTPUT_PULLUP | PIN_OUTPUT_PULLUP | MUX_MODE7) 154*4882a593Smuzhiyun AM4372_IOPAD(0x908, DS0_PIN_INPUT_PULLDOWN | PIN_INPUT_PULLDOWN | MUX_MODE7) 155*4882a593Smuzhiyun AM4372_IOPAD(0x91c, DS0_PIN_OUTPUT_PULLDOWN | PIN_OUTPUT_PULLDOWN | MUX_MODE7) 156*4882a593Smuzhiyun AM4372_IOPAD(0x920, DS0_PIN_INPUT | PIN_INPUT_PULLDOWN | MUX_MODE7) 157*4882a593Smuzhiyun AM4372_IOPAD(0x9e0, DS0_PIN_INPUT_PULLDOWN | PIN_INPUT_PULLDOWN | MUX_MODE7) 158*4882a593Smuzhiyun AM4372_IOPAD(0xA0c, DS0_PIN_OUTPUT_PULLDOWN | PIN_OUTPUT_PULLDOWN | MUX_MODE7) 159*4882a593Smuzhiyun AM4372_IOPAD(0xA38, DS0_PIN_INPUT | PIN_INPUT_PULLDOWN | MUX_MODE7) 160*4882a593Smuzhiyun AM4372_IOPAD(0xA3c, DS0_PIN_INPUT | PIN_INPUT_PULLDOWN | MUX_MODE7) 161*4882a593Smuzhiyun AM4372_IOPAD(0xA40, DS0_PIN_INPUT | PIN_INPUT_PULLDOWN | MUX_MODE7) 162*4882a593Smuzhiyun AM4372_IOPAD(0xA44, DS0_PIN_INPUT | PIN_INPUT_PULLDOWN | MUX_MODE7) 163*4882a593Smuzhiyun AM4372_IOPAD(0xA48, DS0_PIN_INPUT | PIN_INPUT_PULLDOWN | MUX_MODE7) 164*4882a593Smuzhiyun AM4372_IOPAD(0xA4c, DS0_PIN_INPUT | PIN_INPUT_PULLDOWN | MUX_MODE7) 165*4882a593Smuzhiyun AM4372_IOPAD(0xA50, DS0_PIN_INPUT | PIN_INPUT_PULLDOWN | MUX_MODE7) 166*4882a593Smuzhiyun AM4372_IOPAD(0xA54, DS0_PIN_INPUT | PIN_INPUT_PULLDOWN | MUX_MODE7) 167*4882a593Smuzhiyun AM4372_IOPAD(0xA58, DS0_PIN_INPUT | PIN_INPUT_PULLDOWN | MUX_MODE7) 168*4882a593Smuzhiyun AM4372_IOPAD(0xA5c, DS0_PIN_INPUT | PIN_INPUT_PULLDOWN | MUX_MODE7) 169*4882a593Smuzhiyun AM4372_IOPAD(0xA60, DS0_PIN_INPUT | PIN_INPUT_PULLDOWN | MUX_MODE7) 170*4882a593Smuzhiyun AM4372_IOPAD(0xA64, DS0_PIN_OUTPUT_PULLUP | PIN_OUTPUT_PULLUP | MUX_MODE7) 171*4882a593Smuzhiyun AM4372_IOPAD(0xA68, DS0_PIN_INPUT | PIN_INPUT_PULLDOWN | MUX_MODE7) 172*4882a593Smuzhiyun AM4372_IOPAD(0xA6C, DS0_PIN_INPUT | PIN_INPUT_PULLDOWN | MUX_MODE7) 173*4882a593Smuzhiyun AM4372_IOPAD(0xA74, DS0_PIN_INPUT_PULLDOWN | PIN_INPUT_PULLDOWN | MUX_MODE7) 174*4882a593Smuzhiyun AM4372_IOPAD(0xA78, DS0_PIN_INPUT | PIN_INPUT_PULLDOWN | MUX_MODE7) 175*4882a593Smuzhiyun >; 176*4882a593Smuzhiyun }; 177*4882a593Smuzhiyun 178*4882a593Smuzhiyun cpsw_default: cpsw_default { 179*4882a593Smuzhiyun pinctrl-single,pins = < 180*4882a593Smuzhiyun /* Slave 1 */ 181*4882a593Smuzhiyun AM4372_IOPAD(0x90c, PIN_INPUT_PULLDOWN | MUX_MODE1) /* mii1_crs.rmii1_crs */ 182*4882a593Smuzhiyun AM4372_IOPAD(0x910, PIN_INPUT_PULLDOWN | MUX_MODE1) /* mii1_rxerr.rmii1_rxerr */ 183*4882a593Smuzhiyun AM4372_IOPAD(0x914, PIN_OUTPUT_PULLDOWN | MUX_MODE1) /* mii1_txen.rmii1_txen */ 184*4882a593Smuzhiyun AM4372_IOPAD(0x918, PIN_INPUT_PULLDOWN | MUX_MODE1) /* mii1_rxdv.rmii1_rxdv */ 185*4882a593Smuzhiyun AM4372_IOPAD(0x924, PIN_OUTPUT_PULLDOWN | MUX_MODE1) /* mii1_txd1.rmii1_txd1 */ 186*4882a593Smuzhiyun AM4372_IOPAD(0x928, PIN_OUTPUT_PULLDOWN | MUX_MODE1) /* mii1_txd0.rmii1_txd0 */ 187*4882a593Smuzhiyun AM4372_IOPAD(0x93c, PIN_INPUT_PULLDOWN | MUX_MODE1) /* mii1_rxd1.rmii1_rxd1 */ 188*4882a593Smuzhiyun AM4372_IOPAD(0x940, PIN_INPUT_PULLDOWN | MUX_MODE1) /* mii1_rxd0.rmii1_rxd0 */ 189*4882a593Smuzhiyun AM4372_IOPAD(0x944, PIN_INPUT_PULLDOWN | MUX_MODE0) /* rmii1_refclk.rmii1_refclk */ 190*4882a593Smuzhiyun >; 191*4882a593Smuzhiyun }; 192*4882a593Smuzhiyun 193*4882a593Smuzhiyun cpsw_sleep: cpsw_sleep { 194*4882a593Smuzhiyun pinctrl-single,pins = < 195*4882a593Smuzhiyun /* Slave 1 reset value */ 196*4882a593Smuzhiyun AM4372_IOPAD(0x90c, PIN_INPUT_PULLDOWN | MUX_MODE7) 197*4882a593Smuzhiyun AM4372_IOPAD(0x910, PIN_INPUT_PULLDOWN | MUX_MODE7) 198*4882a593Smuzhiyun AM4372_IOPAD(0x914, PIN_INPUT_PULLDOWN | MUX_MODE7) 199*4882a593Smuzhiyun AM4372_IOPAD(0x918, PIN_INPUT_PULLDOWN | MUX_MODE7) 200*4882a593Smuzhiyun AM4372_IOPAD(0x924, PIN_INPUT_PULLDOWN | MUX_MODE7) 201*4882a593Smuzhiyun AM4372_IOPAD(0x928, PIN_INPUT_PULLDOWN | MUX_MODE7) 202*4882a593Smuzhiyun AM4372_IOPAD(0x93c, PIN_INPUT_PULLDOWN | MUX_MODE7) 203*4882a593Smuzhiyun AM4372_IOPAD(0x940, PIN_INPUT_PULLDOWN | MUX_MODE7) 204*4882a593Smuzhiyun AM4372_IOPAD(0x944, PIN_INPUT_PULLDOWN | MUX_MODE7) 205*4882a593Smuzhiyun >; 206*4882a593Smuzhiyun }; 207*4882a593Smuzhiyun 208*4882a593Smuzhiyun davinci_mdio_default: davinci_mdio_default { 209*4882a593Smuzhiyun pinctrl-single,pins = < 210*4882a593Smuzhiyun /* MDIO */ 211*4882a593Smuzhiyun AM4372_IOPAD(0x948, PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* mdio_data.mdio_data */ 212*4882a593Smuzhiyun AM4372_IOPAD(0x94c, PIN_OUTPUT_PULLUP | MUX_MODE0) /* mdio_clk.mdio_clk */ 213*4882a593Smuzhiyun >; 214*4882a593Smuzhiyun }; 215*4882a593Smuzhiyun 216*4882a593Smuzhiyun davinci_mdio_sleep: davinci_mdio_sleep { 217*4882a593Smuzhiyun pinctrl-single,pins = < 218*4882a593Smuzhiyun /* MDIO reset value */ 219*4882a593Smuzhiyun AM4372_IOPAD(0x948, PIN_INPUT_PULLDOWN | MUX_MODE7) 220*4882a593Smuzhiyun AM4372_IOPAD(0x94c, PIN_INPUT_PULLDOWN | MUX_MODE7) 221*4882a593Smuzhiyun >; 222*4882a593Smuzhiyun }; 223*4882a593Smuzhiyun 224*4882a593Smuzhiyun i2c0_pins: pinmux_i2c0_pins { 225*4882a593Smuzhiyun pinctrl-single,pins = < 226*4882a593Smuzhiyun AM4372_IOPAD(0x988, PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* i2c0_sda.i2c0_sda */ 227*4882a593Smuzhiyun AM4372_IOPAD(0x98c, PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* i2c0_scl.i2c0_scl */ 228*4882a593Smuzhiyun >; 229*4882a593Smuzhiyun }; 230*4882a593Smuzhiyun 231*4882a593Smuzhiyun nand_flash_x8_default: nand_flash_x8_default { 232*4882a593Smuzhiyun pinctrl-single,pins = < 233*4882a593Smuzhiyun AM4372_IOPAD(0x840, PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_a0.SELQSPIorNAND/GPIO */ 234*4882a593Smuzhiyun AM4372_IOPAD(0x800, PIN_INPUT_PULLDOWN | MUX_MODE0) /* gpmc_ad0.gpmc_ad0 */ 235*4882a593Smuzhiyun AM4372_IOPAD(0x804, PIN_INPUT_PULLDOWN | MUX_MODE0) /* gpmc_ad1.gpmc_ad1 */ 236*4882a593Smuzhiyun AM4372_IOPAD(0x808, PIN_INPUT_PULLDOWN | MUX_MODE0) /* gpmc_ad2.gpmc_ad2 */ 237*4882a593Smuzhiyun AM4372_IOPAD(0x80c, PIN_INPUT_PULLDOWN | MUX_MODE0) /* gpmc_ad3.gpmc_ad3 */ 238*4882a593Smuzhiyun AM4372_IOPAD(0x810, PIN_INPUT_PULLDOWN | MUX_MODE0) /* gpmc_ad4.gpmc_ad4 */ 239*4882a593Smuzhiyun AM4372_IOPAD(0x814, PIN_INPUT_PULLDOWN | MUX_MODE0) /* gpmc_ad5.gpmc_ad5 */ 240*4882a593Smuzhiyun AM4372_IOPAD(0x818, PIN_INPUT_PULLDOWN | MUX_MODE0) /* gpmc_ad6.gpmc_ad6 */ 241*4882a593Smuzhiyun AM4372_IOPAD(0x81c, PIN_INPUT_PULLDOWN | MUX_MODE0) /* gpmc_ad7.gpmc_ad7 */ 242*4882a593Smuzhiyun AM4372_IOPAD(0x870, PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_wait0.gpmc_wait0 */ 243*4882a593Smuzhiyun AM4372_IOPAD(0x874, PIN_OUTPUT_PULLUP | MUX_MODE7) /* gpmc_wpn.gpmc_wpn */ 244*4882a593Smuzhiyun AM4372_IOPAD(0x87c, PIN_OUTPUT | MUX_MODE0) /* gpmc_csn0.gpmc_csn0 */ 245*4882a593Smuzhiyun AM4372_IOPAD(0x890, PIN_OUTPUT | MUX_MODE0) /* gpmc_advn_ale.gpmc_advn_ale */ 246*4882a593Smuzhiyun AM4372_IOPAD(0x894, PIN_OUTPUT | MUX_MODE0) /* gpmc_oen_ren.gpmc_oen_ren */ 247*4882a593Smuzhiyun AM4372_IOPAD(0x898, PIN_OUTPUT | MUX_MODE0) /* gpmc_wen.gpmc_wen */ 248*4882a593Smuzhiyun AM4372_IOPAD(0x89c, PIN_OUTPUT | MUX_MODE0) /* gpmc_be0n_cle.gpmc_be0n_cle */ 249*4882a593Smuzhiyun >; 250*4882a593Smuzhiyun }; 251*4882a593Smuzhiyun 252*4882a593Smuzhiyun nand_flash_x8_sleep: nand_flash_x8_sleep { 253*4882a593Smuzhiyun pinctrl-single,pins = < 254*4882a593Smuzhiyun AM4372_IOPAD(0x840, DS0_PIN_OUTPUT_PULLDOWN | MUX_MODE7) 255*4882a593Smuzhiyun AM4372_IOPAD(0x800, DS0_PIN_OUTPUT_PULLDOWN | MUX_MODE7) 256*4882a593Smuzhiyun AM4372_IOPAD(0x804, DS0_PIN_OUTPUT_PULLDOWN | MUX_MODE7) 257*4882a593Smuzhiyun AM4372_IOPAD(0x808, DS0_PIN_OUTPUT_PULLDOWN | MUX_MODE7) 258*4882a593Smuzhiyun AM4372_IOPAD(0x80c, DS0_PIN_OUTPUT_PULLDOWN | MUX_MODE7) 259*4882a593Smuzhiyun AM4372_IOPAD(0x810, DS0_PIN_OUTPUT_PULLDOWN | MUX_MODE7) 260*4882a593Smuzhiyun AM4372_IOPAD(0x814, DS0_PIN_OUTPUT_PULLDOWN | MUX_MODE7) 261*4882a593Smuzhiyun AM4372_IOPAD(0x818, DS0_PIN_OUTPUT_PULLDOWN | MUX_MODE7) 262*4882a593Smuzhiyun AM4372_IOPAD(0x81c, DS0_PIN_OUTPUT_PULLDOWN | MUX_MODE7) 263*4882a593Smuzhiyun AM4372_IOPAD(0x870, DS0_PIN_OUTPUT_PULLUP | MUX_MODE7) 264*4882a593Smuzhiyun AM4372_IOPAD(0x874, DS0_PIN_OUTPUT_PULLUP | MUX_MODE7) 265*4882a593Smuzhiyun AM4372_IOPAD(0x87c, DS0_PIN_OUTPUT_PULLUP | MUX_MODE7) 266*4882a593Smuzhiyun AM4372_IOPAD(0x890, DS0_PIN_OUTPUT_PULLUP | MUX_MODE7) 267*4882a593Smuzhiyun AM4372_IOPAD(0x894, DS0_PIN_OUTPUT_PULLUP | MUX_MODE7) 268*4882a593Smuzhiyun AM4372_IOPAD(0x898, DS0_PIN_OUTPUT_PULLUP | MUX_MODE7) 269*4882a593Smuzhiyun AM4372_IOPAD(0x89c, DS0_PIN_OUTPUT_PULLUP | MUX_MODE7) 270*4882a593Smuzhiyun >; 271*4882a593Smuzhiyun }; 272*4882a593Smuzhiyun 273*4882a593Smuzhiyun ecap0_pins_default: backlight_pins_default { 274*4882a593Smuzhiyun pinctrl-single,pins = < 275*4882a593Smuzhiyun AM4372_IOPAD(0x964, MUX_MODE0) /* eCAP0_in_PWM0_out.eCAP0_in_PWM0_out MODE0 */ 276*4882a593Smuzhiyun >; 277*4882a593Smuzhiyun }; 278*4882a593Smuzhiyun 279*4882a593Smuzhiyun ecap0_pins_sleep: backlight_pins_sleep { 280*4882a593Smuzhiyun pinctrl-single,pins = < 281*4882a593Smuzhiyun AM4372_IOPAD(0x964, DS0_PIN_OUTPUT_PULLUP | MUX_MODE7) 282*4882a593Smuzhiyun >; 283*4882a593Smuzhiyun }; 284*4882a593Smuzhiyun 285*4882a593Smuzhiyun i2c2_pins: pinmux_i2c2_pins { 286*4882a593Smuzhiyun pinctrl-single,pins = < 287*4882a593Smuzhiyun AM4372_IOPAD(0x9c0, PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE8) /* i2c2_sda.i2c2_sda */ 288*4882a593Smuzhiyun AM4372_IOPAD(0x9c4, PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE8) /* i2c2_scl.i2c2_scl */ 289*4882a593Smuzhiyun >; 290*4882a593Smuzhiyun }; 291*4882a593Smuzhiyun 292*4882a593Smuzhiyun spi0_pins_default: pinmux_spi0_pins_default { 293*4882a593Smuzhiyun pinctrl-single,pins = < 294*4882a593Smuzhiyun AM4372_IOPAD(0x950, PIN_INPUT | MUX_MODE0) /* spi0_clk.spi0_clk */ 295*4882a593Smuzhiyun AM4372_IOPAD(0x954, PIN_OUTPUT | MUX_MODE0) /* spi0_d0.spi0_d0 */ 296*4882a593Smuzhiyun AM4372_IOPAD(0x958, PIN_INPUT | MUX_MODE0) /* spi0_d1.spi0_d1 */ 297*4882a593Smuzhiyun AM4372_IOPAD(0x95c, PIN_OUTPUT | MUX_MODE0) /* spi0_cs0.spi0_cs0 */ 298*4882a593Smuzhiyun >; 299*4882a593Smuzhiyun }; 300*4882a593Smuzhiyun 301*4882a593Smuzhiyun spi0_pins_sleep: pinmux_spi0_pins_sleep { 302*4882a593Smuzhiyun pinctrl-single,pins = < 303*4882a593Smuzhiyun AM4372_IOPAD(0x950, DS0_PIN_OUTPUT_PULLUP | PIN_OUTPUT_PULLUP | MUX_MODE7) 304*4882a593Smuzhiyun AM4372_IOPAD(0x954, DS0_PIN_OUTPUT_PULLUP | PIN_OUTPUT_PULLUP | MUX_MODE7) 305*4882a593Smuzhiyun AM4372_IOPAD(0x958, DS0_PIN_OUTPUT_PULLUP | PIN_OUTPUT_PULLUP | MUX_MODE7) 306*4882a593Smuzhiyun AM4372_IOPAD(0x95c, DS0_PIN_OUTPUT_PULLUP | PIN_OUTPUT_PULLUP | MUX_MODE7) 307*4882a593Smuzhiyun >; 308*4882a593Smuzhiyun }; 309*4882a593Smuzhiyun 310*4882a593Smuzhiyun spi1_pins_default: pinmux_spi1_pins_default { 311*4882a593Smuzhiyun pinctrl-single,pins = < 312*4882a593Smuzhiyun AM4372_IOPAD(0x990, PIN_INPUT | MUX_MODE3) /* mcasp0_aclkx.spi1_clk */ 313*4882a593Smuzhiyun AM4372_IOPAD(0x994, PIN_OUTPUT | MUX_MODE3) /* mcasp0_fsx.spi1_d0 */ 314*4882a593Smuzhiyun AM4372_IOPAD(0x998, PIN_INPUT | MUX_MODE3) /* mcasp0_axr0.spi1_d1 */ 315*4882a593Smuzhiyun AM4372_IOPAD(0x99c, PIN_OUTPUT | MUX_MODE3) /* mcasp0_ahclkr.spi1_cs0 */ 316*4882a593Smuzhiyun >; 317*4882a593Smuzhiyun }; 318*4882a593Smuzhiyun 319*4882a593Smuzhiyun spi1_pins_sleep: pinmux_spi1_pins_sleep { 320*4882a593Smuzhiyun pinctrl-single,pins = < 321*4882a593Smuzhiyun AM4372_IOPAD(0x990, DS0_PIN_OUTPUT_PULLDOWN | PIN_OUTPUT_PULLDOWN | MUX_MODE7) 322*4882a593Smuzhiyun AM4372_IOPAD(0x994, DS0_PIN_OUTPUT_PULLDOWN | PIN_OUTPUT_PULLDOWN | MUX_MODE7) 323*4882a593Smuzhiyun AM4372_IOPAD(0x998, DS0_PIN_OUTPUT_PULLDOWN | PIN_OUTPUT_PULLDOWN | MUX_MODE7) 324*4882a593Smuzhiyun AM4372_IOPAD(0x99c, DS0_PIN_OUTPUT_PULLDOWN | PIN_OUTPUT_PULLDOWN | MUX_MODE7) 325*4882a593Smuzhiyun >; 326*4882a593Smuzhiyun }; 327*4882a593Smuzhiyun 328*4882a593Smuzhiyun mmc1_pins_default: pinmux_mmc1_pins_default { 329*4882a593Smuzhiyun pinctrl-single,pins = < 330*4882a593Smuzhiyun AM4372_IOPAD(0x960, PIN_INPUT | MUX_MODE7) /* spi0_cs1.gpio0_6 */ 331*4882a593Smuzhiyun >; 332*4882a593Smuzhiyun }; 333*4882a593Smuzhiyun 334*4882a593Smuzhiyun mmc1_pins_sleep: pinmux_mmc1_pins_sleep { 335*4882a593Smuzhiyun pinctrl-single,pins = < 336*4882a593Smuzhiyun AM4372_IOPAD(0x960, DS0_PIN_OUTPUT_PULLUP | PIN_INPUT | MUX_MODE7) 337*4882a593Smuzhiyun >; 338*4882a593Smuzhiyun }; 339*4882a593Smuzhiyun 340*4882a593Smuzhiyun matrix_keypad_default: matrix_keypad_default { 341*4882a593Smuzhiyun pinctrl-single,pins = < 342*4882a593Smuzhiyun AM4372_IOPAD(0x92c, PIN_OUTPUT | MUX_MODE7) /* mii1_tx_clk.gpio3_9 */ 343*4882a593Smuzhiyun AM4372_IOPAD(0x930, PIN_OUTPUT | MUX_MODE7) /* mii1_rx_clk.gpio3_10 */ 344*4882a593Smuzhiyun AM4372_IOPAD(0x934, PIN_OUTPUT | MUX_MODE7) /* mii1_rxd3.gpio2_18 */ 345*4882a593Smuzhiyun AM4372_IOPAD(0x938, PIN_OUTPUT | MUX_MODE7) /* mii1_rxd2.gpio2_19 */ 346*4882a593Smuzhiyun AM4372_IOPAD(0x978, PIN_INPUT_PULLDOWN | MUX_MODE7) /* uart1_ctsn.gpio0_12 */ 347*4882a593Smuzhiyun AM4372_IOPAD(0x97C, PIN_INPUT_PULLDOWN | MUX_MODE7) /* uart1_rtsn.gpio0_13 */ 348*4882a593Smuzhiyun AM4372_IOPAD(0x980, PIN_INPUT_PULLDOWN | MUX_MODE7) /* uart1_rxd.gpio0_14 */ 349*4882a593Smuzhiyun AM4372_IOPAD(0x984, PIN_INPUT_PULLDOWN | MUX_MODE7) /* uart1_txd.gpio0_15 */ 350*4882a593Smuzhiyun >; 351*4882a593Smuzhiyun }; 352*4882a593Smuzhiyun 353*4882a593Smuzhiyun matrix_keypad_sleep: matrix_keypad_sleep { 354*4882a593Smuzhiyun pinctrl-single,pins = < 355*4882a593Smuzhiyun AM4372_IOPAD(0x92c, PIN_INPUT_PULLUP | MUX_MODE7) 356*4882a593Smuzhiyun AM4372_IOPAD(0x930, PIN_INPUT_PULLUP | MUX_MODE7) 357*4882a593Smuzhiyun AM4372_IOPAD(0x934, PIN_INPUT_PULLUP | MUX_MODE7) 358*4882a593Smuzhiyun AM4372_IOPAD(0x938, PIN_INPUT_PULLUP | MUX_MODE7) 359*4882a593Smuzhiyun AM4372_IOPAD(0x978, PIN_INPUT_PULLDOWN | MUX_MODE7) 360*4882a593Smuzhiyun AM4372_IOPAD(0x97C, PIN_INPUT_PULLDOWN | MUX_MODE7) 361*4882a593Smuzhiyun AM4372_IOPAD(0x980, PIN_INPUT_PULLDOWN | MUX_MODE7) 362*4882a593Smuzhiyun AM4372_IOPAD(0x984, PIN_INPUT_PULLDOWN | MUX_MODE7) 363*4882a593Smuzhiyun >; 364*4882a593Smuzhiyun }; 365*4882a593Smuzhiyun 366*4882a593Smuzhiyun qspi1_pins_default: qspi1_pins_default { 367*4882a593Smuzhiyun pinctrl-single,pins = < 368*4882a593Smuzhiyun AM4372_IOPAD(0x87c, PIN_INPUT_PULLUP | MUX_MODE3) 369*4882a593Smuzhiyun AM4372_IOPAD(0x888, PIN_INPUT_PULLUP | MUX_MODE2) 370*4882a593Smuzhiyun AM4372_IOPAD(0x890, PIN_INPUT_PULLUP | MUX_MODE3) 371*4882a593Smuzhiyun AM4372_IOPAD(0x894, PIN_INPUT_PULLUP | MUX_MODE3) 372*4882a593Smuzhiyun AM4372_IOPAD(0x898, PIN_INPUT_PULLUP | MUX_MODE3) 373*4882a593Smuzhiyun AM4372_IOPAD(0x89c, PIN_INPUT_PULLUP | MUX_MODE3) 374*4882a593Smuzhiyun >; 375*4882a593Smuzhiyun }; 376*4882a593Smuzhiyun 377*4882a593Smuzhiyun qspi1_pins_sleep: qspi1_pins_sleep { 378*4882a593Smuzhiyun pinctrl-single,pins = < 379*4882a593Smuzhiyun AM4372_IOPAD(0x87c, DS0_PIN_OUTPUT_PULLUP | MUX_MODE7) 380*4882a593Smuzhiyun AM4372_IOPAD(0x888, DS0_PIN_OUTPUT_PULLUP | MUX_MODE7) 381*4882a593Smuzhiyun AM4372_IOPAD(0x890, DS0_PIN_OUTPUT_PULLUP | MUX_MODE7) 382*4882a593Smuzhiyun AM4372_IOPAD(0x894, DS0_PIN_OUTPUT_PULLUP | MUX_MODE7) 383*4882a593Smuzhiyun AM4372_IOPAD(0x898, DS0_PIN_OUTPUT_PULLUP | MUX_MODE7) 384*4882a593Smuzhiyun AM4372_IOPAD(0x89c, DS0_PIN_OUTPUT_PULLUP | MUX_MODE7) 385*4882a593Smuzhiyun >; 386*4882a593Smuzhiyun }; 387*4882a593Smuzhiyun 388*4882a593Smuzhiyun pixcir_ts_pins_default: pixcir_ts_pins_default { 389*4882a593Smuzhiyun pinctrl-single,pins = < 390*4882a593Smuzhiyun AM4372_IOPAD(0x844, PIN_INPUT_PULLUP | MUX_MODE7) /* gpmc_a1.gpio1_17 */ 391*4882a593Smuzhiyun >; 392*4882a593Smuzhiyun }; 393*4882a593Smuzhiyun 394*4882a593Smuzhiyun pixcir_ts_pins_sleep: pixcir_ts_pins_sleep { 395*4882a593Smuzhiyun pinctrl-single,pins = < 396*4882a593Smuzhiyun AM4372_IOPAD(0x844, DS0_PIN_OUTPUT_PULLUP | PIN_OUTPUT_PULLUP | MUX_MODE7) /* gpmc_a1.gpio1_17 */ 397*4882a593Smuzhiyun >; 398*4882a593Smuzhiyun }; 399*4882a593Smuzhiyun 400*4882a593Smuzhiyun hdq_pins: pinmux_hdq_pins { 401*4882a593Smuzhiyun pinctrl-single,pins = < 402*4882a593Smuzhiyun AM4372_IOPAD(0xa34, PIN_INPUT_PULLUP | MUX_MODE1) /* cam1_wen.hdq_gpio */ 403*4882a593Smuzhiyun >; 404*4882a593Smuzhiyun }; 405*4882a593Smuzhiyun 406*4882a593Smuzhiyun dss_pins: dss_pins { 407*4882a593Smuzhiyun pinctrl-single,pins = < 408*4882a593Smuzhiyun AM4372_IOPAD(0x820, PIN_OUTPUT_PULLUP | MUX_MODE1) /*gpmc ad 8 -> DSS DATA 23 */ 409*4882a593Smuzhiyun AM4372_IOPAD(0x824, PIN_OUTPUT_PULLUP | MUX_MODE1) 410*4882a593Smuzhiyun AM4372_IOPAD(0x828, PIN_OUTPUT_PULLUP | MUX_MODE1) 411*4882a593Smuzhiyun AM4372_IOPAD(0x82c, PIN_OUTPUT_PULLUP | MUX_MODE1) 412*4882a593Smuzhiyun AM4372_IOPAD(0x830, PIN_OUTPUT_PULLUP | MUX_MODE1) 413*4882a593Smuzhiyun AM4372_IOPAD(0x834, PIN_OUTPUT_PULLUP | MUX_MODE1) 414*4882a593Smuzhiyun AM4372_IOPAD(0x838, PIN_OUTPUT_PULLUP | MUX_MODE1) 415*4882a593Smuzhiyun AM4372_IOPAD(0x83c, PIN_OUTPUT_PULLUP | MUX_MODE1) /*gpmc ad 15 -> DSS DATA 16 */ 416*4882a593Smuzhiyun AM4372_IOPAD(0x8a0, PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS DATA 0 */ 417*4882a593Smuzhiyun AM4372_IOPAD(0x8a4, PIN_OUTPUT_PULLUP | MUX_MODE0) 418*4882a593Smuzhiyun AM4372_IOPAD(0x8a8, PIN_OUTPUT_PULLUP | MUX_MODE0) 419*4882a593Smuzhiyun AM4372_IOPAD(0x8ac, PIN_OUTPUT_PULLUP | MUX_MODE0) 420*4882a593Smuzhiyun AM4372_IOPAD(0x8b0, PIN_OUTPUT_PULLUP | MUX_MODE0) 421*4882a593Smuzhiyun AM4372_IOPAD(0x8b4, PIN_OUTPUT_PULLUP | MUX_MODE0) 422*4882a593Smuzhiyun AM4372_IOPAD(0x8B8, PIN_OUTPUT_PULLUP | MUX_MODE0) 423*4882a593Smuzhiyun AM4372_IOPAD(0x8bc, PIN_OUTPUT_PULLUP | MUX_MODE0) 424*4882a593Smuzhiyun AM4372_IOPAD(0x8c0, PIN_OUTPUT_PULLUP | MUX_MODE0) 425*4882a593Smuzhiyun AM4372_IOPAD(0x8c4, PIN_OUTPUT_PULLUP | MUX_MODE0) 426*4882a593Smuzhiyun AM4372_IOPAD(0x8c8, PIN_OUTPUT_PULLUP | MUX_MODE0) 427*4882a593Smuzhiyun AM4372_IOPAD(0x8cc, PIN_OUTPUT_PULLUP | MUX_MODE0) 428*4882a593Smuzhiyun AM4372_IOPAD(0x8d0, PIN_OUTPUT_PULLUP | MUX_MODE0) 429*4882a593Smuzhiyun AM4372_IOPAD(0x8d4, PIN_OUTPUT_PULLUP | MUX_MODE0) 430*4882a593Smuzhiyun AM4372_IOPAD(0x8d8, PIN_OUTPUT_PULLUP | MUX_MODE0) 431*4882a593Smuzhiyun AM4372_IOPAD(0x8dc, PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS DATA 15 */ 432*4882a593Smuzhiyun AM4372_IOPAD(0x8e0, PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS VSYNC */ 433*4882a593Smuzhiyun AM4372_IOPAD(0x8e4, PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS HSYNC */ 434*4882a593Smuzhiyun AM4372_IOPAD(0x8e8, PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS PCLK */ 435*4882a593Smuzhiyun AM4372_IOPAD(0x8ec, PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS AC BIAS EN */ 436*4882a593Smuzhiyun >; 437*4882a593Smuzhiyun }; 438*4882a593Smuzhiyun 439*4882a593Smuzhiyun display_mux_pins: display_mux_pins { 440*4882a593Smuzhiyun pinctrl-single,pins = < 441*4882a593Smuzhiyun /* GPMC CLK -> GPIO 2_1 to select LCD / HDMI */ 442*4882a593Smuzhiyun AM4372_IOPAD(0x88C, PIN_OUTPUT_PULLUP | MUX_MODE7) 443*4882a593Smuzhiyun >; 444*4882a593Smuzhiyun }; 445*4882a593Smuzhiyun 446*4882a593Smuzhiyun vpfe1_pins_default: vpfe1_pins_default { 447*4882a593Smuzhiyun pinctrl-single,pins = < 448*4882a593Smuzhiyun AM4372_IOPAD(0x9cc, PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data9 mode 0 */ 449*4882a593Smuzhiyun AM4372_IOPAD(0x9d0, PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data8 mode 0 */ 450*4882a593Smuzhiyun AM4372_IOPAD(0x9d4, PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_hd mode 0 */ 451*4882a593Smuzhiyun AM4372_IOPAD(0x9d8, PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_vd mode 0 */ 452*4882a593Smuzhiyun AM4372_IOPAD(0x9dc, PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_pclk mode 0 */ 453*4882a593Smuzhiyun AM4372_IOPAD(0x9e8, PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data0 mode 0 */ 454*4882a593Smuzhiyun AM4372_IOPAD(0x9ec, PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data1 mode 0 */ 455*4882a593Smuzhiyun AM4372_IOPAD(0x9f0, PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data2 mode 0 */ 456*4882a593Smuzhiyun AM4372_IOPAD(0x9f4, PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data3 mode 0 */ 457*4882a593Smuzhiyun AM4372_IOPAD(0x9f8, PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data4 mode 0 */ 458*4882a593Smuzhiyun AM4372_IOPAD(0x9fc, PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data5 mode 0 */ 459*4882a593Smuzhiyun AM4372_IOPAD(0xa00, PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data6 mode 0 */ 460*4882a593Smuzhiyun AM4372_IOPAD(0xa04, PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data7 mode 0 */ 461*4882a593Smuzhiyun >; 462*4882a593Smuzhiyun }; 463*4882a593Smuzhiyun 464*4882a593Smuzhiyun vpfe1_pins_sleep: vpfe1_pins_sleep { 465*4882a593Smuzhiyun pinctrl-single,pins = < 466*4882a593Smuzhiyun AM4372_IOPAD(0x9cc, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) 467*4882a593Smuzhiyun AM4372_IOPAD(0x9d0, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) 468*4882a593Smuzhiyun AM4372_IOPAD(0x9d4, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) 469*4882a593Smuzhiyun AM4372_IOPAD(0x9d8, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) 470*4882a593Smuzhiyun AM4372_IOPAD(0x9dc, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) 471*4882a593Smuzhiyun AM4372_IOPAD(0x9e8, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) 472*4882a593Smuzhiyun AM4372_IOPAD(0x9ec, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) 473*4882a593Smuzhiyun AM4372_IOPAD(0x9f0, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) 474*4882a593Smuzhiyun AM4372_IOPAD(0x9f4, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) 475*4882a593Smuzhiyun AM4372_IOPAD(0x9f8, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) 476*4882a593Smuzhiyun AM4372_IOPAD(0x9fc, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) 477*4882a593Smuzhiyun AM4372_IOPAD(0xa00, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) 478*4882a593Smuzhiyun AM4372_IOPAD(0xa04, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) 479*4882a593Smuzhiyun >; 480*4882a593Smuzhiyun }; 481*4882a593Smuzhiyun 482*4882a593Smuzhiyun uart0_pins_default: uart0_pins_default { 483*4882a593Smuzhiyun pinctrl-single,pins = < 484*4882a593Smuzhiyun AM4372_IOPAD(0x968, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE0) /* uart0_ctsn.uart0_ctsn */ 485*4882a593Smuzhiyun AM4372_IOPAD(0x96C, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE0) /* uart0_rtsn.uart0_rtsn */ 486*4882a593Smuzhiyun AM4372_IOPAD(0x970, PIN_INPUT_PULLUP | SLEWCTRL_FAST | DS0_PULL_UP_DOWN_EN | MUX_MODE0) /* uart0_rxd.uart0_rxd */ 487*4882a593Smuzhiyun AM4372_IOPAD(0x974, PIN_INPUT | SLEWCTRL_FAST | DS0_PULL_UP_DOWN_EN | MUX_MODE0) /* uart0_txd.uart0_txd */ 488*4882a593Smuzhiyun >; 489*4882a593Smuzhiyun }; 490*4882a593Smuzhiyun 491*4882a593Smuzhiyun uart0_pins_sleep: uart0_pins_sleep { 492*4882a593Smuzhiyun pinctrl-single,pins = < 493*4882a593Smuzhiyun AM4372_IOPAD(0x968, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) 494*4882a593Smuzhiyun AM4372_IOPAD(0x96C, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) 495*4882a593Smuzhiyun AM4372_IOPAD(0x970, PIN_INPUT_PULLUP | SLEWCTRL_FAST | DS0_PULL_UP_DOWN_EN | MUX_MODE0) 496*4882a593Smuzhiyun AM4372_IOPAD(0x974, PIN_INPUT | SLEWCTRL_FAST | DS0_PULL_UP_DOWN_EN | MUX_MODE0) 497*4882a593Smuzhiyun >; 498*4882a593Smuzhiyun }; 499*4882a593Smuzhiyun 500*4882a593Smuzhiyun usb2_phy1_default: usb2_phy1_default { 501*4882a593Smuzhiyun pinctrl-single,pins = < 502*4882a593Smuzhiyun AM4372_IOPAD(0xac0, PIN_INPUT_PULLDOWN | MUX_MODE0) 503*4882a593Smuzhiyun >; 504*4882a593Smuzhiyun }; 505*4882a593Smuzhiyun 506*4882a593Smuzhiyun usb2_phy1_sleep: usb2_phy1_sleep { 507*4882a593Smuzhiyun pinctrl-single,pins = < 508*4882a593Smuzhiyun AM4372_IOPAD(0xac0, DS0_PULL_UP_DOWN_EN | PIN_INPUT_PULLDOWN | MUX_MODE7) 509*4882a593Smuzhiyun >; 510*4882a593Smuzhiyun }; 511*4882a593Smuzhiyun 512*4882a593Smuzhiyun usb2_phy2_default: usb2_phy2_default { 513*4882a593Smuzhiyun pinctrl-single,pins = < 514*4882a593Smuzhiyun AM4372_IOPAD(0xac4, PIN_INPUT_PULLDOWN | MUX_MODE0) 515*4882a593Smuzhiyun >; 516*4882a593Smuzhiyun }; 517*4882a593Smuzhiyun 518*4882a593Smuzhiyun usb2_phy2_sleep: usb2_phy2_sleep { 519*4882a593Smuzhiyun pinctrl-single,pins = < 520*4882a593Smuzhiyun AM4372_IOPAD(0xac4, DS0_PULL_UP_DOWN_EN | PIN_INPUT_PULLDOWN | MUX_MODE7) 521*4882a593Smuzhiyun >; 522*4882a593Smuzhiyun }; 523*4882a593Smuzhiyun 524*4882a593Smuzhiyun mcasp1_pins: mcasp1_pins { 525*4882a593Smuzhiyun pinctrl-single,pins = < 526*4882a593Smuzhiyun AM4372_IOPAD(0x9a0, PIN_INPUT_PULLDOWN | MUX_MODE3) /* MCASP0_ACLKR/MCASP1_ACLKX */ 527*4882a593Smuzhiyun AM4372_IOPAD(0x9a4, PIN_INPUT_PULLDOWN | MUX_MODE3) /* MCASP0_FSR/MCASP1_FSX */ 528*4882a593Smuzhiyun AM4372_IOPAD(0x9a8, PIN_OUTPUT_PULLDOWN | MUX_MODE3)/* MCASP0_AXR1/MCASP1_AXR0 */ 529*4882a593Smuzhiyun AM4372_IOPAD(0x9ac, PIN_INPUT_PULLDOWN | MUX_MODE3) /* MCASP0_AHCLKX/MCASP1_AXR1 */ 530*4882a593Smuzhiyun >; 531*4882a593Smuzhiyun }; 532*4882a593Smuzhiyun 533*4882a593Smuzhiyun mcasp1_sleep_pins: mcasp1_sleep_pins { 534*4882a593Smuzhiyun pinctrl-single,pins = < 535*4882a593Smuzhiyun AM4372_IOPAD(0x9a0, PIN_INPUT_PULLDOWN | MUX_MODE7) 536*4882a593Smuzhiyun AM4372_IOPAD(0x9a4, PIN_INPUT_PULLDOWN | MUX_MODE7) 537*4882a593Smuzhiyun AM4372_IOPAD(0x9a8, PIN_INPUT_PULLDOWN | MUX_MODE7) 538*4882a593Smuzhiyun AM4372_IOPAD(0x9ac, PIN_INPUT_PULLDOWN | MUX_MODE7) 539*4882a593Smuzhiyun >; 540*4882a593Smuzhiyun }; 541*4882a593Smuzhiyun}; 542*4882a593Smuzhiyun 543*4882a593Smuzhiyun&mmc1 { 544*4882a593Smuzhiyun status = "okay"; 545*4882a593Smuzhiyun vmmc-supply = <&vmmcsd_fixed>; 546*4882a593Smuzhiyun bus-width = <4>; 547*4882a593Smuzhiyun pinctrl-names = "default", "sleep"; 548*4882a593Smuzhiyun pinctrl-0 = <&mmc1_pins_default>; 549*4882a593Smuzhiyun pinctrl-1 = <&mmc1_pins_sleep>; 550*4882a593Smuzhiyun cd-gpios = <&gpio0 6 GPIO_ACTIVE_LOW>; 551*4882a593Smuzhiyun}; 552*4882a593Smuzhiyun 553*4882a593Smuzhiyun&mac_sw { 554*4882a593Smuzhiyun pinctrl-names = "default", "sleep"; 555*4882a593Smuzhiyun pinctrl-0 = <&cpsw_default>; 556*4882a593Smuzhiyun pinctrl-1 = <&cpsw_sleep>; 557*4882a593Smuzhiyun status = "okay"; 558*4882a593Smuzhiyun}; 559*4882a593Smuzhiyun 560*4882a593Smuzhiyun&davinci_mdio_sw { 561*4882a593Smuzhiyun pinctrl-names = "default", "sleep"; 562*4882a593Smuzhiyun pinctrl-0 = <&davinci_mdio_default>; 563*4882a593Smuzhiyun pinctrl-1 = <&davinci_mdio_sleep>; 564*4882a593Smuzhiyun 565*4882a593Smuzhiyun ethphy0: ethernet-phy@16 { 566*4882a593Smuzhiyun reg = <16>; 567*4882a593Smuzhiyun }; 568*4882a593Smuzhiyun}; 569*4882a593Smuzhiyun 570*4882a593Smuzhiyun&cpsw_port1 { 571*4882a593Smuzhiyun phy-handle = <ðphy0>; 572*4882a593Smuzhiyun phy-mode = "rmii"; 573*4882a593Smuzhiyun phys = <&phy_gmii_sel 1 1>; 574*4882a593Smuzhiyun ti,dual-emac-pvid = <1>; 575*4882a593Smuzhiyun}; 576*4882a593Smuzhiyun 577*4882a593Smuzhiyun&cpsw_port2 { 578*4882a593Smuzhiyun status = "disabled"; 579*4882a593Smuzhiyun}; 580*4882a593Smuzhiyun 581*4882a593Smuzhiyun&i2c0 { 582*4882a593Smuzhiyun status = "okay"; 583*4882a593Smuzhiyun pinctrl-names = "default"; 584*4882a593Smuzhiyun pinctrl-0 = <&i2c0_pins>; 585*4882a593Smuzhiyun clock-frequency = <100000>; 586*4882a593Smuzhiyun 587*4882a593Smuzhiyun tps65218: tps65218@24 { 588*4882a593Smuzhiyun reg = <0x24>; 589*4882a593Smuzhiyun compatible = "ti,tps65218"; 590*4882a593Smuzhiyun interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; /* NMIn */ 591*4882a593Smuzhiyun interrupt-controller; 592*4882a593Smuzhiyun #interrupt-cells = <2>; 593*4882a593Smuzhiyun 594*4882a593Smuzhiyun dcdc1: regulator-dcdc1 { 595*4882a593Smuzhiyun regulator-name = "vdd_core"; 596*4882a593Smuzhiyun regulator-min-microvolt = <912000>; 597*4882a593Smuzhiyun regulator-max-microvolt = <1144000>; 598*4882a593Smuzhiyun regulator-boot-on; 599*4882a593Smuzhiyun regulator-always-on; 600*4882a593Smuzhiyun }; 601*4882a593Smuzhiyun 602*4882a593Smuzhiyun dcdc2: regulator-dcdc2 { 603*4882a593Smuzhiyun regulator-name = "vdd_mpu"; 604*4882a593Smuzhiyun regulator-min-microvolt = <912000>; 605*4882a593Smuzhiyun regulator-max-microvolt = <1378000>; 606*4882a593Smuzhiyun regulator-boot-on; 607*4882a593Smuzhiyun regulator-always-on; 608*4882a593Smuzhiyun }; 609*4882a593Smuzhiyun 610*4882a593Smuzhiyun dcdc3: regulator-dcdc3 { 611*4882a593Smuzhiyun regulator-name = "vdcdc3"; 612*4882a593Smuzhiyun regulator-boot-on; 613*4882a593Smuzhiyun regulator-always-on; 614*4882a593Smuzhiyun regulator-state-mem { 615*4882a593Smuzhiyun regulator-on-in-suspend; 616*4882a593Smuzhiyun }; 617*4882a593Smuzhiyun regulator-state-disk { 618*4882a593Smuzhiyun regulator-off-in-suspend; 619*4882a593Smuzhiyun }; 620*4882a593Smuzhiyun }; 621*4882a593Smuzhiyun 622*4882a593Smuzhiyun dcdc4: regulator-dcdc4 { 623*4882a593Smuzhiyun regulator-name = "vdcdc4"; 624*4882a593Smuzhiyun regulator-min-microvolt = <3300000>; 625*4882a593Smuzhiyun regulator-max-microvolt = <3300000>; 626*4882a593Smuzhiyun regulator-boot-on; 627*4882a593Smuzhiyun regulator-always-on; 628*4882a593Smuzhiyun }; 629*4882a593Smuzhiyun 630*4882a593Smuzhiyun dcdc5: regulator-dcdc5 { 631*4882a593Smuzhiyun regulator-name = "v1_0bat"; 632*4882a593Smuzhiyun regulator-min-microvolt = <1000000>; 633*4882a593Smuzhiyun regulator-max-microvolt = <1000000>; 634*4882a593Smuzhiyun regulator-boot-on; 635*4882a593Smuzhiyun regulator-always-on; 636*4882a593Smuzhiyun }; 637*4882a593Smuzhiyun 638*4882a593Smuzhiyun dcdc6: regulator-dcdc6 { 639*4882a593Smuzhiyun regulator-name = "v1_8bat"; 640*4882a593Smuzhiyun regulator-min-microvolt = <1800000>; 641*4882a593Smuzhiyun regulator-max-microvolt = <1800000>; 642*4882a593Smuzhiyun regulator-boot-on; 643*4882a593Smuzhiyun regulator-always-on; 644*4882a593Smuzhiyun }; 645*4882a593Smuzhiyun 646*4882a593Smuzhiyun ldo1: regulator-ldo1 { 647*4882a593Smuzhiyun regulator-min-microvolt = <1800000>; 648*4882a593Smuzhiyun regulator-max-microvolt = <1800000>; 649*4882a593Smuzhiyun regulator-boot-on; 650*4882a593Smuzhiyun regulator-always-on; 651*4882a593Smuzhiyun }; 652*4882a593Smuzhiyun }; 653*4882a593Smuzhiyun 654*4882a593Smuzhiyun at24@50 { 655*4882a593Smuzhiyun compatible = "atmel,24c256"; 656*4882a593Smuzhiyun pagesize = <64>; 657*4882a593Smuzhiyun reg = <0x50>; 658*4882a593Smuzhiyun }; 659*4882a593Smuzhiyun 660*4882a593Smuzhiyun pixcir_ts@5c { 661*4882a593Smuzhiyun compatible = "pixcir,pixcir_tangoc"; 662*4882a593Smuzhiyun pinctrl-names = "default", "sleep"; 663*4882a593Smuzhiyun pinctrl-0 = <&pixcir_ts_pins_default>; 664*4882a593Smuzhiyun pinctrl-1 = <&pixcir_ts_pins_sleep>; 665*4882a593Smuzhiyun 666*4882a593Smuzhiyun reg = <0x5c>; 667*4882a593Smuzhiyun interrupt-parent = <&gpio1>; 668*4882a593Smuzhiyun interrupts = <17 IRQ_TYPE_EDGE_FALLING>; 669*4882a593Smuzhiyun 670*4882a593Smuzhiyun attb-gpio = <&gpio1 17 GPIO_ACTIVE_HIGH>; 671*4882a593Smuzhiyun 672*4882a593Smuzhiyun touchscreen-size-x = <1024>; 673*4882a593Smuzhiyun touchscreen-size-y = <600>; 674*4882a593Smuzhiyun }; 675*4882a593Smuzhiyun 676*4882a593Smuzhiyun tlv320aic3111: tlv320aic3111@18 { 677*4882a593Smuzhiyun #sound-dai-cells = <0>; 678*4882a593Smuzhiyun compatible = "ti,tlv320aic3111"; 679*4882a593Smuzhiyun reg = <0x18>; 680*4882a593Smuzhiyun status = "okay"; 681*4882a593Smuzhiyun 682*4882a593Smuzhiyun ai31xx-micbias-vg = <MICBIAS_2_0V>; 683*4882a593Smuzhiyun 684*4882a593Smuzhiyun /* Regulators */ 685*4882a593Smuzhiyun HPVDD-supply = <&dcdc4>; /* v3_3AUD -> V3_3D -> DCDC4 */ 686*4882a593Smuzhiyun SPRVDD-supply = <&vbat>; /* vbat */ 687*4882a593Smuzhiyun SPLVDD-supply = <&vbat>; /* vbat */ 688*4882a593Smuzhiyun AVDD-supply = <&dcdc4>; /* v3_3AUD -> V3_3D -> DCDC4 */ 689*4882a593Smuzhiyun IOVDD-supply = <&dcdc4>; /* V3_3D -> DCDC4 */ 690*4882a593Smuzhiyun DVDD-supply = <&ldo1>; /* V1_8AUD -> V1_8D -> LDO1 */ 691*4882a593Smuzhiyun }; 692*4882a593Smuzhiyun 693*4882a593Smuzhiyun ov2659@30 { 694*4882a593Smuzhiyun compatible = "ovti,ov2659"; 695*4882a593Smuzhiyun reg = <0x30>; 696*4882a593Smuzhiyun 697*4882a593Smuzhiyun clocks = <&audio_mstrclk>; 698*4882a593Smuzhiyun clock-names = "xvclk"; 699*4882a593Smuzhiyun 700*4882a593Smuzhiyun port { 701*4882a593Smuzhiyun ov2659_1: endpoint { 702*4882a593Smuzhiyun remote-endpoint = <&vpfe1_ep>; 703*4882a593Smuzhiyun link-frequencies = /bits/ 64 <70000000>; 704*4882a593Smuzhiyun }; 705*4882a593Smuzhiyun }; 706*4882a593Smuzhiyun }; 707*4882a593Smuzhiyun}; 708*4882a593Smuzhiyun 709*4882a593Smuzhiyun&i2c2 { 710*4882a593Smuzhiyun pinctrl-names = "default"; 711*4882a593Smuzhiyun pinctrl-0 = <&i2c2_pins>; 712*4882a593Smuzhiyun status = "okay"; 713*4882a593Smuzhiyun}; 714*4882a593Smuzhiyun 715*4882a593Smuzhiyun&gpio0 { 716*4882a593Smuzhiyun status = "okay"; 717*4882a593Smuzhiyun}; 718*4882a593Smuzhiyun 719*4882a593Smuzhiyun&gpio1 { 720*4882a593Smuzhiyun status = "okay"; 721*4882a593Smuzhiyun}; 722*4882a593Smuzhiyun 723*4882a593Smuzhiyun&gpio2 { 724*4882a593Smuzhiyun pinctrl-names = "default"; 725*4882a593Smuzhiyun pinctrl-0 = <&display_mux_pins>; 726*4882a593Smuzhiyun status = "okay"; 727*4882a593Smuzhiyun 728*4882a593Smuzhiyun p1 { 729*4882a593Smuzhiyun /* 730*4882a593Smuzhiyun * SelLCDorHDMI selects between display and audio paths: 731*4882a593Smuzhiyun * Low: HDMI display with audio via HDMI 732*4882a593Smuzhiyun * High: LCD display with analog audio via aic3111 codec 733*4882a593Smuzhiyun */ 734*4882a593Smuzhiyun gpio-hog; 735*4882a593Smuzhiyun gpios = <1 GPIO_ACTIVE_HIGH>; 736*4882a593Smuzhiyun output-high; 737*4882a593Smuzhiyun line-name = "SelLCDorHDMI"; 738*4882a593Smuzhiyun }; 739*4882a593Smuzhiyun}; 740*4882a593Smuzhiyun 741*4882a593Smuzhiyun&gpio3 { 742*4882a593Smuzhiyun status = "okay"; 743*4882a593Smuzhiyun}; 744*4882a593Smuzhiyun 745*4882a593Smuzhiyun&elm { 746*4882a593Smuzhiyun status = "okay"; 747*4882a593Smuzhiyun}; 748*4882a593Smuzhiyun 749*4882a593Smuzhiyun&gpmc { 750*4882a593Smuzhiyun status = "okay"; /* Disable QSPI when enabling GPMC (NAND) */ 751*4882a593Smuzhiyun pinctrl-names = "default", "sleep"; 752*4882a593Smuzhiyun pinctrl-0 = <&nand_flash_x8_default>; 753*4882a593Smuzhiyun pinctrl-1 = <&nand_flash_x8_sleep>; 754*4882a593Smuzhiyun ranges = <0 0 0x08000000 0x01000000>; /* CS0 space. Min partition = 16MB */ 755*4882a593Smuzhiyun nand@0,0 { 756*4882a593Smuzhiyun compatible = "ti,omap2-nand"; 757*4882a593Smuzhiyun reg = <0 0 4>; /* CS0, offset 0, IO size 4 */ 758*4882a593Smuzhiyun interrupt-parent = <&gpmc>; 759*4882a593Smuzhiyun interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */ 760*4882a593Smuzhiyun <1 IRQ_TYPE_NONE>; /* termcount */ 761*4882a593Smuzhiyun rb-gpios = <&gpmc 0 GPIO_ACTIVE_HIGH>; /* gpmc_wait0 */ 762*4882a593Smuzhiyun ti,nand-xfer-type = "prefetch-dma"; 763*4882a593Smuzhiyun ti,nand-ecc-opt = "bch16"; 764*4882a593Smuzhiyun ti,elm-id = <&elm>; 765*4882a593Smuzhiyun nand-bus-width = <8>; 766*4882a593Smuzhiyun gpmc,device-width = <1>; 767*4882a593Smuzhiyun gpmc,sync-clk-ps = <0>; 768*4882a593Smuzhiyun gpmc,cs-on-ns = <0>; 769*4882a593Smuzhiyun gpmc,cs-rd-off-ns = <40>; /* tCEA + tCHZ + 1 */ 770*4882a593Smuzhiyun gpmc,cs-wr-off-ns = <40>; 771*4882a593Smuzhiyun gpmc,adv-on-ns = <0>; /* cs-on-ns */ 772*4882a593Smuzhiyun gpmc,adv-rd-off-ns = <25>; /* min( tALH + tALS + 1) */ 773*4882a593Smuzhiyun gpmc,adv-wr-off-ns = <25>; /* min( tALH + tALS + 1) */ 774*4882a593Smuzhiyun gpmc,we-on-ns = <0>; /* cs-on-ns */ 775*4882a593Smuzhiyun gpmc,we-off-ns = <20>; /* we-on-time + tWP + 2 */ 776*4882a593Smuzhiyun gpmc,oe-on-ns = <3>; /* cs-on-ns + tRR + 2 */ 777*4882a593Smuzhiyun gpmc,oe-off-ns = <30>; /* oe-on-ns + tRP + 2 */ 778*4882a593Smuzhiyun gpmc,access-ns = <30>; /* tCEA + 4*/ 779*4882a593Smuzhiyun gpmc,rd-cycle-ns = <40>; 780*4882a593Smuzhiyun gpmc,wr-cycle-ns = <40>; 781*4882a593Smuzhiyun gpmc,bus-turnaround-ns = <0>; 782*4882a593Smuzhiyun gpmc,cycle2cycle-delay-ns = <0>; 783*4882a593Smuzhiyun gpmc,clk-activation-ns = <0>; 784*4882a593Smuzhiyun gpmc,wr-access-ns = <40>; 785*4882a593Smuzhiyun gpmc,wr-data-mux-bus-ns = <0>; 786*4882a593Smuzhiyun /* MTD partition table */ 787*4882a593Smuzhiyun /* All SPL-* partitions are sized to minimal length 788*4882a593Smuzhiyun * which can be independently programmable. For 789*4882a593Smuzhiyun * NAND flash this is equal to size of erase-block */ 790*4882a593Smuzhiyun #address-cells = <1>; 791*4882a593Smuzhiyun #size-cells = <1>; 792*4882a593Smuzhiyun partition@0 { 793*4882a593Smuzhiyun label = "NAND.SPL"; 794*4882a593Smuzhiyun reg = <0x00000000 0x00040000>; 795*4882a593Smuzhiyun }; 796*4882a593Smuzhiyun partition@1 { 797*4882a593Smuzhiyun label = "NAND.SPL.backup1"; 798*4882a593Smuzhiyun reg = <0x00040000 0x00040000>; 799*4882a593Smuzhiyun }; 800*4882a593Smuzhiyun partition@2 { 801*4882a593Smuzhiyun label = "NAND.SPL.backup2"; 802*4882a593Smuzhiyun reg = <0x00080000 0x00040000>; 803*4882a593Smuzhiyun }; 804*4882a593Smuzhiyun partition@3 { 805*4882a593Smuzhiyun label = "NAND.SPL.backup3"; 806*4882a593Smuzhiyun reg = <0x000C0000 0x00040000>; 807*4882a593Smuzhiyun }; 808*4882a593Smuzhiyun partition@4 { 809*4882a593Smuzhiyun label = "NAND.u-boot-spl-os"; 810*4882a593Smuzhiyun reg = <0x00100000 0x00080000>; 811*4882a593Smuzhiyun }; 812*4882a593Smuzhiyun partition@5 { 813*4882a593Smuzhiyun label = "NAND.u-boot"; 814*4882a593Smuzhiyun reg = <0x00180000 0x00100000>; 815*4882a593Smuzhiyun }; 816*4882a593Smuzhiyun partition@6 { 817*4882a593Smuzhiyun label = "NAND.u-boot-env"; 818*4882a593Smuzhiyun reg = <0x00280000 0x00040000>; 819*4882a593Smuzhiyun }; 820*4882a593Smuzhiyun partition@7 { 821*4882a593Smuzhiyun label = "NAND.u-boot-env.backup1"; 822*4882a593Smuzhiyun reg = <0x002C0000 0x00040000>; 823*4882a593Smuzhiyun }; 824*4882a593Smuzhiyun partition@8 { 825*4882a593Smuzhiyun label = "NAND.kernel"; 826*4882a593Smuzhiyun reg = <0x00300000 0x00700000>; 827*4882a593Smuzhiyun }; 828*4882a593Smuzhiyun partition@9 { 829*4882a593Smuzhiyun label = "NAND.file-system"; 830*4882a593Smuzhiyun reg = <0x00a00000 0x1f600000>; 831*4882a593Smuzhiyun }; 832*4882a593Smuzhiyun }; 833*4882a593Smuzhiyun}; 834*4882a593Smuzhiyun 835*4882a593Smuzhiyun&epwmss0 { 836*4882a593Smuzhiyun status = "okay"; 837*4882a593Smuzhiyun}; 838*4882a593Smuzhiyun 839*4882a593Smuzhiyun&rtc_target { 840*4882a593Smuzhiyun status = "disabled"; 841*4882a593Smuzhiyun}; 842*4882a593Smuzhiyun 843*4882a593Smuzhiyun&tscadc { 844*4882a593Smuzhiyun status = "okay"; 845*4882a593Smuzhiyun 846*4882a593Smuzhiyun adc { 847*4882a593Smuzhiyun ti,adc-channels = <0 1 2 3 4 5 6 7>; 848*4882a593Smuzhiyun }; 849*4882a593Smuzhiyun}; 850*4882a593Smuzhiyun 851*4882a593Smuzhiyun&ecap0 { 852*4882a593Smuzhiyun status = "okay"; 853*4882a593Smuzhiyun pinctrl-names = "default", "sleep"; 854*4882a593Smuzhiyun pinctrl-0 = <&ecap0_pins_default>; 855*4882a593Smuzhiyun pinctrl-1 = <&ecap0_pins_sleep>; 856*4882a593Smuzhiyun}; 857*4882a593Smuzhiyun 858*4882a593Smuzhiyun&spi0 { 859*4882a593Smuzhiyun status = "okay"; 860*4882a593Smuzhiyun pinctrl-names = "default", "sleep"; 861*4882a593Smuzhiyun pinctrl-0 = <&spi0_pins_default>; 862*4882a593Smuzhiyun pinctrl-1 = <&spi0_pins_sleep>; 863*4882a593Smuzhiyun ti,pindir-d0-out-d1-in; 864*4882a593Smuzhiyun}; 865*4882a593Smuzhiyun 866*4882a593Smuzhiyun&spi1 { 867*4882a593Smuzhiyun status = "okay"; 868*4882a593Smuzhiyun pinctrl-names = "default", "sleep"; 869*4882a593Smuzhiyun pinctrl-0 = <&spi1_pins_default>; 870*4882a593Smuzhiyun pinctrl-1 = <&spi1_pins_sleep>; 871*4882a593Smuzhiyun ti,pindir-d0-out-d1-in; 872*4882a593Smuzhiyun}; 873*4882a593Smuzhiyun 874*4882a593Smuzhiyun&usb2_phy1 { 875*4882a593Smuzhiyun status = "okay"; 876*4882a593Smuzhiyun pinctrl-names = "default", "sleep"; 877*4882a593Smuzhiyun pinctrl-0 = <&usb2_phy1_default>; 878*4882a593Smuzhiyun pinctrl-1 = <&usb2_phy1_sleep>; 879*4882a593Smuzhiyun}; 880*4882a593Smuzhiyun 881*4882a593Smuzhiyun&usb1 { 882*4882a593Smuzhiyun dr_mode = "otg"; 883*4882a593Smuzhiyun status = "okay"; 884*4882a593Smuzhiyun}; 885*4882a593Smuzhiyun 886*4882a593Smuzhiyun&usb2_phy2 { 887*4882a593Smuzhiyun status = "okay"; 888*4882a593Smuzhiyun pinctrl-names = "default", "sleep"; 889*4882a593Smuzhiyun pinctrl-0 = <&usb2_phy2_default>; 890*4882a593Smuzhiyun pinctrl-1 = <&usb2_phy2_sleep>; 891*4882a593Smuzhiyun}; 892*4882a593Smuzhiyun 893*4882a593Smuzhiyun&usb2 { 894*4882a593Smuzhiyun dr_mode = "host"; 895*4882a593Smuzhiyun status = "okay"; 896*4882a593Smuzhiyun}; 897*4882a593Smuzhiyun 898*4882a593Smuzhiyun&qspi { 899*4882a593Smuzhiyun status = "disabled"; /* Disable GPMC (NAND) when enabling QSPI */ 900*4882a593Smuzhiyun pinctrl-names = "default", "sleep"; 901*4882a593Smuzhiyun pinctrl-0 = <&qspi1_pins_default>; 902*4882a593Smuzhiyun pinctrl-1 = <&qspi1_pins_sleep>; 903*4882a593Smuzhiyun 904*4882a593Smuzhiyun spi-max-frequency = <48000000>; 905*4882a593Smuzhiyun m25p80@0 { 906*4882a593Smuzhiyun compatible = "mx66l51235l"; 907*4882a593Smuzhiyun spi-max-frequency = <48000000>; 908*4882a593Smuzhiyun reg = <0>; 909*4882a593Smuzhiyun spi-cpol; 910*4882a593Smuzhiyun spi-cpha; 911*4882a593Smuzhiyun spi-tx-bus-width = <1>; 912*4882a593Smuzhiyun spi-rx-bus-width = <4>; 913*4882a593Smuzhiyun #address-cells = <1>; 914*4882a593Smuzhiyun #size-cells = <1>; 915*4882a593Smuzhiyun 916*4882a593Smuzhiyun /* MTD partition table. 917*4882a593Smuzhiyun * The ROM checks the first 512KiB 918*4882a593Smuzhiyun * for a valid file to boot(XIP). 919*4882a593Smuzhiyun */ 920*4882a593Smuzhiyun partition@0 { 921*4882a593Smuzhiyun label = "QSPI.U_BOOT"; 922*4882a593Smuzhiyun reg = <0x00000000 0x000080000>; 923*4882a593Smuzhiyun }; 924*4882a593Smuzhiyun partition@1 { 925*4882a593Smuzhiyun label = "QSPI.U_BOOT.backup"; 926*4882a593Smuzhiyun reg = <0x00080000 0x00080000>; 927*4882a593Smuzhiyun }; 928*4882a593Smuzhiyun partition@2 { 929*4882a593Smuzhiyun label = "QSPI.U-BOOT-SPL_OS"; 930*4882a593Smuzhiyun reg = <0x00100000 0x00010000>; 931*4882a593Smuzhiyun }; 932*4882a593Smuzhiyun partition@3 { 933*4882a593Smuzhiyun label = "QSPI.U_BOOT_ENV"; 934*4882a593Smuzhiyun reg = <0x00110000 0x00010000>; 935*4882a593Smuzhiyun }; 936*4882a593Smuzhiyun partition@4 { 937*4882a593Smuzhiyun label = "QSPI.U-BOOT-ENV.backup"; 938*4882a593Smuzhiyun reg = <0x00120000 0x00010000>; 939*4882a593Smuzhiyun }; 940*4882a593Smuzhiyun partition@5 { 941*4882a593Smuzhiyun label = "QSPI.KERNEL"; 942*4882a593Smuzhiyun reg = <0x00130000 0x0800000>; 943*4882a593Smuzhiyun }; 944*4882a593Smuzhiyun partition@6 { 945*4882a593Smuzhiyun label = "QSPI.FILESYSTEM"; 946*4882a593Smuzhiyun reg = <0x00930000 0x36D0000>; 947*4882a593Smuzhiyun }; 948*4882a593Smuzhiyun }; 949*4882a593Smuzhiyun}; 950*4882a593Smuzhiyun 951*4882a593Smuzhiyun&hdq { 952*4882a593Smuzhiyun status = "okay"; 953*4882a593Smuzhiyun pinctrl-names = "default"; 954*4882a593Smuzhiyun pinctrl-0 = <&hdq_pins>; 955*4882a593Smuzhiyun}; 956*4882a593Smuzhiyun 957*4882a593Smuzhiyun&dss { 958*4882a593Smuzhiyun status = "okay"; 959*4882a593Smuzhiyun 960*4882a593Smuzhiyun pinctrl-names = "default"; 961*4882a593Smuzhiyun pinctrl-0 = <&dss_pins>; 962*4882a593Smuzhiyun 963*4882a593Smuzhiyun port { 964*4882a593Smuzhiyun dpi_out: endpoint { 965*4882a593Smuzhiyun remote-endpoint = <&lcd_in>; 966*4882a593Smuzhiyun data-lines = <24>; 967*4882a593Smuzhiyun }; 968*4882a593Smuzhiyun }; 969*4882a593Smuzhiyun}; 970*4882a593Smuzhiyun 971*4882a593Smuzhiyun&vpfe1 { 972*4882a593Smuzhiyun status = "okay"; 973*4882a593Smuzhiyun pinctrl-names = "default", "sleep"; 974*4882a593Smuzhiyun pinctrl-0 = <&vpfe1_pins_default>; 975*4882a593Smuzhiyun pinctrl-1 = <&vpfe1_pins_sleep>; 976*4882a593Smuzhiyun 977*4882a593Smuzhiyun port { 978*4882a593Smuzhiyun vpfe1_ep: endpoint { 979*4882a593Smuzhiyun remote-endpoint = <&ov2659_1>; 980*4882a593Smuzhiyun ti,am437x-vpfe-interface = <0>; 981*4882a593Smuzhiyun bus-width = <8>; 982*4882a593Smuzhiyun hsync-active = <0>; 983*4882a593Smuzhiyun vsync-active = <0>; 984*4882a593Smuzhiyun }; 985*4882a593Smuzhiyun }; 986*4882a593Smuzhiyun}; 987*4882a593Smuzhiyun 988*4882a593Smuzhiyun&uart0 { 989*4882a593Smuzhiyun status = "okay"; 990*4882a593Smuzhiyun pinctrl-names = "default", "sleep"; 991*4882a593Smuzhiyun pinctrl-0 = <&uart0_pins_default>; 992*4882a593Smuzhiyun pinctrl-1 = <&uart0_pins_sleep>; 993*4882a593Smuzhiyun}; 994*4882a593Smuzhiyun 995*4882a593Smuzhiyun&mcasp1 { 996*4882a593Smuzhiyun #sound-dai-cells = <0>; 997*4882a593Smuzhiyun pinctrl-names = "default", "sleep"; 998*4882a593Smuzhiyun pinctrl-0 = <&mcasp1_pins>; 999*4882a593Smuzhiyun pinctrl-1 = <&mcasp1_sleep_pins>; 1000*4882a593Smuzhiyun 1001*4882a593Smuzhiyun status = "okay"; 1002*4882a593Smuzhiyun 1003*4882a593Smuzhiyun op-mode = <0>; /* MCASP_IIS_MODE */ 1004*4882a593Smuzhiyun tdm-slots = <2>; 1005*4882a593Smuzhiyun /* 4 serializer */ 1006*4882a593Smuzhiyun serial-dir = < /* 0: INACTIVE, 1: TX, 2: RX */ 1007*4882a593Smuzhiyun 1 2 0 0 1008*4882a593Smuzhiyun >; 1009*4882a593Smuzhiyun tx-num-evt = <32>; 1010*4882a593Smuzhiyun rx-num-evt = <32>; 1011*4882a593Smuzhiyun}; 1012*4882a593Smuzhiyun 1013*4882a593Smuzhiyun&mux_synctimer32k_ck { 1014*4882a593Smuzhiyun assigned-clocks = <&mux_synctimer32k_ck>; 1015*4882a593Smuzhiyun assigned-clock-parents = <&clkdiv32k_ick>; 1016*4882a593Smuzhiyun}; 1017*4882a593Smuzhiyun 1018*4882a593Smuzhiyun&cpu { 1019*4882a593Smuzhiyun cpu0-supply = <&dcdc2>; 1020*4882a593Smuzhiyun}; 1021