1*4882a593Smuzhiyun// SPDX-License-Identifier: GPL-2.0-only 2*4882a593Smuzhiyun/* 3*4882a593Smuzhiyun * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/ 4*4882a593Smuzhiyun */ 5*4882a593Smuzhiyun 6*4882a593Smuzhiyun/* 7*4882a593Smuzhiyun * VScom OnRISC 8*4882a593Smuzhiyun * http://www.vscom.de 9*4882a593Smuzhiyun */ 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun/dts-v1/; 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun#include "am335x-baltos.dtsi" 14*4882a593Smuzhiyun#include "am335x-baltos-leds.dtsi" 15*4882a593Smuzhiyun 16*4882a593Smuzhiyun/ { 17*4882a593Smuzhiyun model = "NetCom Plus"; 18*4882a593Smuzhiyun}; 19*4882a593Smuzhiyun 20*4882a593Smuzhiyun&am33xx_pinmux { 21*4882a593Smuzhiyun uart1_pins: pinmux_uart1_pins { 22*4882a593Smuzhiyun pinctrl-single,pins = < 23*4882a593Smuzhiyun AM33XX_PADCONF(AM335X_PIN_UART1_RXD, PIN_INPUT, MUX_MODE0) /* RX */ 24*4882a593Smuzhiyun AM33XX_PADCONF(AM335X_PIN_UART1_TXD, PIN_INPUT, MUX_MODE0) /* TX */ 25*4882a593Smuzhiyun AM33XX_PADCONF(AM335X_PIN_UART1_CTSN, PIN_INPUT_PULLDOWN, MUX_MODE0) /* CTS */ 26*4882a593Smuzhiyun AM33XX_PADCONF(AM335X_PIN_UART1_RTSN, PIN_OUTPUT_PULLDOWN, MUX_MODE0) /* RTS */ 27*4882a593Smuzhiyun AM33XX_PADCONF(AM335X_PIN_LCD_VSYNC, PIN_OUTPUT_PULLDOWN, MUX_MODE7) /* DTR */ 28*4882a593Smuzhiyun AM33XX_PADCONF(AM335X_PIN_LCD_HSYNC, PIN_INPUT_PULLDOWN, MUX_MODE7) /* DSR */ 29*4882a593Smuzhiyun AM33XX_PADCONF(AM335X_PIN_LCD_PCLK, PIN_INPUT_PULLDOWN, MUX_MODE7) /* DCD */ 30*4882a593Smuzhiyun AM33XX_PADCONF(AM335X_PIN_LCD_AC_BIAS_EN, PIN_INPUT_PULLDOWN, MUX_MODE7) /* RI */ 31*4882a593Smuzhiyun >; 32*4882a593Smuzhiyun }; 33*4882a593Smuzhiyun 34*4882a593Smuzhiyun uart2_pins: pinmux_uart2_pins { 35*4882a593Smuzhiyun pinctrl-single,pins = < 36*4882a593Smuzhiyun AM33XX_PADCONF(AM335X_PIN_SPI0_SCLK, PIN_INPUT, MUX_MODE1) /* RX */ 37*4882a593Smuzhiyun AM33XX_PADCONF(AM335X_PIN_SPI0_D0, PIN_OUTPUT, MUX_MODE1) /* TX */ 38*4882a593Smuzhiyun AM33XX_PADCONF(AM335X_PIN_I2C0_SDA, PIN_INPUT_PULLDOWN, MUX_MODE2) /* CTS */ 39*4882a593Smuzhiyun AM33XX_PADCONF(AM335X_PIN_I2C0_SCL, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* RTS */ 40*4882a593Smuzhiyun AM33XX_PADCONF(AM335X_PIN_GPMC_AD12, PIN_OUTPUT_PULLDOWN, MUX_MODE7) /* DTR */ 41*4882a593Smuzhiyun AM33XX_PADCONF(AM335X_PIN_GPMC_AD13, PIN_INPUT_PULLDOWN, MUX_MODE7) /* DSR */ 42*4882a593Smuzhiyun AM33XX_PADCONF(AM335X_PIN_GPMC_AD14, PIN_INPUT_PULLDOWN, MUX_MODE7) /* DCD */ 43*4882a593Smuzhiyun AM33XX_PADCONF(AM335X_PIN_GPMC_AD15, PIN_INPUT_PULLDOWN, MUX_MODE7) /* RI */ 44*4882a593Smuzhiyun >; 45*4882a593Smuzhiyun }; 46*4882a593Smuzhiyun}; 47*4882a593Smuzhiyun 48*4882a593Smuzhiyun&usb0_phy { 49*4882a593Smuzhiyun status = "okay"; 50*4882a593Smuzhiyun}; 51*4882a593Smuzhiyun 52*4882a593Smuzhiyun&usb0 { 53*4882a593Smuzhiyun status = "okay"; 54*4882a593Smuzhiyun dr_mode = "host"; 55*4882a593Smuzhiyun}; 56*4882a593Smuzhiyun 57*4882a593Smuzhiyun&uart1 { 58*4882a593Smuzhiyun pinctrl-names = "default"; 59*4882a593Smuzhiyun pinctrl-0 = <&uart1_pins>; 60*4882a593Smuzhiyun dtr-gpios = <&gpio2 22 GPIO_ACTIVE_LOW>; 61*4882a593Smuzhiyun dsr-gpios = <&gpio2 23 GPIO_ACTIVE_LOW>; 62*4882a593Smuzhiyun dcd-gpios = <&gpio2 24 GPIO_ACTIVE_LOW>; 63*4882a593Smuzhiyun rng-gpios = <&gpio2 25 GPIO_ACTIVE_LOW>; 64*4882a593Smuzhiyun 65*4882a593Smuzhiyun status = "okay"; 66*4882a593Smuzhiyun}; 67*4882a593Smuzhiyun 68*4882a593Smuzhiyun&uart2 { 69*4882a593Smuzhiyun pinctrl-names = "default"; 70*4882a593Smuzhiyun pinctrl-0 = <&uart2_pins>; 71*4882a593Smuzhiyun dtr-gpios = <&gpio1 12 GPIO_ACTIVE_LOW>; 72*4882a593Smuzhiyun dsr-gpios = <&gpio1 13 GPIO_ACTIVE_LOW>; 73*4882a593Smuzhiyun dcd-gpios = <&gpio1 14 GPIO_ACTIVE_LOW>; 74*4882a593Smuzhiyun rng-gpios = <&gpio1 15 GPIO_ACTIVE_LOW>; 75*4882a593Smuzhiyun 76*4882a593Smuzhiyun status = "okay"; 77*4882a593Smuzhiyun}; 78*4882a593Smuzhiyun 79*4882a593Smuzhiyun&davinci_mdio { 80*4882a593Smuzhiyun phy0: ethernet-phy@0 { 81*4882a593Smuzhiyun reg = <1>; 82*4882a593Smuzhiyun }; 83*4882a593Smuzhiyun}; 84*4882a593Smuzhiyun 85*4882a593Smuzhiyun&cpsw_emac0 { 86*4882a593Smuzhiyun phy-mode = "rmii"; 87*4882a593Smuzhiyun dual_emac_res_vlan = <1>; 88*4882a593Smuzhiyun phy-handle = <&phy0>; 89*4882a593Smuzhiyun}; 90*4882a593Smuzhiyun 91*4882a593Smuzhiyun&cpsw_emac1 { 92*4882a593Smuzhiyun phy-mode = "rgmii-id"; 93*4882a593Smuzhiyun dual_emac_res_vlan = <2>; 94*4882a593Smuzhiyun phy-handle = <&phy1>; 95*4882a593Smuzhiyun}; 96