1*4882a593Smuzhiyun// SPDX-License-Identifier: GPL-2.0 2*4882a593Smuzhiyun/* 3*4882a593Smuzhiyun * Copyright (C) 2018 MOXA Inc. - https://www.moxa.com/ 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Authors: SZ Lin (林上智) <sz.lin@moxa.com> 6*4882a593Smuzhiyun * Wes Huang (黃淵河) <wes.huang@moxa.com> 7*4882a593Smuzhiyun * Fero JD Zhou (周俊達) <FeroJD.Zhou@moxa.com> 8*4882a593Smuzhiyun */ 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun#include "am33xx.dtsi" 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun/ { 13*4882a593Smuzhiyun vbat: vbat-regulator { 14*4882a593Smuzhiyun compatible = "regulator-fixed"; 15*4882a593Smuzhiyun }; 16*4882a593Smuzhiyun 17*4882a593Smuzhiyun /* Power supply provides a fixed 3.3V @3A */ 18*4882a593Smuzhiyun vmmcsd_fixed: vmmcsd-regulator { 19*4882a593Smuzhiyun compatible = "regulator-fixed"; 20*4882a593Smuzhiyun regulator-name = "vmmcsd_fixed"; 21*4882a593Smuzhiyun regulator-min-microvolt = <3300000>; 22*4882a593Smuzhiyun regulator-max-microvolt = <3300000>; 23*4882a593Smuzhiyun regulator-boot-on; 24*4882a593Smuzhiyun }; 25*4882a593Smuzhiyun 26*4882a593Smuzhiyun buttons: push_button { 27*4882a593Smuzhiyun compatible = "gpio-keys"; 28*4882a593Smuzhiyun }; 29*4882a593Smuzhiyun}; 30*4882a593Smuzhiyun 31*4882a593Smuzhiyun&am33xx_pinmux { 32*4882a593Smuzhiyun pinctrl-names = "default"; 33*4882a593Smuzhiyun 34*4882a593Smuzhiyun i2c0_pins: pinmux_i2c0_pins { 35*4882a593Smuzhiyun pinctrl-single,pins = < 36*4882a593Smuzhiyun AM33XX_PADCONF(AM335X_PIN_I2C0_SDA, PIN_INPUT_PULLUP, MUX_MODE0) 37*4882a593Smuzhiyun AM33XX_PADCONF(AM335X_PIN_I2C0_SCL, PIN_INPUT_PULLUP, MUX_MODE0) 38*4882a593Smuzhiyun >; 39*4882a593Smuzhiyun }; 40*4882a593Smuzhiyun 41*4882a593Smuzhiyun push_button_pins: pinmux_push_button { 42*4882a593Smuzhiyun pinctrl-single,pins = < 43*4882a593Smuzhiyun AM33XX_PADCONF(AM335X_PIN_LCD_HSYNC, PIN_INPUT_PULLDOWN, MUX_MODE7) /* lcd_hsync.gpio2_23 */ 44*4882a593Smuzhiyun >; 45*4882a593Smuzhiyun }; 46*4882a593Smuzhiyun 47*4882a593Smuzhiyun uart0_pins: pinmux_uart0_pins { 48*4882a593Smuzhiyun pinctrl-single,pins = < 49*4882a593Smuzhiyun AM33XX_PADCONF(AM335X_PIN_UART0_RXD, PIN_INPUT_PULLUP, MUX_MODE0) 50*4882a593Smuzhiyun AM33XX_PADCONF(AM335X_PIN_UART0_TXD, PIN_OUTPUT_PULLDOWN, MUX_MODE0) 51*4882a593Smuzhiyun >; 52*4882a593Smuzhiyun }; 53*4882a593Smuzhiyun 54*4882a593Smuzhiyun davinci_mdio_default: davinci_mdio_default { 55*4882a593Smuzhiyun pinctrl-single,pins = < 56*4882a593Smuzhiyun /* MDIO */ 57*4882a593Smuzhiyun AM33XX_PADCONF(AM335X_PIN_MDIO, PIN_INPUT_PULLUP | SLEWCTRL_FAST, MUX_MODE0) 58*4882a593Smuzhiyun AM33XX_PADCONF(AM335X_PIN_MDC, PIN_OUTPUT_PULLUP, MUX_MODE0) 59*4882a593Smuzhiyun >; 60*4882a593Smuzhiyun }; 61*4882a593Smuzhiyun 62*4882a593Smuzhiyun mmc1_pins_default: pinmux_mmc1_pins { 63*4882a593Smuzhiyun pinctrl-single,pins = < 64*4882a593Smuzhiyun /* eMMC */ 65*4882a593Smuzhiyun AM33XX_PADCONF(AM335X_PIN_GPMC_AD0, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad12.mmc1_dat0 */ 66*4882a593Smuzhiyun AM33XX_PADCONF(AM335X_PIN_GPMC_AD1, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad13.mmc1_dat1 */ 67*4882a593Smuzhiyun AM33XX_PADCONF(AM335X_PIN_GPMC_AD2, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad14.mmc1_dat2 */ 68*4882a593Smuzhiyun AM33XX_PADCONF(AM335X_PIN_GPMC_AD3, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad15.mmc1_dat3 */ 69*4882a593Smuzhiyun AM33XX_PADCONF(AM335X_PIN_GPMC_AD4, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad8.mmc1_dat4 */ 70*4882a593Smuzhiyun AM33XX_PADCONF(AM335X_PIN_GPMC_AD5, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad9.mmc1_dat5 */ 71*4882a593Smuzhiyun AM33XX_PADCONF(AM335X_PIN_GPMC_AD6, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad10.mmc1_dat6 */ 72*4882a593Smuzhiyun AM33XX_PADCONF(AM335X_PIN_GPMC_AD7, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad11.mmc1_dat7 */ 73*4882a593Smuzhiyun AM33XX_PADCONF(AM335X_PIN_GPMC_CSN2, PIN_INPUT_PULLUP, MUX_MODE2) /* gpmc_csn2.mmc1_cmd */ 74*4882a593Smuzhiyun AM33XX_PADCONF(AM335X_PIN_GPMC_CSN1, PIN_INPUT_PULLUP, MUX_MODE2) /* gpmc_csn1.mmc1_clk */ 75*4882a593Smuzhiyun >; 76*4882a593Smuzhiyun }; 77*4882a593Smuzhiyun 78*4882a593Smuzhiyun spi0_pins: pinmux_spi0 { 79*4882a593Smuzhiyun pinctrl-single,pins = < 80*4882a593Smuzhiyun AM33XX_PADCONF(AM335X_PIN_SPI0_SCLK, PIN_INPUT_PULLUP, MUX_MODE0) 81*4882a593Smuzhiyun AM33XX_PADCONF(AM335X_PIN_SPI0_CS0, PIN_INPUT_PULLUP, MUX_MODE0) 82*4882a593Smuzhiyun AM33XX_PADCONF(AM335X_PIN_SPI0_D0, PIN_INPUT_PULLUP, MUX_MODE0) 83*4882a593Smuzhiyun AM33XX_PADCONF(AM335X_PIN_SPI0_D1, PIN_INPUT_PULLUP, MUX_MODE0) 84*4882a593Smuzhiyun >; 85*4882a593Smuzhiyun }; 86*4882a593Smuzhiyun}; 87*4882a593Smuzhiyun 88*4882a593Smuzhiyun&uart0 { 89*4882a593Smuzhiyun /* Console */ 90*4882a593Smuzhiyun status = "okay"; 91*4882a593Smuzhiyun pinctrl-names = "default"; 92*4882a593Smuzhiyun pinctrl-0 = <&uart0_pins>; 93*4882a593Smuzhiyun}; 94*4882a593Smuzhiyun 95*4882a593Smuzhiyun&i2c0 { 96*4882a593Smuzhiyun pinctrl-names = "default"; 97*4882a593Smuzhiyun pinctrl-0 = <&i2c0_pins>; 98*4882a593Smuzhiyun 99*4882a593Smuzhiyun status = "okay"; 100*4882a593Smuzhiyun clock-frequency = <400000>; 101*4882a593Smuzhiyun 102*4882a593Smuzhiyun eeprom: eeprom@50 { 103*4882a593Smuzhiyun compatible = "atmel,24c16"; 104*4882a593Smuzhiyun pagesize = <16>; 105*4882a593Smuzhiyun reg = <0x50>; 106*4882a593Smuzhiyun }; 107*4882a593Smuzhiyun 108*4882a593Smuzhiyun rtc_wdt: rtc_wdt@68 { 109*4882a593Smuzhiyun compatible = "dallas,ds1374"; 110*4882a593Smuzhiyun reg = <0x68>; 111*4882a593Smuzhiyun }; 112*4882a593Smuzhiyun}; 113*4882a593Smuzhiyun 114*4882a593Smuzhiyun&usb0 { 115*4882a593Smuzhiyun dr_mode = "host"; 116*4882a593Smuzhiyun}; 117*4882a593Smuzhiyun 118*4882a593Smuzhiyun/* Power */ 119*4882a593Smuzhiyun&vbat { 120*4882a593Smuzhiyun regulator-name = "vbat"; 121*4882a593Smuzhiyun regulator-min-microvolt = <5000000>; 122*4882a593Smuzhiyun regulator-max-microvolt = <5000000>; 123*4882a593Smuzhiyun}; 124*4882a593Smuzhiyun 125*4882a593Smuzhiyun&mac { 126*4882a593Smuzhiyun pinctrl-names = "default"; 127*4882a593Smuzhiyun pinctrl-0 = <&cpsw_default>; 128*4882a593Smuzhiyun status = "okay"; 129*4882a593Smuzhiyun}; 130*4882a593Smuzhiyun 131*4882a593Smuzhiyun&davinci_mdio { 132*4882a593Smuzhiyun pinctrl-names = "default"; 133*4882a593Smuzhiyun pinctrl-0 = <&davinci_mdio_default>; 134*4882a593Smuzhiyun status = "okay"; 135*4882a593Smuzhiyun}; 136*4882a593Smuzhiyun 137*4882a593Smuzhiyun&cpsw_emac0 { 138*4882a593Smuzhiyun status = "okay"; 139*4882a593Smuzhiyun}; 140*4882a593Smuzhiyun 141*4882a593Smuzhiyun&cpsw_emac1 { 142*4882a593Smuzhiyun status = "okay"; 143*4882a593Smuzhiyun}; 144*4882a593Smuzhiyun 145*4882a593Smuzhiyun&sham { 146*4882a593Smuzhiyun status = "okay"; 147*4882a593Smuzhiyun}; 148*4882a593Smuzhiyun 149*4882a593Smuzhiyun&aes { 150*4882a593Smuzhiyun status = "okay"; 151*4882a593Smuzhiyun}; 152*4882a593Smuzhiyun 153*4882a593Smuzhiyun&gpio0_target { 154*4882a593Smuzhiyun ti,no-reset-on-init; 155*4882a593Smuzhiyun}; 156*4882a593Smuzhiyun 157*4882a593Smuzhiyun&mmc2 { 158*4882a593Smuzhiyun pinctrl-names = "default"; 159*4882a593Smuzhiyun vmmc-supply = <&vmmcsd_fixed>; 160*4882a593Smuzhiyun bus-width = <8>; 161*4882a593Smuzhiyun pinctrl-0 = <&mmc1_pins_default>; 162*4882a593Smuzhiyun non-removable; 163*4882a593Smuzhiyun status = "okay"; 164*4882a593Smuzhiyun}; 165*4882a593Smuzhiyun 166*4882a593Smuzhiyun&buttons { 167*4882a593Smuzhiyun pinctrl-names = "default"; 168*4882a593Smuzhiyun pinctrl-0 = <&push_button_pins>; 169*4882a593Smuzhiyun #address-cells = <1>; 170*4882a593Smuzhiyun #size-cells = <0>; 171*4882a593Smuzhiyun 172*4882a593Smuzhiyun button@0 { 173*4882a593Smuzhiyun label = "push_button"; 174*4882a593Smuzhiyun linux,code = <0x100>; 175*4882a593Smuzhiyun gpios = <&gpio2 23 GPIO_ACTIVE_LOW>; 176*4882a593Smuzhiyun }; 177*4882a593Smuzhiyun}; 178*4882a593Smuzhiyun 179*4882a593Smuzhiyun/* SPI Busses */ 180*4882a593Smuzhiyun&spi0 { 181*4882a593Smuzhiyun status = "okay"; 182*4882a593Smuzhiyun pinctrl-names = "default"; 183*4882a593Smuzhiyun pinctrl-0 = <&spi0_pins>; 184*4882a593Smuzhiyun 185*4882a593Smuzhiyun m25p80@0 { 186*4882a593Smuzhiyun compatible = "mx25l6405d"; 187*4882a593Smuzhiyun spi-max-frequency = <40000000>; 188*4882a593Smuzhiyun 189*4882a593Smuzhiyun reg = <0>; 190*4882a593Smuzhiyun spi-cpol; 191*4882a593Smuzhiyun spi-cpha; 192*4882a593Smuzhiyun 193*4882a593Smuzhiyun partitions { 194*4882a593Smuzhiyun compatible = "fixed-partitions"; 195*4882a593Smuzhiyun #address-cells = <1>; 196*4882a593Smuzhiyun #size-cells = <1>; 197*4882a593Smuzhiyun 198*4882a593Smuzhiyun /* reg : The partition's offset and size within the mtd bank. */ 199*4882a593Smuzhiyun partitions@0 { 200*4882a593Smuzhiyun label = "MLO"; 201*4882a593Smuzhiyun reg = <0x0 0x80000>; 202*4882a593Smuzhiyun }; 203*4882a593Smuzhiyun 204*4882a593Smuzhiyun partitions@1 { 205*4882a593Smuzhiyun label = "U-Boot"; 206*4882a593Smuzhiyun reg = <0x80000 0x100000>; 207*4882a593Smuzhiyun }; 208*4882a593Smuzhiyun 209*4882a593Smuzhiyun partitions@2 { 210*4882a593Smuzhiyun label = "U-Boot Env"; 211*4882a593Smuzhiyun reg = <0x180000 0x40000>; 212*4882a593Smuzhiyun }; 213*4882a593Smuzhiyun }; 214*4882a593Smuzhiyun }; 215*4882a593Smuzhiyun}; 216*4882a593Smuzhiyun 217*4882a593Smuzhiyun&spi1 { 218*4882a593Smuzhiyun status = "okay"; 219*4882a593Smuzhiyun pinctrl-names = "default"; 220*4882a593Smuzhiyun pinctrl-0 = <&spi1_pins>; 221*4882a593Smuzhiyun 222*4882a593Smuzhiyun tpm_spi_tis@0 { 223*4882a593Smuzhiyun compatible = "tcg,tpm_tis-spi"; 224*4882a593Smuzhiyun reg = <0>; 225*4882a593Smuzhiyun spi-max-frequency = <500000>; 226*4882a593Smuzhiyun }; 227*4882a593Smuzhiyun}; 228