1*4882a593Smuzhiyun// SPDX-License-Identifier: GPL-2.0-only 2*4882a593Smuzhiyun/* 3*4882a593Smuzhiyun * am335x-cm-t335.dts - Device Tree file for Compulab CM-T335 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Copyright (C) 2014 - 2015 CompuLab Ltd. - http://www.compulab.co.il/ 6*4882a593Smuzhiyun */ 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun/dts-v1/; 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun#include "am33xx.dtsi" 11*4882a593Smuzhiyun#include <dt-bindings/interrupt-controller/irq.h> 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun/ { 14*4882a593Smuzhiyun model = "CompuLab CM-T335"; 15*4882a593Smuzhiyun compatible = "compulab,cm-t335", "ti,am33xx"; 16*4882a593Smuzhiyun 17*4882a593Smuzhiyun memory@80000000 { 18*4882a593Smuzhiyun device_type = "memory"; 19*4882a593Smuzhiyun reg = <0x80000000 0x8000000>; /* 128 MB */ 20*4882a593Smuzhiyun }; 21*4882a593Smuzhiyun 22*4882a593Smuzhiyun leds { 23*4882a593Smuzhiyun compatible = "gpio-leds"; 24*4882a593Smuzhiyun pinctrl-names = "default"; 25*4882a593Smuzhiyun pinctrl-0 = <&gpio_led_pins>; 26*4882a593Smuzhiyun led0 { 27*4882a593Smuzhiyun label = "cm_t335:green"; 28*4882a593Smuzhiyun gpios = <&gpio2 0 GPIO_ACTIVE_LOW>; /* gpio2_0 */ 29*4882a593Smuzhiyun linux,default-trigger = "heartbeat"; 30*4882a593Smuzhiyun }; 31*4882a593Smuzhiyun }; 32*4882a593Smuzhiyun 33*4882a593Smuzhiyun /* regulator for mmc */ 34*4882a593Smuzhiyun vmmc_fixed: fixedregulator0 { 35*4882a593Smuzhiyun compatible = "regulator-fixed"; 36*4882a593Smuzhiyun regulator-name = "vmmc_fixed"; 37*4882a593Smuzhiyun regulator-min-microvolt = <3300000>; 38*4882a593Smuzhiyun regulator-max-microvolt = <3300000>; 39*4882a593Smuzhiyun }; 40*4882a593Smuzhiyun 41*4882a593Smuzhiyun /* Regulator for WiFi */ 42*4882a593Smuzhiyun vwlan_fixed: fixedregulator2 { 43*4882a593Smuzhiyun compatible = "regulator-fixed"; 44*4882a593Smuzhiyun regulator-name = "vwlan_fixed"; 45*4882a593Smuzhiyun gpio = <&gpio0 20 GPIO_ACTIVE_HIGH>; /* gpio0_20 */ 46*4882a593Smuzhiyun enable-active-high; 47*4882a593Smuzhiyun }; 48*4882a593Smuzhiyun 49*4882a593Smuzhiyun backlight { 50*4882a593Smuzhiyun compatible = "pwm-backlight"; 51*4882a593Smuzhiyun pwms = <&ecap0 0 50000 0>; 52*4882a593Smuzhiyun brightness-levels = <0 51 53 56 62 75 101 152 255>; 53*4882a593Smuzhiyun default-brightness-level = <8>; 54*4882a593Smuzhiyun }; 55*4882a593Smuzhiyun 56*4882a593Smuzhiyun sound { 57*4882a593Smuzhiyun compatible = "simple-audio-card"; 58*4882a593Smuzhiyun simple-audio-card,name = "cm-t335"; 59*4882a593Smuzhiyun 60*4882a593Smuzhiyun simple-audio-card,widgets = 61*4882a593Smuzhiyun "Microphone", "Mic Jack", 62*4882a593Smuzhiyun "Line", "Line In", 63*4882a593Smuzhiyun "Headphone", "Headphone Jack"; 64*4882a593Smuzhiyun 65*4882a593Smuzhiyun simple-audio-card,routing = 66*4882a593Smuzhiyun "Headphone Jack", "LHPOUT", 67*4882a593Smuzhiyun "Headphone Jack", "RHPOUT", 68*4882a593Smuzhiyun "LLINEIN", "Line In", 69*4882a593Smuzhiyun "RLINEIN", "Line In", 70*4882a593Smuzhiyun "MICIN", "Mic Jack"; 71*4882a593Smuzhiyun 72*4882a593Smuzhiyun simple-audio-card,format = "i2s"; 73*4882a593Smuzhiyun simple-audio-card,bitclock-master = <&sound_master>; 74*4882a593Smuzhiyun simple-audio-card,frame-master = <&sound_master>; 75*4882a593Smuzhiyun 76*4882a593Smuzhiyun simple-audio-card,cpu { 77*4882a593Smuzhiyun sound-dai = <&mcasp1>; 78*4882a593Smuzhiyun }; 79*4882a593Smuzhiyun 80*4882a593Smuzhiyun sound_master: simple-audio-card,codec { 81*4882a593Smuzhiyun sound-dai = <&tlv320aic23>; 82*4882a593Smuzhiyun system-clock-frequency = <12000000>; 83*4882a593Smuzhiyun }; 84*4882a593Smuzhiyun }; 85*4882a593Smuzhiyun}; 86*4882a593Smuzhiyun 87*4882a593Smuzhiyun&am33xx_pinmux { 88*4882a593Smuzhiyun pinctrl-names = "default"; 89*4882a593Smuzhiyun pinctrl-0 = <&bluetooth_pins>; 90*4882a593Smuzhiyun 91*4882a593Smuzhiyun i2c0_pins: pinmux_i2c0_pins { 92*4882a593Smuzhiyun pinctrl-single,pins = < 93*4882a593Smuzhiyun AM33XX_PADCONF(AM335X_PIN_I2C0_SDA, PIN_INPUT_PULLUP, MUX_MODE0) 94*4882a593Smuzhiyun AM33XX_PADCONF(AM335X_PIN_I2C0_SCL, PIN_INPUT_PULLUP, MUX_MODE0) 95*4882a593Smuzhiyun >; 96*4882a593Smuzhiyun }; 97*4882a593Smuzhiyun 98*4882a593Smuzhiyun i2c1_pins: pinmux_i2c1_pins { 99*4882a593Smuzhiyun pinctrl-single,pins = < 100*4882a593Smuzhiyun /* uart0_ctsn.i2c1_sda */ 101*4882a593Smuzhiyun AM33XX_PADCONF(AM335X_PIN_UART0_CTSN, PIN_INPUT_PULLUP, MUX_MODE2) 102*4882a593Smuzhiyun /* uart0_rtsn.i2c1_scl */ 103*4882a593Smuzhiyun AM33XX_PADCONF(AM335X_PIN_UART0_RTSN, PIN_INPUT_PULLUP, MUX_MODE2) 104*4882a593Smuzhiyun >; 105*4882a593Smuzhiyun }; 106*4882a593Smuzhiyun 107*4882a593Smuzhiyun gpio_led_pins: pinmux_gpio_led_pins { 108*4882a593Smuzhiyun pinctrl-single,pins = < 109*4882a593Smuzhiyun /* gpmc_csn3.gpio2_0 */ 110*4882a593Smuzhiyun AM33XX_PADCONF(AM335X_PIN_GPMC_CSN3, PIN_OUTPUT, MUX_MODE7) 111*4882a593Smuzhiyun >; 112*4882a593Smuzhiyun }; 113*4882a593Smuzhiyun 114*4882a593Smuzhiyun nandflash_pins: pinmux_nandflash_pins { 115*4882a593Smuzhiyun pinctrl-single,pins = < 116*4882a593Smuzhiyun AM33XX_PADCONF(AM335X_PIN_GPMC_AD0, PIN_INPUT_PULLUP, MUX_MODE0) 117*4882a593Smuzhiyun AM33XX_PADCONF(AM335X_PIN_GPMC_AD1, PIN_INPUT_PULLUP, MUX_MODE0) 118*4882a593Smuzhiyun AM33XX_PADCONF(AM335X_PIN_GPMC_AD2, PIN_INPUT_PULLUP, MUX_MODE0) 119*4882a593Smuzhiyun AM33XX_PADCONF(AM335X_PIN_GPMC_AD3, PIN_INPUT_PULLUP, MUX_MODE0) 120*4882a593Smuzhiyun AM33XX_PADCONF(AM335X_PIN_GPMC_AD4, PIN_INPUT_PULLUP, MUX_MODE0) 121*4882a593Smuzhiyun AM33XX_PADCONF(AM335X_PIN_GPMC_AD5, PIN_INPUT_PULLUP, MUX_MODE0) 122*4882a593Smuzhiyun AM33XX_PADCONF(AM335X_PIN_GPMC_AD6, PIN_INPUT_PULLUP, MUX_MODE0) 123*4882a593Smuzhiyun AM33XX_PADCONF(AM335X_PIN_GPMC_AD7, PIN_INPUT_PULLUP, MUX_MODE0) 124*4882a593Smuzhiyun AM33XX_PADCONF(AM335X_PIN_GPMC_WAIT0, PIN_INPUT_PULLUP, MUX_MODE0) 125*4882a593Smuzhiyun /* gpmc_wpn.gpio0_30 */ 126*4882a593Smuzhiyun AM33XX_PADCONF(AM335X_PIN_GPMC_WPN, PIN_INPUT_PULLUP, MUX_MODE7) 127*4882a593Smuzhiyun AM33XX_PADCONF(AM335X_PIN_GPMC_CSN0, PIN_OUTPUT, MUX_MODE0) 128*4882a593Smuzhiyun AM33XX_PADCONF(AM335X_PIN_GPMC_ADVN_ALE, PIN_OUTPUT, MUX_MODE0) 129*4882a593Smuzhiyun AM33XX_PADCONF(AM335X_PIN_GPMC_OEN_REN, PIN_OUTPUT, MUX_MODE0) 130*4882a593Smuzhiyun AM33XX_PADCONF(AM335X_PIN_GPMC_WEN, PIN_OUTPUT, MUX_MODE0) 131*4882a593Smuzhiyun AM33XX_PADCONF(AM335X_PIN_GPMC_BEN0_CLE, PIN_OUTPUT, MUX_MODE0) 132*4882a593Smuzhiyun >; 133*4882a593Smuzhiyun }; 134*4882a593Smuzhiyun 135*4882a593Smuzhiyun uart0_pins: pinmux_uart0_pins { 136*4882a593Smuzhiyun pinctrl-single,pins = < 137*4882a593Smuzhiyun AM33XX_PADCONF(AM335X_PIN_UART0_RXD, PIN_INPUT_PULLUP, MUX_MODE0) 138*4882a593Smuzhiyun AM33XX_PADCONF(AM335X_PIN_UART0_TXD, PIN_OUTPUT_PULLDOWN, MUX_MODE0) 139*4882a593Smuzhiyun >; 140*4882a593Smuzhiyun }; 141*4882a593Smuzhiyun 142*4882a593Smuzhiyun uart1_pins: pinmux_uart1_pins { 143*4882a593Smuzhiyun pinctrl-single,pins = < 144*4882a593Smuzhiyun AM33XX_PADCONF(AM335X_PIN_UART1_CTSN, PIN_INPUT, MUX_MODE0) 145*4882a593Smuzhiyun AM33XX_PADCONF(AM335X_PIN_UART1_RTSN, PIN_OUTPUT_PULLDOWN, MUX_MODE0) 146*4882a593Smuzhiyun AM33XX_PADCONF(AM335X_PIN_UART1_RXD, PIN_INPUT_PULLUP, MUX_MODE0) 147*4882a593Smuzhiyun AM33XX_PADCONF(AM335X_PIN_UART1_TXD, PIN_OUTPUT_PULLDOWN, MUX_MODE0) 148*4882a593Smuzhiyun >; 149*4882a593Smuzhiyun }; 150*4882a593Smuzhiyun 151*4882a593Smuzhiyun dcan0_pins: pinmux_dcan0_pins { 152*4882a593Smuzhiyun pinctrl-single,pins = < 153*4882a593Smuzhiyun /* uart1_ctsn.dcan0_tx */ 154*4882a593Smuzhiyun AM33XX_PADCONF(AM335X_PIN_UART1_CTSN, PIN_OUTPUT, MUX_MODE2) 155*4882a593Smuzhiyun /* uart1_rtsn.dcan0_rx */ 156*4882a593Smuzhiyun AM33XX_PADCONF(AM335X_PIN_UART1_RTSN, PIN_INPUT, MUX_MODE2) 157*4882a593Smuzhiyun >; 158*4882a593Smuzhiyun }; 159*4882a593Smuzhiyun 160*4882a593Smuzhiyun dcan1_pins: pinmux_dcan1_pins { 161*4882a593Smuzhiyun pinctrl-single,pins = < 162*4882a593Smuzhiyun /* uart1_rxd.dcan1_tx */ 163*4882a593Smuzhiyun AM33XX_PADCONF(AM335X_PIN_UART1_RXD, PIN_OUTPUT, MUX_MODE2) 164*4882a593Smuzhiyun /* uart1_txd.dcan1_rx */ 165*4882a593Smuzhiyun AM33XX_PADCONF(AM335X_PIN_UART1_TXD, PIN_INPUT, MUX_MODE2) 166*4882a593Smuzhiyun >; 167*4882a593Smuzhiyun }; 168*4882a593Smuzhiyun 169*4882a593Smuzhiyun ecap0_pins: pinmux_ecap0_pins { 170*4882a593Smuzhiyun pinctrl-single,pins = < 171*4882a593Smuzhiyun AM33XX_PADCONF(AM335X_PIN_ECAP0_IN_PWM0_OUT, 0x0, MUX_MODE0) 172*4882a593Smuzhiyun >; 173*4882a593Smuzhiyun }; 174*4882a593Smuzhiyun 175*4882a593Smuzhiyun cpsw_default: cpsw_default { 176*4882a593Smuzhiyun pinctrl-single,pins = < 177*4882a593Smuzhiyun /* Slave 1 */ 178*4882a593Smuzhiyun /* mii1_tx_en.rgmii1_tctl */ 179*4882a593Smuzhiyun AM33XX_PADCONF(AM335X_PIN_MII1_TX_EN, PIN_OUTPUT_PULLDOWN, MUX_MODE2) 180*4882a593Smuzhiyun /* mii1_rxdv.rgmii1_rctl */ 181*4882a593Smuzhiyun AM33XX_PADCONF(AM335X_PIN_MII1_RX_DV, PIN_INPUT_PULLDOWN, MUX_MODE2) 182*4882a593Smuzhiyun /* mii1_txd3.rgmii1_td3 */ 183*4882a593Smuzhiyun AM33XX_PADCONF(AM335X_PIN_MII1_TXD3, PIN_OUTPUT_PULLDOWN, MUX_MODE2) 184*4882a593Smuzhiyun /* mii1_txd2.rgmii1_td2 */ 185*4882a593Smuzhiyun AM33XX_PADCONF(AM335X_PIN_MII1_TXD2, PIN_OUTPUT_PULLDOWN, MUX_MODE2) 186*4882a593Smuzhiyun /* mii1_txd1.rgmii1_td1 */ 187*4882a593Smuzhiyun AM33XX_PADCONF(AM335X_PIN_MII1_TXD1, PIN_OUTPUT_PULLDOWN, MUX_MODE2) 188*4882a593Smuzhiyun /* mii1_txd0.rgmii1_td0 */ 189*4882a593Smuzhiyun AM33XX_PADCONF(AM335X_PIN_MII1_TXD0, PIN_OUTPUT_PULLDOWN, MUX_MODE2) 190*4882a593Smuzhiyun /* mii1_txclk.rgmii1_tclk */ 191*4882a593Smuzhiyun AM33XX_PADCONF(AM335X_PIN_MII1_TX_CLK, PIN_OUTPUT_PULLDOWN, MUX_MODE2) 192*4882a593Smuzhiyun /* mii1_rxclk.rgmii1_rclk */ 193*4882a593Smuzhiyun AM33XX_PADCONF(AM335X_PIN_MII1_RX_CLK, PIN_INPUT_PULLDOWN, MUX_MODE2) 194*4882a593Smuzhiyun /* mii1_rxd3.rgmii1_rd3 */ 195*4882a593Smuzhiyun AM33XX_PADCONF(AM335X_PIN_MII1_RXD3, PIN_INPUT_PULLDOWN, MUX_MODE2) 196*4882a593Smuzhiyun /* mii1_rxd2.rgmii1_rd2 */ 197*4882a593Smuzhiyun AM33XX_PADCONF(AM335X_PIN_MII1_RXD2, PIN_INPUT_PULLDOWN, MUX_MODE2) 198*4882a593Smuzhiyun /* mii1_rxd1.rgmii1_rd1 */ 199*4882a593Smuzhiyun AM33XX_PADCONF(AM335X_PIN_MII1_RXD1, PIN_INPUT_PULLDOWN, MUX_MODE2) 200*4882a593Smuzhiyun /* mii1_rxd0.rgmii1_rd0 */ 201*4882a593Smuzhiyun AM33XX_PADCONF(AM335X_PIN_MII1_RXD0, PIN_INPUT_PULLDOWN, MUX_MODE2) 202*4882a593Smuzhiyun >; 203*4882a593Smuzhiyun }; 204*4882a593Smuzhiyun 205*4882a593Smuzhiyun cpsw_sleep: cpsw_sleep { 206*4882a593Smuzhiyun pinctrl-single,pins = < 207*4882a593Smuzhiyun /* Slave 1 reset value */ 208*4882a593Smuzhiyun AM33XX_PADCONF(AM335X_PIN_MII1_TX_EN, PIN_INPUT_PULLDOWN, MUX_MODE7) 209*4882a593Smuzhiyun AM33XX_PADCONF(AM335X_PIN_MII1_RX_DV, PIN_INPUT_PULLDOWN, MUX_MODE7) 210*4882a593Smuzhiyun AM33XX_PADCONF(AM335X_PIN_MII1_TXD3, PIN_INPUT_PULLDOWN, MUX_MODE7) 211*4882a593Smuzhiyun AM33XX_PADCONF(AM335X_PIN_MII1_TXD2, PIN_INPUT_PULLDOWN, MUX_MODE7) 212*4882a593Smuzhiyun AM33XX_PADCONF(AM335X_PIN_MII1_TXD1, PIN_INPUT_PULLDOWN, MUX_MODE7) 213*4882a593Smuzhiyun AM33XX_PADCONF(AM335X_PIN_MII1_TXD0, PIN_INPUT_PULLDOWN, MUX_MODE7) 214*4882a593Smuzhiyun AM33XX_PADCONF(AM335X_PIN_MII1_TX_CLK, PIN_INPUT_PULLDOWN, MUX_MODE7) 215*4882a593Smuzhiyun AM33XX_PADCONF(AM335X_PIN_MII1_RX_CLK, PIN_INPUT_PULLDOWN, MUX_MODE7) 216*4882a593Smuzhiyun AM33XX_PADCONF(AM335X_PIN_MII1_RXD3, PIN_INPUT_PULLDOWN, MUX_MODE7) 217*4882a593Smuzhiyun AM33XX_PADCONF(AM335X_PIN_MII1_RXD2, PIN_INPUT_PULLDOWN, MUX_MODE7) 218*4882a593Smuzhiyun AM33XX_PADCONF(AM335X_PIN_MII1_RXD1, PIN_INPUT_PULLDOWN, MUX_MODE7) 219*4882a593Smuzhiyun AM33XX_PADCONF(AM335X_PIN_MII1_RXD0, PIN_INPUT_PULLDOWN, MUX_MODE7) 220*4882a593Smuzhiyun >; 221*4882a593Smuzhiyun }; 222*4882a593Smuzhiyun 223*4882a593Smuzhiyun davinci_mdio_default: davinci_mdio_default { 224*4882a593Smuzhiyun pinctrl-single,pins = < 225*4882a593Smuzhiyun AM33XX_PADCONF(AM335X_PIN_MDIO, PIN_INPUT_PULLUP | SLEWCTRL_FAST, MUX_MODE0) 226*4882a593Smuzhiyun AM33XX_PADCONF(AM335X_PIN_MDC, PIN_OUTPUT_PULLUP, MUX_MODE0) 227*4882a593Smuzhiyun >; 228*4882a593Smuzhiyun }; 229*4882a593Smuzhiyun 230*4882a593Smuzhiyun davinci_mdio_sleep: davinci_mdio_sleep { 231*4882a593Smuzhiyun pinctrl-single,pins = < 232*4882a593Smuzhiyun /* MDIO reset value */ 233*4882a593Smuzhiyun AM33XX_PADCONF(AM335X_PIN_MDIO, PIN_INPUT_PULLDOWN, MUX_MODE7) 234*4882a593Smuzhiyun AM33XX_PADCONF(AM335X_PIN_MDC, PIN_INPUT_PULLDOWN, MUX_MODE7) 235*4882a593Smuzhiyun >; 236*4882a593Smuzhiyun }; 237*4882a593Smuzhiyun 238*4882a593Smuzhiyun mmc1_pins: pinmux_mmc1_pins { 239*4882a593Smuzhiyun pinctrl-single,pins = < 240*4882a593Smuzhiyun AM33XX_PADCONF(AM335X_PIN_MMC0_DAT3, PIN_INPUT_PULLUP, MUX_MODE0) 241*4882a593Smuzhiyun AM33XX_PADCONF(AM335X_PIN_MMC0_DAT2, PIN_INPUT_PULLUP, MUX_MODE0) 242*4882a593Smuzhiyun AM33XX_PADCONF(AM335X_PIN_MMC0_DAT1, PIN_INPUT_PULLUP, MUX_MODE0) 243*4882a593Smuzhiyun AM33XX_PADCONF(AM335X_PIN_MMC0_DAT0, PIN_INPUT_PULLUP, MUX_MODE0) 244*4882a593Smuzhiyun AM33XX_PADCONF(AM335X_PIN_MMC0_CLK, PIN_INPUT_PULLUP, MUX_MODE0) 245*4882a593Smuzhiyun AM33XX_PADCONF(AM335X_PIN_MMC0_CMD, PIN_INPUT_PULLUP, MUX_MODE0) 246*4882a593Smuzhiyun >; 247*4882a593Smuzhiyun }; 248*4882a593Smuzhiyun 249*4882a593Smuzhiyun spi0_pins: pinmux_spi0_pins { 250*4882a593Smuzhiyun pinctrl-single,pins = < 251*4882a593Smuzhiyun AM33XX_PADCONF(AM335X_PIN_SPI0_SCLK, PIN_INPUT, MUX_MODE0) 252*4882a593Smuzhiyun AM33XX_PADCONF(AM335X_PIN_SPI0_D0, PIN_OUTPUT_PULLUP, MUX_MODE0) 253*4882a593Smuzhiyun AM33XX_PADCONF(AM335X_PIN_SPI0_D1, PIN_INPUT, MUX_MODE0) 254*4882a593Smuzhiyun AM33XX_PADCONF(AM335X_PIN_SPI0_CS0, PIN_OUTPUT, MUX_MODE0) 255*4882a593Smuzhiyun AM33XX_PADCONF(AM335X_PIN_SPI0_CS1, PIN_OUTPUT, MUX_MODE0) 256*4882a593Smuzhiyun >; 257*4882a593Smuzhiyun }; 258*4882a593Smuzhiyun 259*4882a593Smuzhiyun /* wl1271 bluetooth */ 260*4882a593Smuzhiyun bluetooth_pins: pinmux_bluetooth_pins { 261*4882a593Smuzhiyun pinctrl-single,pins = < 262*4882a593Smuzhiyun /* XDMA_EVENT_INTR0.gpio0_19 - bluetooth enable */ 263*4882a593Smuzhiyun AM33XX_PADCONF(AM335X_PIN_XDMA_EVENT_INTR0, PIN_OUTPUT_PULLUP, MUX_MODE7) 264*4882a593Smuzhiyun >; 265*4882a593Smuzhiyun }; 266*4882a593Smuzhiyun 267*4882a593Smuzhiyun /* TLV320AIC23B codec */ 268*4882a593Smuzhiyun mcasp1_pins: pinmux_mcasp1_pins { 269*4882a593Smuzhiyun pinctrl-single,pins = < 270*4882a593Smuzhiyun /* MII1_CRS.mcasp1_aclkx */ 271*4882a593Smuzhiyun AM33XX_PADCONF(AM335X_PIN_MII1_CRS, PIN_INPUT_PULLDOWN, MUX_MODE4) 272*4882a593Smuzhiyun /* MII1_RX_ER.mcasp1_fsx */ 273*4882a593Smuzhiyun AM33XX_PADCONF(AM335X_PIN_MII1_RX_ER, PIN_INPUT_PULLDOWN, MUX_MODE4) 274*4882a593Smuzhiyun /* MII1_COL.mcasp1_axr2 */ 275*4882a593Smuzhiyun AM33XX_PADCONF(AM335X_PIN_MII1_COL, PIN_INPUT_PULLDOWN, MUX_MODE4) 276*4882a593Smuzhiyun /* RMII1_REF_CLK.mcasp1_axr3 */ 277*4882a593Smuzhiyun AM33XX_PADCONF(AM335X_PIN_RMII1_REF_CLK, PIN_INPUT_PULLDOWN, MUX_MODE4) 278*4882a593Smuzhiyun >; 279*4882a593Smuzhiyun }; 280*4882a593Smuzhiyun 281*4882a593Smuzhiyun /* wl1271 WiFi */ 282*4882a593Smuzhiyun wifi_pins: pinmux_wifi_pins { 283*4882a593Smuzhiyun pinctrl-single,pins = < 284*4882a593Smuzhiyun /* EMU1.gpio3_8 - WiFi IRQ */ 285*4882a593Smuzhiyun AM33XX_PADCONF(AM335X_PIN_EMU1, PIN_INPUT_PULLUP, MUX_MODE7) 286*4882a593Smuzhiyun /* XDMA_EVENT_INTR1.gpio0_20 - WiFi enable */ 287*4882a593Smuzhiyun AM33XX_PADCONF(AM335X_PIN_XDMA_EVENT_INTR1, PIN_OUTPUT, MUX_MODE7) 288*4882a593Smuzhiyun >; 289*4882a593Smuzhiyun }; 290*4882a593Smuzhiyun}; 291*4882a593Smuzhiyun 292*4882a593Smuzhiyun&uart0 { 293*4882a593Smuzhiyun pinctrl-names = "default"; 294*4882a593Smuzhiyun pinctrl-0 = <&uart0_pins>; 295*4882a593Smuzhiyun 296*4882a593Smuzhiyun status = "okay"; 297*4882a593Smuzhiyun}; 298*4882a593Smuzhiyun 299*4882a593Smuzhiyun/* WLS1271 bluetooth */ 300*4882a593Smuzhiyun&uart1 { 301*4882a593Smuzhiyun pinctrl-names = "default"; 302*4882a593Smuzhiyun pinctrl-0 = <&uart1_pins>; 303*4882a593Smuzhiyun 304*4882a593Smuzhiyunstatus = "okay"; 305*4882a593Smuzhiyun}; 306*4882a593Smuzhiyun 307*4882a593Smuzhiyun&i2c0 { 308*4882a593Smuzhiyun pinctrl-names = "default"; 309*4882a593Smuzhiyun pinctrl-0 = <&i2c0_pins>; 310*4882a593Smuzhiyun 311*4882a593Smuzhiyun status = "okay"; 312*4882a593Smuzhiyun clock-frequency = <400000>; 313*4882a593Smuzhiyun /* CM-T335 board EEPROM */ 314*4882a593Smuzhiyun eeprom: 24c02@50 { 315*4882a593Smuzhiyun compatible = "atmel,24c02"; 316*4882a593Smuzhiyun reg = <0x50>; 317*4882a593Smuzhiyun pagesize = <16>; 318*4882a593Smuzhiyun }; 319*4882a593Smuzhiyun /* Real Time Clock */ 320*4882a593Smuzhiyun ext_rtc: em3027@56 { 321*4882a593Smuzhiyun compatible = "emmicro,em3027"; 322*4882a593Smuzhiyun reg = <0x56>; 323*4882a593Smuzhiyun }; 324*4882a593Smuzhiyun /* Audio codec */ 325*4882a593Smuzhiyun tlv320aic23: codec@1a { 326*4882a593Smuzhiyun compatible = "ti,tlv320aic23"; 327*4882a593Smuzhiyun reg = <0x1a>; 328*4882a593Smuzhiyun #sound-dai-cells= <0>; 329*4882a593Smuzhiyun status = "okay"; 330*4882a593Smuzhiyun }; 331*4882a593Smuzhiyun}; 332*4882a593Smuzhiyun 333*4882a593Smuzhiyun&epwmss0 { 334*4882a593Smuzhiyun status = "okay"; 335*4882a593Smuzhiyun 336*4882a593Smuzhiyun ecap0: ecap@100 { 337*4882a593Smuzhiyun status = "okay"; 338*4882a593Smuzhiyun pinctrl-names = "default"; 339*4882a593Smuzhiyun pinctrl-0 = <&ecap0_pins>; 340*4882a593Smuzhiyun }; 341*4882a593Smuzhiyun}; 342*4882a593Smuzhiyun 343*4882a593Smuzhiyun&gpmc { 344*4882a593Smuzhiyun status = "okay"; 345*4882a593Smuzhiyun pinctrl-names = "default"; 346*4882a593Smuzhiyun pinctrl-0 = <&nandflash_pins>; 347*4882a593Smuzhiyun ranges = <0 0 0x08000000 0x10000000>; /* CS0: NAND */ 348*4882a593Smuzhiyun nand@0,0 { 349*4882a593Smuzhiyun compatible = "ti,omap2-nand"; 350*4882a593Smuzhiyun reg = <0 0 4>; /* CS0, offset 0, IO size 4 */ 351*4882a593Smuzhiyun interrupt-parent = <&gpmc>; 352*4882a593Smuzhiyun interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */ 353*4882a593Smuzhiyun <1 IRQ_TYPE_NONE>; /* termcount */ 354*4882a593Smuzhiyun rb-gpios = <&gpmc 0 GPIO_ACTIVE_HIGH>; /* gpmc_wait0 */ 355*4882a593Smuzhiyun ti,nand-ecc-opt = "bch8"; 356*4882a593Smuzhiyun ti,elm-id = <&elm>; 357*4882a593Smuzhiyun nand-bus-width = <8>; 358*4882a593Smuzhiyun gpmc,device-width = <1>; 359*4882a593Smuzhiyun gpmc,sync-clk-ps = <0>; 360*4882a593Smuzhiyun gpmc,cs-on-ns = <0>; 361*4882a593Smuzhiyun gpmc,cs-rd-off-ns = <44>; 362*4882a593Smuzhiyun gpmc,cs-wr-off-ns = <44>; 363*4882a593Smuzhiyun gpmc,adv-on-ns = <6>; 364*4882a593Smuzhiyun gpmc,adv-rd-off-ns = <34>; 365*4882a593Smuzhiyun gpmc,adv-wr-off-ns = <44>; 366*4882a593Smuzhiyun gpmc,we-on-ns = <0>; 367*4882a593Smuzhiyun gpmc,we-off-ns = <40>; 368*4882a593Smuzhiyun gpmc,oe-on-ns = <0>; 369*4882a593Smuzhiyun gpmc,oe-off-ns = <54>; 370*4882a593Smuzhiyun gpmc,access-ns = <64>; 371*4882a593Smuzhiyun gpmc,rd-cycle-ns = <82>; 372*4882a593Smuzhiyun gpmc,wr-cycle-ns = <82>; 373*4882a593Smuzhiyun gpmc,bus-turnaround-ns = <0>; 374*4882a593Smuzhiyun gpmc,cycle2cycle-delay-ns = <0>; 375*4882a593Smuzhiyun gpmc,clk-activation-ns = <0>; 376*4882a593Smuzhiyun gpmc,wr-access-ns = <40>; 377*4882a593Smuzhiyun gpmc,wr-data-mux-bus-ns = <0>; 378*4882a593Smuzhiyun /* MTD partition table */ 379*4882a593Smuzhiyun #address-cells = <1>; 380*4882a593Smuzhiyun #size-cells = <1>; 381*4882a593Smuzhiyun partition@0 { 382*4882a593Smuzhiyun label = "spl"; 383*4882a593Smuzhiyun reg = <0x00000000 0x00200000>; 384*4882a593Smuzhiyun }; 385*4882a593Smuzhiyun partition@1 { 386*4882a593Smuzhiyun label = "uboot"; 387*4882a593Smuzhiyun reg = <0x00200000 0x00100000>; 388*4882a593Smuzhiyun }; 389*4882a593Smuzhiyun partition@2 { 390*4882a593Smuzhiyun label = "uboot environment"; 391*4882a593Smuzhiyun reg = <0x00300000 0x00100000>; 392*4882a593Smuzhiyun }; 393*4882a593Smuzhiyun partition@3 { 394*4882a593Smuzhiyun label = "dtb"; 395*4882a593Smuzhiyun reg = <0x00400000 0x00100000>; 396*4882a593Smuzhiyun }; 397*4882a593Smuzhiyun partition@4 { 398*4882a593Smuzhiyun label = "splash"; 399*4882a593Smuzhiyun reg = <0x00500000 0x00400000>; 400*4882a593Smuzhiyun }; 401*4882a593Smuzhiyun partition@5 { 402*4882a593Smuzhiyun label = "linux"; 403*4882a593Smuzhiyun reg = <0x00900000 0x00600000>; 404*4882a593Smuzhiyun }; 405*4882a593Smuzhiyun partition@6 { 406*4882a593Smuzhiyun label = "rootfs"; 407*4882a593Smuzhiyun reg = <0x00F00000 0>; 408*4882a593Smuzhiyun }; 409*4882a593Smuzhiyun }; 410*4882a593Smuzhiyun}; 411*4882a593Smuzhiyun 412*4882a593Smuzhiyun&elm { 413*4882a593Smuzhiyun status = "okay"; 414*4882a593Smuzhiyun}; 415*4882a593Smuzhiyun 416*4882a593Smuzhiyun&mac { 417*4882a593Smuzhiyun pinctrl-names = "default", "sleep"; 418*4882a593Smuzhiyun pinctrl-0 = <&cpsw_default>; 419*4882a593Smuzhiyun pinctrl-1 = <&cpsw_sleep>; 420*4882a593Smuzhiyun slaves = <1>; 421*4882a593Smuzhiyun status = "okay"; 422*4882a593Smuzhiyun}; 423*4882a593Smuzhiyun 424*4882a593Smuzhiyun&davinci_mdio { 425*4882a593Smuzhiyun pinctrl-names = "default", "sleep"; 426*4882a593Smuzhiyun pinctrl-0 = <&davinci_mdio_default>; 427*4882a593Smuzhiyun pinctrl-1 = <&davinci_mdio_sleep>; 428*4882a593Smuzhiyun status = "okay"; 429*4882a593Smuzhiyun 430*4882a593Smuzhiyun ethphy0: ethernet-phy@0 { 431*4882a593Smuzhiyun reg = <0>; 432*4882a593Smuzhiyun }; 433*4882a593Smuzhiyun}; 434*4882a593Smuzhiyun 435*4882a593Smuzhiyun&cpsw_emac0 { 436*4882a593Smuzhiyun phy-handle = <ðphy0>; 437*4882a593Smuzhiyun phy-mode = "rgmii-txid"; 438*4882a593Smuzhiyun}; 439*4882a593Smuzhiyun 440*4882a593Smuzhiyun&mmc1 { 441*4882a593Smuzhiyun status = "okay"; 442*4882a593Smuzhiyun vmmc-supply = <&vmmc_fixed>; 443*4882a593Smuzhiyun bus-width = <4>; 444*4882a593Smuzhiyun pinctrl-names = "default"; 445*4882a593Smuzhiyun pinctrl-0 = <&mmc1_pins>; 446*4882a593Smuzhiyun}; 447*4882a593Smuzhiyun 448*4882a593Smuzhiyun&dcan0 { 449*4882a593Smuzhiyun status = "okay"; 450*4882a593Smuzhiyun pinctrl-names = "default"; 451*4882a593Smuzhiyun pinctrl-0 = <&dcan0_pins>; 452*4882a593Smuzhiyun}; 453*4882a593Smuzhiyun 454*4882a593Smuzhiyun&dcan1 { 455*4882a593Smuzhiyun status = "okay"; 456*4882a593Smuzhiyun pinctrl-names = "default"; 457*4882a593Smuzhiyun pinctrl-0 = <&dcan1_pins>; 458*4882a593Smuzhiyun}; 459*4882a593Smuzhiyun 460*4882a593Smuzhiyun/* Touschscreen and analog digital converter */ 461*4882a593Smuzhiyun&tscadc { 462*4882a593Smuzhiyun status = "okay"; 463*4882a593Smuzhiyun tsc { 464*4882a593Smuzhiyun ti,wires = <4>; 465*4882a593Smuzhiyun ti,x-plate-resistance = <200>; 466*4882a593Smuzhiyun ti,coordinate-readouts = <5>; 467*4882a593Smuzhiyun ti,wire-config = <0x01 0x10 0x23 0x32>; 468*4882a593Smuzhiyun ti,charge-delay = <0x400>; 469*4882a593Smuzhiyun }; 470*4882a593Smuzhiyun 471*4882a593Smuzhiyun adc { 472*4882a593Smuzhiyun ti,adc-channels = <4 5 6 7>; 473*4882a593Smuzhiyun }; 474*4882a593Smuzhiyun}; 475*4882a593Smuzhiyun 476*4882a593Smuzhiyun/* CPU audio */ 477*4882a593Smuzhiyun&mcasp1 { 478*4882a593Smuzhiyun pinctrl-names = "default"; 479*4882a593Smuzhiyun pinctrl-0 = <&mcasp1_pins>; 480*4882a593Smuzhiyun 481*4882a593Smuzhiyun op-mode = <0>; /* MCASP_IIS_MODE */ 482*4882a593Smuzhiyun tdm-slots = <2>; 483*4882a593Smuzhiyun /* 16 serializers */ 484*4882a593Smuzhiyun num-serializer = <16>; 485*4882a593Smuzhiyun serial-dir = < /* 0: INACTIVE, 1: TX, 2: RX */ 486*4882a593Smuzhiyun 0 0 2 1 0 0 0 0 0 0 0 0 0 0 0 0 487*4882a593Smuzhiyun >; 488*4882a593Smuzhiyun tx-num-evt = <1>; 489*4882a593Smuzhiyun rx-num-evt = <1>; 490*4882a593Smuzhiyun 491*4882a593Smuzhiyun #sound-dai-cells= <0>; 492*4882a593Smuzhiyun status = "okay"; 493*4882a593Smuzhiyun}; 494*4882a593Smuzhiyun 495*4882a593Smuzhiyun&spi0 { 496*4882a593Smuzhiyun status = "okay"; 497*4882a593Smuzhiyun pinctrl-names = "default"; 498*4882a593Smuzhiyun pinctrl-0 = <&spi0_pins>; 499*4882a593Smuzhiyun ti,pindir-d0-out-d1-in; 500*4882a593Smuzhiyun /* WLS1271 WiFi */ 501*4882a593Smuzhiyun wlcore: wlcore@1 { 502*4882a593Smuzhiyun compatible = "ti,wl1271"; 503*4882a593Smuzhiyun pinctrl-names = "default"; 504*4882a593Smuzhiyun pinctrl-0 = <&wifi_pins>; 505*4882a593Smuzhiyun reg = <1>; 506*4882a593Smuzhiyun spi-max-frequency = <48000000>; 507*4882a593Smuzhiyun clock-xtal; 508*4882a593Smuzhiyun ref-clock-frequency = <38400000>; 509*4882a593Smuzhiyun interrupt-parent = <&gpio3>; 510*4882a593Smuzhiyun interrupts = <8 IRQ_TYPE_LEVEL_HIGH>; 511*4882a593Smuzhiyun vwlan-supply = <&vwlan_fixed>; 512*4882a593Smuzhiyun }; 513*4882a593Smuzhiyun}; 514