1*4882a593Smuzhiyun// SPDX-License-Identifier: GPL-2.0-only 2*4882a593Smuzhiyun/* 3*4882a593Smuzhiyun * Copyright (C) 2014, 2015 Synopsys, Inc. (www.synopsys.com) 4*4882a593Smuzhiyun */ 5*4882a593Smuzhiyun 6*4882a593Smuzhiyun/* 7*4882a593Smuzhiyun * Device tree for AXC003 CPU card: 8*4882a593Smuzhiyun * HS38x2 (Dual Core) with IDU intc (VDK version) 9*4882a593Smuzhiyun */ 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun/include/ "skeleton_hs_idu.dtsi" 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun/ { 14*4882a593Smuzhiyun compatible = "snps,arc"; 15*4882a593Smuzhiyun #address-cells = <1>; 16*4882a593Smuzhiyun #size-cells = <1>; 17*4882a593Smuzhiyun 18*4882a593Smuzhiyun cpu_card { 19*4882a593Smuzhiyun compatible = "simple-bus"; 20*4882a593Smuzhiyun #address-cells = <1>; 21*4882a593Smuzhiyun #size-cells = <1>; 22*4882a593Smuzhiyun 23*4882a593Smuzhiyun ranges = <0x00000000 0xf0000000 0x10000000>; 24*4882a593Smuzhiyun 25*4882a593Smuzhiyun core_clk: core_clk { 26*4882a593Smuzhiyun #clock-cells = <0>; 27*4882a593Smuzhiyun compatible = "fixed-clock"; 28*4882a593Smuzhiyun clock-frequency = <50000000>; 29*4882a593Smuzhiyun }; 30*4882a593Smuzhiyun 31*4882a593Smuzhiyun core_intc: archs-intc@cpu { 32*4882a593Smuzhiyun compatible = "snps,archs-intc"; 33*4882a593Smuzhiyun interrupt-controller; 34*4882a593Smuzhiyun #interrupt-cells = <1>; 35*4882a593Smuzhiyun }; 36*4882a593Smuzhiyun 37*4882a593Smuzhiyun idu_intc: idu-interrupt-controller { 38*4882a593Smuzhiyun compatible = "snps,archs-idu-intc"; 39*4882a593Smuzhiyun interrupt-controller; 40*4882a593Smuzhiyun interrupt-parent = <&core_intc>; 41*4882a593Smuzhiyun #interrupt-cells = <1>; 42*4882a593Smuzhiyun }; 43*4882a593Smuzhiyun 44*4882a593Smuzhiyun debug_uart: dw-apb-uart@5000 { 45*4882a593Smuzhiyun compatible = "snps,dw-apb-uart"; 46*4882a593Smuzhiyun reg = <0x5000 0x100>; 47*4882a593Smuzhiyun clock-frequency = <2403200>; 48*4882a593Smuzhiyun interrupt-parent = <&idu_intc>; 49*4882a593Smuzhiyun interrupts = <2>; 50*4882a593Smuzhiyun baud = <115200>; 51*4882a593Smuzhiyun reg-shift = <2>; 52*4882a593Smuzhiyun reg-io-width = <4>; 53*4882a593Smuzhiyun }; 54*4882a593Smuzhiyun 55*4882a593Smuzhiyun }; 56*4882a593Smuzhiyun 57*4882a593Smuzhiyun mb_intc: interrupt-controller@e0012000 { 58*4882a593Smuzhiyun #interrupt-cells = <1>; 59*4882a593Smuzhiyun compatible = "snps,dw-apb-ictl"; 60*4882a593Smuzhiyun reg = < 0xe0012000 0x200 >; 61*4882a593Smuzhiyun interrupt-controller; 62*4882a593Smuzhiyun interrupt-parent = <&idu_intc>; 63*4882a593Smuzhiyun interrupts = <0>; 64*4882a593Smuzhiyun }; 65*4882a593Smuzhiyun 66*4882a593Smuzhiyun memory { 67*4882a593Smuzhiyun #address-cells = <1>; 68*4882a593Smuzhiyun #size-cells = <1>; 69*4882a593Smuzhiyun ranges = <0x00000000 0x80000000 0x40000000>; 70*4882a593Smuzhiyun device_type = "memory"; 71*4882a593Smuzhiyun reg = <0x80000000 0x20000000>; /* 512MiB */ 72*4882a593Smuzhiyun }; 73*4882a593Smuzhiyun}; 74