1*4882a593Smuzhiyun// SPDX-License-Identifier: GPL-2.0-only 2*4882a593Smuzhiyun/* 3*4882a593Smuzhiyun * Copyright (C) 2016 Synopsys, Inc. (www.synopsys.com) 4*4882a593Smuzhiyun */ 5*4882a593Smuzhiyun 6*4882a593Smuzhiyun/ { 7*4882a593Smuzhiyun compatible = "snps,arc"; 8*4882a593Smuzhiyun #address-cells = <1>; 9*4882a593Smuzhiyun #size-cells = <1>; 10*4882a593Smuzhiyun chosen { }; 11*4882a593Smuzhiyun aliases { }; 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun cpus { 14*4882a593Smuzhiyun #address-cells = <1>; 15*4882a593Smuzhiyun #size-cells = <0>; 16*4882a593Smuzhiyun 17*4882a593Smuzhiyun cpu@0 { 18*4882a593Smuzhiyun device_type = "cpu"; 19*4882a593Smuzhiyun compatible = "snps,archs38"; 20*4882a593Smuzhiyun reg = <0>; 21*4882a593Smuzhiyun clocks = <&core_clk>; 22*4882a593Smuzhiyun }; 23*4882a593Smuzhiyun }; 24*4882a593Smuzhiyun 25*4882a593Smuzhiyun /* TIMER0 with interrupt for clockevent */ 26*4882a593Smuzhiyun timer0 { 27*4882a593Smuzhiyun compatible = "snps,arc-timer"; 28*4882a593Smuzhiyun interrupts = <16>; 29*4882a593Smuzhiyun interrupt-parent = <&core_intc>; 30*4882a593Smuzhiyun clocks = <&core_clk>; 31*4882a593Smuzhiyun }; 32*4882a593Smuzhiyun 33*4882a593Smuzhiyun /* 64-bit Local RTC: preferred clocksource for UP */ 34*4882a593Smuzhiyun rtc { 35*4882a593Smuzhiyun compatible = "snps,archs-timer-rtc"; 36*4882a593Smuzhiyun clocks = <&core_clk>; 37*4882a593Smuzhiyun }; 38*4882a593Smuzhiyun 39*4882a593Smuzhiyun /* TIMER1 for free running clocksource: Fallback if rtc not found */ 40*4882a593Smuzhiyun timer1 { 41*4882a593Smuzhiyun compatible = "snps,arc-timer"; 42*4882a593Smuzhiyun clocks = <&core_clk>; 43*4882a593Smuzhiyun }; 44*4882a593Smuzhiyun 45*4882a593Smuzhiyun memory { 46*4882a593Smuzhiyun device_type = "memory"; 47*4882a593Smuzhiyun reg = <0x80000000 0x10000000>; /* 256M */ 48*4882a593Smuzhiyun }; 49*4882a593Smuzhiyun}; 50