xref: /OK3568_Linux_fs/kernel/scripts/dtc/include-prefixes/arc/haps_hs.dts (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun// SPDX-License-Identifier: GPL-2.0-only
2*4882a593Smuzhiyun/*
3*4882a593Smuzhiyun * Copyright (C) 2016-2014 Synopsys, Inc. (www.synopsys.com)
4*4882a593Smuzhiyun */
5*4882a593Smuzhiyun/dts-v1/;
6*4882a593Smuzhiyun
7*4882a593Smuzhiyun/include/ "skeleton_hs.dtsi"
8*4882a593Smuzhiyun
9*4882a593Smuzhiyun/ {
10*4882a593Smuzhiyun	model = "snps,zebu_hs";
11*4882a593Smuzhiyun	compatible = "snps,zebu_hs";
12*4882a593Smuzhiyun	#address-cells = <2>;
13*4882a593Smuzhiyun	#size-cells = <2>;
14*4882a593Smuzhiyun	interrupt-parent = <&core_intc>;
15*4882a593Smuzhiyun
16*4882a593Smuzhiyun	memory {
17*4882a593Smuzhiyun		device_type = "memory";
18*4882a593Smuzhiyun		/* CONFIG_LINUX_RAM_BASE needs to match low mem start */
19*4882a593Smuzhiyun		reg = <0x0 0x80000000 0x0 0x20000000	/* 512 MB low mem */
20*4882a593Smuzhiyun		       0x1 0x00000000 0x0 0x40000000>;	/* 1 GB highmem */
21*4882a593Smuzhiyun	};
22*4882a593Smuzhiyun
23*4882a593Smuzhiyun	chosen {
24*4882a593Smuzhiyun		bootargs = "earlycon=uart8250,mmio32,0xf0000000,115200n8 console=ttyS0,115200n8 debug print-fatal-signals=1";
25*4882a593Smuzhiyun	};
26*4882a593Smuzhiyun
27*4882a593Smuzhiyun	aliases {
28*4882a593Smuzhiyun		serial0 = &uart0;
29*4882a593Smuzhiyun	};
30*4882a593Smuzhiyun
31*4882a593Smuzhiyun	fpga {
32*4882a593Smuzhiyun		compatible = "simple-bus";
33*4882a593Smuzhiyun		#address-cells = <1>;
34*4882a593Smuzhiyun		#size-cells = <1>;
35*4882a593Smuzhiyun
36*4882a593Smuzhiyun		/* only perip space at end of low mem accessible
37*4882a593Smuzhiyun			  bus addr,  parent bus addr, size    */
38*4882a593Smuzhiyun		ranges = <0x80000000 0x0 0x80000000 0x80000000>;
39*4882a593Smuzhiyun
40*4882a593Smuzhiyun		core_clk: core_clk {
41*4882a593Smuzhiyun			#clock-cells = <0>;
42*4882a593Smuzhiyun			compatible = "fixed-clock";
43*4882a593Smuzhiyun			clock-frequency = <50000000>;
44*4882a593Smuzhiyun		};
45*4882a593Smuzhiyun
46*4882a593Smuzhiyun		core_intc: interrupt-controller {
47*4882a593Smuzhiyun			compatible = "snps,archs-intc";
48*4882a593Smuzhiyun			interrupt-controller;
49*4882a593Smuzhiyun			#interrupt-cells = <1>;
50*4882a593Smuzhiyun		};
51*4882a593Smuzhiyun
52*4882a593Smuzhiyun		uart0: serial@f0000000 {
53*4882a593Smuzhiyun			compatible = "ns16550a";
54*4882a593Smuzhiyun			reg = <0xf0000000 0x2000>;
55*4882a593Smuzhiyun			interrupts = <24>;
56*4882a593Smuzhiyun			clock-frequency = <50000000>;
57*4882a593Smuzhiyun			baud = <115200>;
58*4882a593Smuzhiyun			reg-shift = <2>;
59*4882a593Smuzhiyun			reg-io-width = <4>;
60*4882a593Smuzhiyun			no-loopback-test = <1>;
61*4882a593Smuzhiyun		};
62*4882a593Smuzhiyun
63*4882a593Smuzhiyun		arcpct0: pct {
64*4882a593Smuzhiyun			compatible = "snps,archs-pct";
65*4882a593Smuzhiyun			#interrupt-cells = <1>;
66*4882a593Smuzhiyun			interrupts = <20>;
67*4882a593Smuzhiyun		};
68*4882a593Smuzhiyun
69*4882a593Smuzhiyun		virtio0: virtio@f0100000 {
70*4882a593Smuzhiyun			compatible = "virtio,mmio";
71*4882a593Smuzhiyun			reg = <0xf0100000 0x2000>;
72*4882a593Smuzhiyun			interrupts = <31>;
73*4882a593Smuzhiyun		};
74*4882a593Smuzhiyun
75*4882a593Smuzhiyun		virtio1: virtio@f0102000 {
76*4882a593Smuzhiyun			compatible = "virtio,mmio";
77*4882a593Smuzhiyun			reg = <0xf0102000 0x2000>;
78*4882a593Smuzhiyun			interrupts = <32>;
79*4882a593Smuzhiyun		};
80*4882a593Smuzhiyun
81*4882a593Smuzhiyun		virtio2: virtio@f0104000 {
82*4882a593Smuzhiyun			compatible = "virtio,mmio";
83*4882a593Smuzhiyun			reg = <0xf0104000 0x2000>;
84*4882a593Smuzhiyun			interrupts = <33>;
85*4882a593Smuzhiyun		};
86*4882a593Smuzhiyun
87*4882a593Smuzhiyun		virtio3: virtio@f0106000 {
88*4882a593Smuzhiyun			compatible = "virtio,mmio";
89*4882a593Smuzhiyun			reg = <0xf0106000 0x2000>;
90*4882a593Smuzhiyun			interrupts = <34>;
91*4882a593Smuzhiyun		};
92*4882a593Smuzhiyun
93*4882a593Smuzhiyun		virtio4: virtio@f0108000 {
94*4882a593Smuzhiyun			compatible = "virtio,mmio";
95*4882a593Smuzhiyun			reg = <0xf0108000 0x2000>;
96*4882a593Smuzhiyun			interrupts = <35>;
97*4882a593Smuzhiyun		};
98*4882a593Smuzhiyun	};
99*4882a593Smuzhiyun};
100