1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Simple pci display device. 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Framebuffer memory is pci bar 0. 6*4882a593Smuzhiyun * Configuration (read-only) is in pci config space. 7*4882a593Smuzhiyun * Format field uses drm fourcc codes. 8*4882a593Smuzhiyun * ATM only DRM_FORMAT_XRGB8888 is supported. 9*4882a593Smuzhiyun */ 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun /* pci ids */ 12*4882a593Smuzhiyun #define MDPY_PCI_VENDOR_ID PCI_VENDOR_ID_REDHAT 13*4882a593Smuzhiyun #define MDPY_PCI_DEVICE_ID 0x000f 14*4882a593Smuzhiyun #define MDPY_PCI_SUBVENDOR_ID PCI_SUBVENDOR_ID_REDHAT_QUMRANET 15*4882a593Smuzhiyun #define MDPY_PCI_SUBDEVICE_ID PCI_SUBDEVICE_ID_QEMU 16*4882a593Smuzhiyun 17*4882a593Smuzhiyun /* pci cfg space offsets for fb config (dword) */ 18*4882a593Smuzhiyun #define MDPY_VENDORCAP_OFFSET 0x40 19*4882a593Smuzhiyun #define MDPY_VENDORCAP_SIZE 0x10 20*4882a593Smuzhiyun #define MDPY_FORMAT_OFFSET (MDPY_VENDORCAP_OFFSET + 0x04) 21*4882a593Smuzhiyun #define MDPY_WIDTH_OFFSET (MDPY_VENDORCAP_OFFSET + 0x08) 22*4882a593Smuzhiyun #define MDPY_HEIGHT_OFFSET (MDPY_VENDORCAP_OFFSET + 0x0c) 23