1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * Shared Memory Communications over RDMA (SMC-R) and RoCE
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * Work Requests exploiting Infiniband API
6*4882a593Smuzhiyun *
7*4882a593Smuzhiyun * Work requests (WR) of type ib_post_send or ib_post_recv respectively
8*4882a593Smuzhiyun * are submitted to either RC SQ or RC RQ respectively
9*4882a593Smuzhiyun * (reliably connected send/receive queue)
10*4882a593Smuzhiyun * and become work queue entries (WQEs).
11*4882a593Smuzhiyun * While an SQ WR/WQE is pending, we track it until transmission completion.
12*4882a593Smuzhiyun * Through a send or receive completion queue (CQ) respectively,
13*4882a593Smuzhiyun * we get completion queue entries (CQEs) [aka work completions (WCs)].
14*4882a593Smuzhiyun * Since the CQ callback is called from IRQ context, we split work by using
15*4882a593Smuzhiyun * bottom halves implemented by tasklets.
16*4882a593Smuzhiyun *
17*4882a593Smuzhiyun * SMC uses this to exchange LLC (link layer control)
18*4882a593Smuzhiyun * and CDC (connection data control) messages.
19*4882a593Smuzhiyun *
20*4882a593Smuzhiyun * Copyright IBM Corp. 2016
21*4882a593Smuzhiyun *
22*4882a593Smuzhiyun * Author(s): Steffen Maier <maier@linux.vnet.ibm.com>
23*4882a593Smuzhiyun */
24*4882a593Smuzhiyun
25*4882a593Smuzhiyun #include <linux/atomic.h>
26*4882a593Smuzhiyun #include <linux/hashtable.h>
27*4882a593Smuzhiyun #include <linux/wait.h>
28*4882a593Smuzhiyun #include <rdma/ib_verbs.h>
29*4882a593Smuzhiyun #include <asm/div64.h>
30*4882a593Smuzhiyun
31*4882a593Smuzhiyun #include "smc.h"
32*4882a593Smuzhiyun #include "smc_wr.h"
33*4882a593Smuzhiyun
34*4882a593Smuzhiyun #define SMC_WR_MAX_POLL_CQE 10 /* max. # of compl. queue elements in 1 poll */
35*4882a593Smuzhiyun
36*4882a593Smuzhiyun #define SMC_WR_RX_HASH_BITS 4
37*4882a593Smuzhiyun static DEFINE_HASHTABLE(smc_wr_rx_hash, SMC_WR_RX_HASH_BITS);
38*4882a593Smuzhiyun static DEFINE_SPINLOCK(smc_wr_rx_hash_lock);
39*4882a593Smuzhiyun
40*4882a593Smuzhiyun struct smc_wr_tx_pend { /* control data for a pending send request */
41*4882a593Smuzhiyun u64 wr_id; /* work request id sent */
42*4882a593Smuzhiyun smc_wr_tx_handler handler;
43*4882a593Smuzhiyun enum ib_wc_status wc_status; /* CQE status */
44*4882a593Smuzhiyun struct smc_link *link;
45*4882a593Smuzhiyun u32 idx;
46*4882a593Smuzhiyun struct smc_wr_tx_pend_priv priv;
47*4882a593Smuzhiyun u8 compl_requested;
48*4882a593Smuzhiyun };
49*4882a593Smuzhiyun
50*4882a593Smuzhiyun /******************************** send queue *********************************/
51*4882a593Smuzhiyun
52*4882a593Smuzhiyun /*------------------------------- completion --------------------------------*/
53*4882a593Smuzhiyun
54*4882a593Smuzhiyun /* returns true if at least one tx work request is pending on the given link */
smc_wr_is_tx_pend(struct smc_link * link)55*4882a593Smuzhiyun static inline bool smc_wr_is_tx_pend(struct smc_link *link)
56*4882a593Smuzhiyun {
57*4882a593Smuzhiyun if (find_first_bit(link->wr_tx_mask, link->wr_tx_cnt) !=
58*4882a593Smuzhiyun link->wr_tx_cnt) {
59*4882a593Smuzhiyun return true;
60*4882a593Smuzhiyun }
61*4882a593Smuzhiyun return false;
62*4882a593Smuzhiyun }
63*4882a593Smuzhiyun
64*4882a593Smuzhiyun /* wait till all pending tx work requests on the given link are completed */
smc_wr_tx_wait_no_pending_sends(struct smc_link * link)65*4882a593Smuzhiyun void smc_wr_tx_wait_no_pending_sends(struct smc_link *link)
66*4882a593Smuzhiyun {
67*4882a593Smuzhiyun wait_event(link->wr_tx_wait, !smc_wr_is_tx_pend(link));
68*4882a593Smuzhiyun }
69*4882a593Smuzhiyun
smc_wr_tx_find_pending_index(struct smc_link * link,u64 wr_id)70*4882a593Smuzhiyun static inline int smc_wr_tx_find_pending_index(struct smc_link *link, u64 wr_id)
71*4882a593Smuzhiyun {
72*4882a593Smuzhiyun u32 i;
73*4882a593Smuzhiyun
74*4882a593Smuzhiyun for (i = 0; i < link->wr_tx_cnt; i++) {
75*4882a593Smuzhiyun if (link->wr_tx_pends[i].wr_id == wr_id)
76*4882a593Smuzhiyun return i;
77*4882a593Smuzhiyun }
78*4882a593Smuzhiyun return link->wr_tx_cnt;
79*4882a593Smuzhiyun }
80*4882a593Smuzhiyun
smc_wr_tx_process_cqe(struct ib_wc * wc)81*4882a593Smuzhiyun static inline void smc_wr_tx_process_cqe(struct ib_wc *wc)
82*4882a593Smuzhiyun {
83*4882a593Smuzhiyun struct smc_wr_tx_pend pnd_snd;
84*4882a593Smuzhiyun struct smc_link *link;
85*4882a593Smuzhiyun u32 pnd_snd_idx;
86*4882a593Smuzhiyun
87*4882a593Smuzhiyun link = wc->qp->qp_context;
88*4882a593Smuzhiyun
89*4882a593Smuzhiyun if (wc->opcode == IB_WC_REG_MR) {
90*4882a593Smuzhiyun if (wc->status)
91*4882a593Smuzhiyun link->wr_reg_state = FAILED;
92*4882a593Smuzhiyun else
93*4882a593Smuzhiyun link->wr_reg_state = CONFIRMED;
94*4882a593Smuzhiyun smc_wr_wakeup_reg_wait(link);
95*4882a593Smuzhiyun return;
96*4882a593Smuzhiyun }
97*4882a593Smuzhiyun
98*4882a593Smuzhiyun pnd_snd_idx = smc_wr_tx_find_pending_index(link, wc->wr_id);
99*4882a593Smuzhiyun if (pnd_snd_idx == link->wr_tx_cnt)
100*4882a593Smuzhiyun return;
101*4882a593Smuzhiyun link->wr_tx_pends[pnd_snd_idx].wc_status = wc->status;
102*4882a593Smuzhiyun if (link->wr_tx_pends[pnd_snd_idx].compl_requested)
103*4882a593Smuzhiyun complete(&link->wr_tx_compl[pnd_snd_idx]);
104*4882a593Smuzhiyun memcpy(&pnd_snd, &link->wr_tx_pends[pnd_snd_idx], sizeof(pnd_snd));
105*4882a593Smuzhiyun /* clear the full struct smc_wr_tx_pend including .priv */
106*4882a593Smuzhiyun memset(&link->wr_tx_pends[pnd_snd_idx], 0,
107*4882a593Smuzhiyun sizeof(link->wr_tx_pends[pnd_snd_idx]));
108*4882a593Smuzhiyun memset(&link->wr_tx_bufs[pnd_snd_idx], 0,
109*4882a593Smuzhiyun sizeof(link->wr_tx_bufs[pnd_snd_idx]));
110*4882a593Smuzhiyun if (!test_and_clear_bit(pnd_snd_idx, link->wr_tx_mask))
111*4882a593Smuzhiyun return;
112*4882a593Smuzhiyun if (wc->status) {
113*4882a593Smuzhiyun /* terminate link */
114*4882a593Smuzhiyun smcr_link_down_cond_sched(link);
115*4882a593Smuzhiyun }
116*4882a593Smuzhiyun if (pnd_snd.handler)
117*4882a593Smuzhiyun pnd_snd.handler(&pnd_snd.priv, link, wc->status);
118*4882a593Smuzhiyun wake_up(&link->wr_tx_wait);
119*4882a593Smuzhiyun }
120*4882a593Smuzhiyun
smc_wr_tx_tasklet_fn(unsigned long data)121*4882a593Smuzhiyun static void smc_wr_tx_tasklet_fn(unsigned long data)
122*4882a593Smuzhiyun {
123*4882a593Smuzhiyun struct smc_ib_device *dev = (struct smc_ib_device *)data;
124*4882a593Smuzhiyun struct ib_wc wc[SMC_WR_MAX_POLL_CQE];
125*4882a593Smuzhiyun int i = 0, rc;
126*4882a593Smuzhiyun int polled = 0;
127*4882a593Smuzhiyun
128*4882a593Smuzhiyun again:
129*4882a593Smuzhiyun polled++;
130*4882a593Smuzhiyun do {
131*4882a593Smuzhiyun memset(&wc, 0, sizeof(wc));
132*4882a593Smuzhiyun rc = ib_poll_cq(dev->roce_cq_send, SMC_WR_MAX_POLL_CQE, wc);
133*4882a593Smuzhiyun if (polled == 1) {
134*4882a593Smuzhiyun ib_req_notify_cq(dev->roce_cq_send,
135*4882a593Smuzhiyun IB_CQ_NEXT_COMP |
136*4882a593Smuzhiyun IB_CQ_REPORT_MISSED_EVENTS);
137*4882a593Smuzhiyun }
138*4882a593Smuzhiyun if (!rc)
139*4882a593Smuzhiyun break;
140*4882a593Smuzhiyun for (i = 0; i < rc; i++)
141*4882a593Smuzhiyun smc_wr_tx_process_cqe(&wc[i]);
142*4882a593Smuzhiyun } while (rc > 0);
143*4882a593Smuzhiyun if (polled == 1)
144*4882a593Smuzhiyun goto again;
145*4882a593Smuzhiyun }
146*4882a593Smuzhiyun
smc_wr_tx_cq_handler(struct ib_cq * ib_cq,void * cq_context)147*4882a593Smuzhiyun void smc_wr_tx_cq_handler(struct ib_cq *ib_cq, void *cq_context)
148*4882a593Smuzhiyun {
149*4882a593Smuzhiyun struct smc_ib_device *dev = (struct smc_ib_device *)cq_context;
150*4882a593Smuzhiyun
151*4882a593Smuzhiyun tasklet_schedule(&dev->send_tasklet);
152*4882a593Smuzhiyun }
153*4882a593Smuzhiyun
154*4882a593Smuzhiyun /*---------------------------- request submission ---------------------------*/
155*4882a593Smuzhiyun
smc_wr_tx_get_free_slot_index(struct smc_link * link,u32 * idx)156*4882a593Smuzhiyun static inline int smc_wr_tx_get_free_slot_index(struct smc_link *link, u32 *idx)
157*4882a593Smuzhiyun {
158*4882a593Smuzhiyun *idx = link->wr_tx_cnt;
159*4882a593Smuzhiyun if (!smc_link_sendable(link))
160*4882a593Smuzhiyun return -ENOLINK;
161*4882a593Smuzhiyun for_each_clear_bit(*idx, link->wr_tx_mask, link->wr_tx_cnt) {
162*4882a593Smuzhiyun if (!test_and_set_bit(*idx, link->wr_tx_mask))
163*4882a593Smuzhiyun return 0;
164*4882a593Smuzhiyun }
165*4882a593Smuzhiyun *idx = link->wr_tx_cnt;
166*4882a593Smuzhiyun return -EBUSY;
167*4882a593Smuzhiyun }
168*4882a593Smuzhiyun
169*4882a593Smuzhiyun /**
170*4882a593Smuzhiyun * smc_wr_tx_get_free_slot() - returns buffer for message assembly,
171*4882a593Smuzhiyun * and sets info for pending transmit tracking
172*4882a593Smuzhiyun * @link: Pointer to smc_link used to later send the message.
173*4882a593Smuzhiyun * @handler: Send completion handler function pointer.
174*4882a593Smuzhiyun * @wr_buf: Out value returns pointer to message buffer.
175*4882a593Smuzhiyun * @wr_rdma_buf: Out value returns pointer to rdma work request.
176*4882a593Smuzhiyun * @wr_pend_priv: Out value returns pointer serving as handler context.
177*4882a593Smuzhiyun *
178*4882a593Smuzhiyun * Return: 0 on success, or -errno on error.
179*4882a593Smuzhiyun */
smc_wr_tx_get_free_slot(struct smc_link * link,smc_wr_tx_handler handler,struct smc_wr_buf ** wr_buf,struct smc_rdma_wr ** wr_rdma_buf,struct smc_wr_tx_pend_priv ** wr_pend_priv)180*4882a593Smuzhiyun int smc_wr_tx_get_free_slot(struct smc_link *link,
181*4882a593Smuzhiyun smc_wr_tx_handler handler,
182*4882a593Smuzhiyun struct smc_wr_buf **wr_buf,
183*4882a593Smuzhiyun struct smc_rdma_wr **wr_rdma_buf,
184*4882a593Smuzhiyun struct smc_wr_tx_pend_priv **wr_pend_priv)
185*4882a593Smuzhiyun {
186*4882a593Smuzhiyun struct smc_link_group *lgr = smc_get_lgr(link);
187*4882a593Smuzhiyun struct smc_wr_tx_pend *wr_pend;
188*4882a593Smuzhiyun u32 idx = link->wr_tx_cnt;
189*4882a593Smuzhiyun struct ib_send_wr *wr_ib;
190*4882a593Smuzhiyun u64 wr_id;
191*4882a593Smuzhiyun int rc;
192*4882a593Smuzhiyun
193*4882a593Smuzhiyun *wr_buf = NULL;
194*4882a593Smuzhiyun *wr_pend_priv = NULL;
195*4882a593Smuzhiyun if (in_softirq() || lgr->terminating) {
196*4882a593Smuzhiyun rc = smc_wr_tx_get_free_slot_index(link, &idx);
197*4882a593Smuzhiyun if (rc)
198*4882a593Smuzhiyun return rc;
199*4882a593Smuzhiyun } else {
200*4882a593Smuzhiyun rc = wait_event_interruptible_timeout(
201*4882a593Smuzhiyun link->wr_tx_wait,
202*4882a593Smuzhiyun !smc_link_sendable(link) ||
203*4882a593Smuzhiyun lgr->terminating ||
204*4882a593Smuzhiyun (smc_wr_tx_get_free_slot_index(link, &idx) != -EBUSY),
205*4882a593Smuzhiyun SMC_WR_TX_WAIT_FREE_SLOT_TIME);
206*4882a593Smuzhiyun if (!rc) {
207*4882a593Smuzhiyun /* timeout - terminate link */
208*4882a593Smuzhiyun smcr_link_down_cond_sched(link);
209*4882a593Smuzhiyun return -EPIPE;
210*4882a593Smuzhiyun }
211*4882a593Smuzhiyun if (idx == link->wr_tx_cnt)
212*4882a593Smuzhiyun return -EPIPE;
213*4882a593Smuzhiyun }
214*4882a593Smuzhiyun wr_id = smc_wr_tx_get_next_wr_id(link);
215*4882a593Smuzhiyun wr_pend = &link->wr_tx_pends[idx];
216*4882a593Smuzhiyun wr_pend->wr_id = wr_id;
217*4882a593Smuzhiyun wr_pend->handler = handler;
218*4882a593Smuzhiyun wr_pend->link = link;
219*4882a593Smuzhiyun wr_pend->idx = idx;
220*4882a593Smuzhiyun wr_ib = &link->wr_tx_ibs[idx];
221*4882a593Smuzhiyun wr_ib->wr_id = wr_id;
222*4882a593Smuzhiyun *wr_buf = &link->wr_tx_bufs[idx];
223*4882a593Smuzhiyun if (wr_rdma_buf)
224*4882a593Smuzhiyun *wr_rdma_buf = &link->wr_tx_rdmas[idx];
225*4882a593Smuzhiyun *wr_pend_priv = &wr_pend->priv;
226*4882a593Smuzhiyun return 0;
227*4882a593Smuzhiyun }
228*4882a593Smuzhiyun
smc_wr_tx_put_slot(struct smc_link * link,struct smc_wr_tx_pend_priv * wr_pend_priv)229*4882a593Smuzhiyun int smc_wr_tx_put_slot(struct smc_link *link,
230*4882a593Smuzhiyun struct smc_wr_tx_pend_priv *wr_pend_priv)
231*4882a593Smuzhiyun {
232*4882a593Smuzhiyun struct smc_wr_tx_pend *pend;
233*4882a593Smuzhiyun
234*4882a593Smuzhiyun pend = container_of(wr_pend_priv, struct smc_wr_tx_pend, priv);
235*4882a593Smuzhiyun if (pend->idx < link->wr_tx_cnt) {
236*4882a593Smuzhiyun u32 idx = pend->idx;
237*4882a593Smuzhiyun
238*4882a593Smuzhiyun /* clear the full struct smc_wr_tx_pend including .priv */
239*4882a593Smuzhiyun memset(&link->wr_tx_pends[idx], 0,
240*4882a593Smuzhiyun sizeof(link->wr_tx_pends[idx]));
241*4882a593Smuzhiyun memset(&link->wr_tx_bufs[idx], 0,
242*4882a593Smuzhiyun sizeof(link->wr_tx_bufs[idx]));
243*4882a593Smuzhiyun test_and_clear_bit(idx, link->wr_tx_mask);
244*4882a593Smuzhiyun wake_up(&link->wr_tx_wait);
245*4882a593Smuzhiyun return 1;
246*4882a593Smuzhiyun }
247*4882a593Smuzhiyun
248*4882a593Smuzhiyun return 0;
249*4882a593Smuzhiyun }
250*4882a593Smuzhiyun
251*4882a593Smuzhiyun /* Send prepared WR slot via ib_post_send.
252*4882a593Smuzhiyun * @priv: pointer to smc_wr_tx_pend_priv identifying prepared message buffer
253*4882a593Smuzhiyun */
smc_wr_tx_send(struct smc_link * link,struct smc_wr_tx_pend_priv * priv)254*4882a593Smuzhiyun int smc_wr_tx_send(struct smc_link *link, struct smc_wr_tx_pend_priv *priv)
255*4882a593Smuzhiyun {
256*4882a593Smuzhiyun struct smc_wr_tx_pend *pend;
257*4882a593Smuzhiyun int rc;
258*4882a593Smuzhiyun
259*4882a593Smuzhiyun ib_req_notify_cq(link->smcibdev->roce_cq_send,
260*4882a593Smuzhiyun IB_CQ_NEXT_COMP | IB_CQ_REPORT_MISSED_EVENTS);
261*4882a593Smuzhiyun pend = container_of(priv, struct smc_wr_tx_pend, priv);
262*4882a593Smuzhiyun rc = ib_post_send(link->roce_qp, &link->wr_tx_ibs[pend->idx], NULL);
263*4882a593Smuzhiyun if (rc) {
264*4882a593Smuzhiyun smc_wr_tx_put_slot(link, priv);
265*4882a593Smuzhiyun smcr_link_down_cond_sched(link);
266*4882a593Smuzhiyun }
267*4882a593Smuzhiyun return rc;
268*4882a593Smuzhiyun }
269*4882a593Smuzhiyun
270*4882a593Smuzhiyun /* Send prepared WR slot via ib_post_send and wait for send completion
271*4882a593Smuzhiyun * notification.
272*4882a593Smuzhiyun * @priv: pointer to smc_wr_tx_pend_priv identifying prepared message buffer
273*4882a593Smuzhiyun */
smc_wr_tx_send_wait(struct smc_link * link,struct smc_wr_tx_pend_priv * priv,unsigned long timeout)274*4882a593Smuzhiyun int smc_wr_tx_send_wait(struct smc_link *link, struct smc_wr_tx_pend_priv *priv,
275*4882a593Smuzhiyun unsigned long timeout)
276*4882a593Smuzhiyun {
277*4882a593Smuzhiyun struct smc_wr_tx_pend *pend;
278*4882a593Smuzhiyun u32 pnd_idx;
279*4882a593Smuzhiyun int rc;
280*4882a593Smuzhiyun
281*4882a593Smuzhiyun pend = container_of(priv, struct smc_wr_tx_pend, priv);
282*4882a593Smuzhiyun pend->compl_requested = 1;
283*4882a593Smuzhiyun pnd_idx = pend->idx;
284*4882a593Smuzhiyun init_completion(&link->wr_tx_compl[pnd_idx]);
285*4882a593Smuzhiyun
286*4882a593Smuzhiyun rc = smc_wr_tx_send(link, priv);
287*4882a593Smuzhiyun if (rc)
288*4882a593Smuzhiyun return rc;
289*4882a593Smuzhiyun /* wait for completion by smc_wr_tx_process_cqe() */
290*4882a593Smuzhiyun rc = wait_for_completion_interruptible_timeout(
291*4882a593Smuzhiyun &link->wr_tx_compl[pnd_idx], timeout);
292*4882a593Smuzhiyun if (rc <= 0)
293*4882a593Smuzhiyun rc = -ENODATA;
294*4882a593Smuzhiyun if (rc > 0)
295*4882a593Smuzhiyun rc = 0;
296*4882a593Smuzhiyun return rc;
297*4882a593Smuzhiyun }
298*4882a593Smuzhiyun
299*4882a593Smuzhiyun /* Register a memory region and wait for result. */
smc_wr_reg_send(struct smc_link * link,struct ib_mr * mr)300*4882a593Smuzhiyun int smc_wr_reg_send(struct smc_link *link, struct ib_mr *mr)
301*4882a593Smuzhiyun {
302*4882a593Smuzhiyun int rc;
303*4882a593Smuzhiyun
304*4882a593Smuzhiyun ib_req_notify_cq(link->smcibdev->roce_cq_send,
305*4882a593Smuzhiyun IB_CQ_NEXT_COMP | IB_CQ_REPORT_MISSED_EVENTS);
306*4882a593Smuzhiyun link->wr_reg_state = POSTED;
307*4882a593Smuzhiyun link->wr_reg.wr.wr_id = (u64)(uintptr_t)mr;
308*4882a593Smuzhiyun link->wr_reg.mr = mr;
309*4882a593Smuzhiyun link->wr_reg.key = mr->rkey;
310*4882a593Smuzhiyun rc = ib_post_send(link->roce_qp, &link->wr_reg.wr, NULL);
311*4882a593Smuzhiyun if (rc)
312*4882a593Smuzhiyun return rc;
313*4882a593Smuzhiyun
314*4882a593Smuzhiyun atomic_inc(&link->wr_reg_refcnt);
315*4882a593Smuzhiyun rc = wait_event_interruptible_timeout(link->wr_reg_wait,
316*4882a593Smuzhiyun (link->wr_reg_state != POSTED),
317*4882a593Smuzhiyun SMC_WR_REG_MR_WAIT_TIME);
318*4882a593Smuzhiyun if (atomic_dec_and_test(&link->wr_reg_refcnt))
319*4882a593Smuzhiyun wake_up_all(&link->wr_reg_wait);
320*4882a593Smuzhiyun if (!rc) {
321*4882a593Smuzhiyun /* timeout - terminate link */
322*4882a593Smuzhiyun smcr_link_down_cond_sched(link);
323*4882a593Smuzhiyun return -EPIPE;
324*4882a593Smuzhiyun }
325*4882a593Smuzhiyun if (rc == -ERESTARTSYS)
326*4882a593Smuzhiyun return -EINTR;
327*4882a593Smuzhiyun switch (link->wr_reg_state) {
328*4882a593Smuzhiyun case CONFIRMED:
329*4882a593Smuzhiyun rc = 0;
330*4882a593Smuzhiyun break;
331*4882a593Smuzhiyun case FAILED:
332*4882a593Smuzhiyun rc = -EIO;
333*4882a593Smuzhiyun break;
334*4882a593Smuzhiyun case POSTED:
335*4882a593Smuzhiyun rc = -EPIPE;
336*4882a593Smuzhiyun break;
337*4882a593Smuzhiyun }
338*4882a593Smuzhiyun return rc;
339*4882a593Smuzhiyun }
340*4882a593Smuzhiyun
341*4882a593Smuzhiyun /****************************** receive queue ********************************/
342*4882a593Smuzhiyun
smc_wr_rx_register_handler(struct smc_wr_rx_handler * handler)343*4882a593Smuzhiyun int smc_wr_rx_register_handler(struct smc_wr_rx_handler *handler)
344*4882a593Smuzhiyun {
345*4882a593Smuzhiyun struct smc_wr_rx_handler *h_iter;
346*4882a593Smuzhiyun int rc = 0;
347*4882a593Smuzhiyun
348*4882a593Smuzhiyun spin_lock(&smc_wr_rx_hash_lock);
349*4882a593Smuzhiyun hash_for_each_possible(smc_wr_rx_hash, h_iter, list, handler->type) {
350*4882a593Smuzhiyun if (h_iter->type == handler->type) {
351*4882a593Smuzhiyun rc = -EEXIST;
352*4882a593Smuzhiyun goto out_unlock;
353*4882a593Smuzhiyun }
354*4882a593Smuzhiyun }
355*4882a593Smuzhiyun hash_add(smc_wr_rx_hash, &handler->list, handler->type);
356*4882a593Smuzhiyun out_unlock:
357*4882a593Smuzhiyun spin_unlock(&smc_wr_rx_hash_lock);
358*4882a593Smuzhiyun return rc;
359*4882a593Smuzhiyun }
360*4882a593Smuzhiyun
361*4882a593Smuzhiyun /* Demultiplex a received work request based on the message type to its handler.
362*4882a593Smuzhiyun * Relies on smc_wr_rx_hash having been completely filled before any IB WRs,
363*4882a593Smuzhiyun * and not being modified any more afterwards so we don't need to lock it.
364*4882a593Smuzhiyun */
smc_wr_rx_demultiplex(struct ib_wc * wc)365*4882a593Smuzhiyun static inline void smc_wr_rx_demultiplex(struct ib_wc *wc)
366*4882a593Smuzhiyun {
367*4882a593Smuzhiyun struct smc_link *link = (struct smc_link *)wc->qp->qp_context;
368*4882a593Smuzhiyun struct smc_wr_rx_handler *handler;
369*4882a593Smuzhiyun struct smc_wr_rx_hdr *wr_rx;
370*4882a593Smuzhiyun u64 temp_wr_id;
371*4882a593Smuzhiyun u32 index;
372*4882a593Smuzhiyun
373*4882a593Smuzhiyun if (wc->byte_len < sizeof(*wr_rx))
374*4882a593Smuzhiyun return; /* short message */
375*4882a593Smuzhiyun temp_wr_id = wc->wr_id;
376*4882a593Smuzhiyun index = do_div(temp_wr_id, link->wr_rx_cnt);
377*4882a593Smuzhiyun wr_rx = (struct smc_wr_rx_hdr *)&link->wr_rx_bufs[index];
378*4882a593Smuzhiyun hash_for_each_possible(smc_wr_rx_hash, handler, list, wr_rx->type) {
379*4882a593Smuzhiyun if (handler->type == wr_rx->type)
380*4882a593Smuzhiyun handler->handler(wc, wr_rx);
381*4882a593Smuzhiyun }
382*4882a593Smuzhiyun }
383*4882a593Smuzhiyun
smc_wr_rx_process_cqes(struct ib_wc wc[],int num)384*4882a593Smuzhiyun static inline void smc_wr_rx_process_cqes(struct ib_wc wc[], int num)
385*4882a593Smuzhiyun {
386*4882a593Smuzhiyun struct smc_link *link;
387*4882a593Smuzhiyun int i;
388*4882a593Smuzhiyun
389*4882a593Smuzhiyun for (i = 0; i < num; i++) {
390*4882a593Smuzhiyun link = wc[i].qp->qp_context;
391*4882a593Smuzhiyun if (wc[i].status == IB_WC_SUCCESS) {
392*4882a593Smuzhiyun link->wr_rx_tstamp = jiffies;
393*4882a593Smuzhiyun smc_wr_rx_demultiplex(&wc[i]);
394*4882a593Smuzhiyun smc_wr_rx_post(link); /* refill WR RX */
395*4882a593Smuzhiyun } else {
396*4882a593Smuzhiyun /* handle status errors */
397*4882a593Smuzhiyun switch (wc[i].status) {
398*4882a593Smuzhiyun case IB_WC_RETRY_EXC_ERR:
399*4882a593Smuzhiyun case IB_WC_RNR_RETRY_EXC_ERR:
400*4882a593Smuzhiyun case IB_WC_WR_FLUSH_ERR:
401*4882a593Smuzhiyun smcr_link_down_cond_sched(link);
402*4882a593Smuzhiyun break;
403*4882a593Smuzhiyun default:
404*4882a593Smuzhiyun smc_wr_rx_post(link); /* refill WR RX */
405*4882a593Smuzhiyun break;
406*4882a593Smuzhiyun }
407*4882a593Smuzhiyun }
408*4882a593Smuzhiyun }
409*4882a593Smuzhiyun }
410*4882a593Smuzhiyun
smc_wr_rx_tasklet_fn(unsigned long data)411*4882a593Smuzhiyun static void smc_wr_rx_tasklet_fn(unsigned long data)
412*4882a593Smuzhiyun {
413*4882a593Smuzhiyun struct smc_ib_device *dev = (struct smc_ib_device *)data;
414*4882a593Smuzhiyun struct ib_wc wc[SMC_WR_MAX_POLL_CQE];
415*4882a593Smuzhiyun int polled = 0;
416*4882a593Smuzhiyun int rc;
417*4882a593Smuzhiyun
418*4882a593Smuzhiyun again:
419*4882a593Smuzhiyun polled++;
420*4882a593Smuzhiyun do {
421*4882a593Smuzhiyun memset(&wc, 0, sizeof(wc));
422*4882a593Smuzhiyun rc = ib_poll_cq(dev->roce_cq_recv, SMC_WR_MAX_POLL_CQE, wc);
423*4882a593Smuzhiyun if (polled == 1) {
424*4882a593Smuzhiyun ib_req_notify_cq(dev->roce_cq_recv,
425*4882a593Smuzhiyun IB_CQ_SOLICITED_MASK
426*4882a593Smuzhiyun | IB_CQ_REPORT_MISSED_EVENTS);
427*4882a593Smuzhiyun }
428*4882a593Smuzhiyun if (!rc)
429*4882a593Smuzhiyun break;
430*4882a593Smuzhiyun smc_wr_rx_process_cqes(&wc[0], rc);
431*4882a593Smuzhiyun } while (rc > 0);
432*4882a593Smuzhiyun if (polled == 1)
433*4882a593Smuzhiyun goto again;
434*4882a593Smuzhiyun }
435*4882a593Smuzhiyun
smc_wr_rx_cq_handler(struct ib_cq * ib_cq,void * cq_context)436*4882a593Smuzhiyun void smc_wr_rx_cq_handler(struct ib_cq *ib_cq, void *cq_context)
437*4882a593Smuzhiyun {
438*4882a593Smuzhiyun struct smc_ib_device *dev = (struct smc_ib_device *)cq_context;
439*4882a593Smuzhiyun
440*4882a593Smuzhiyun tasklet_schedule(&dev->recv_tasklet);
441*4882a593Smuzhiyun }
442*4882a593Smuzhiyun
smc_wr_rx_post_init(struct smc_link * link)443*4882a593Smuzhiyun int smc_wr_rx_post_init(struct smc_link *link)
444*4882a593Smuzhiyun {
445*4882a593Smuzhiyun u32 i;
446*4882a593Smuzhiyun int rc = 0;
447*4882a593Smuzhiyun
448*4882a593Smuzhiyun for (i = 0; i < link->wr_rx_cnt; i++)
449*4882a593Smuzhiyun rc = smc_wr_rx_post(link);
450*4882a593Smuzhiyun return rc;
451*4882a593Smuzhiyun }
452*4882a593Smuzhiyun
453*4882a593Smuzhiyun /***************************** init, exit, misc ******************************/
454*4882a593Smuzhiyun
smc_wr_remember_qp_attr(struct smc_link * lnk)455*4882a593Smuzhiyun void smc_wr_remember_qp_attr(struct smc_link *lnk)
456*4882a593Smuzhiyun {
457*4882a593Smuzhiyun struct ib_qp_attr *attr = &lnk->qp_attr;
458*4882a593Smuzhiyun struct ib_qp_init_attr init_attr;
459*4882a593Smuzhiyun
460*4882a593Smuzhiyun memset(attr, 0, sizeof(*attr));
461*4882a593Smuzhiyun memset(&init_attr, 0, sizeof(init_attr));
462*4882a593Smuzhiyun ib_query_qp(lnk->roce_qp, attr,
463*4882a593Smuzhiyun IB_QP_STATE |
464*4882a593Smuzhiyun IB_QP_CUR_STATE |
465*4882a593Smuzhiyun IB_QP_PKEY_INDEX |
466*4882a593Smuzhiyun IB_QP_PORT |
467*4882a593Smuzhiyun IB_QP_QKEY |
468*4882a593Smuzhiyun IB_QP_AV |
469*4882a593Smuzhiyun IB_QP_PATH_MTU |
470*4882a593Smuzhiyun IB_QP_TIMEOUT |
471*4882a593Smuzhiyun IB_QP_RETRY_CNT |
472*4882a593Smuzhiyun IB_QP_RNR_RETRY |
473*4882a593Smuzhiyun IB_QP_RQ_PSN |
474*4882a593Smuzhiyun IB_QP_ALT_PATH |
475*4882a593Smuzhiyun IB_QP_MIN_RNR_TIMER |
476*4882a593Smuzhiyun IB_QP_SQ_PSN |
477*4882a593Smuzhiyun IB_QP_PATH_MIG_STATE |
478*4882a593Smuzhiyun IB_QP_CAP |
479*4882a593Smuzhiyun IB_QP_DEST_QPN,
480*4882a593Smuzhiyun &init_attr);
481*4882a593Smuzhiyun
482*4882a593Smuzhiyun lnk->wr_tx_cnt = min_t(size_t, SMC_WR_BUF_CNT,
483*4882a593Smuzhiyun lnk->qp_attr.cap.max_send_wr);
484*4882a593Smuzhiyun lnk->wr_rx_cnt = min_t(size_t, SMC_WR_BUF_CNT * 3,
485*4882a593Smuzhiyun lnk->qp_attr.cap.max_recv_wr);
486*4882a593Smuzhiyun }
487*4882a593Smuzhiyun
smc_wr_init_sge(struct smc_link * lnk)488*4882a593Smuzhiyun static void smc_wr_init_sge(struct smc_link *lnk)
489*4882a593Smuzhiyun {
490*4882a593Smuzhiyun u32 i;
491*4882a593Smuzhiyun
492*4882a593Smuzhiyun for (i = 0; i < lnk->wr_tx_cnt; i++) {
493*4882a593Smuzhiyun lnk->wr_tx_sges[i].addr =
494*4882a593Smuzhiyun lnk->wr_tx_dma_addr + i * SMC_WR_BUF_SIZE;
495*4882a593Smuzhiyun lnk->wr_tx_sges[i].length = SMC_WR_TX_SIZE;
496*4882a593Smuzhiyun lnk->wr_tx_sges[i].lkey = lnk->roce_pd->local_dma_lkey;
497*4882a593Smuzhiyun lnk->wr_tx_rdma_sges[i].tx_rdma_sge[0].wr_tx_rdma_sge[0].lkey =
498*4882a593Smuzhiyun lnk->roce_pd->local_dma_lkey;
499*4882a593Smuzhiyun lnk->wr_tx_rdma_sges[i].tx_rdma_sge[0].wr_tx_rdma_sge[1].lkey =
500*4882a593Smuzhiyun lnk->roce_pd->local_dma_lkey;
501*4882a593Smuzhiyun lnk->wr_tx_rdma_sges[i].tx_rdma_sge[1].wr_tx_rdma_sge[0].lkey =
502*4882a593Smuzhiyun lnk->roce_pd->local_dma_lkey;
503*4882a593Smuzhiyun lnk->wr_tx_rdma_sges[i].tx_rdma_sge[1].wr_tx_rdma_sge[1].lkey =
504*4882a593Smuzhiyun lnk->roce_pd->local_dma_lkey;
505*4882a593Smuzhiyun lnk->wr_tx_ibs[i].next = NULL;
506*4882a593Smuzhiyun lnk->wr_tx_ibs[i].sg_list = &lnk->wr_tx_sges[i];
507*4882a593Smuzhiyun lnk->wr_tx_ibs[i].num_sge = 1;
508*4882a593Smuzhiyun lnk->wr_tx_ibs[i].opcode = IB_WR_SEND;
509*4882a593Smuzhiyun lnk->wr_tx_ibs[i].send_flags =
510*4882a593Smuzhiyun IB_SEND_SIGNALED | IB_SEND_SOLICITED;
511*4882a593Smuzhiyun lnk->wr_tx_rdmas[i].wr_tx_rdma[0].wr.opcode = IB_WR_RDMA_WRITE;
512*4882a593Smuzhiyun lnk->wr_tx_rdmas[i].wr_tx_rdma[1].wr.opcode = IB_WR_RDMA_WRITE;
513*4882a593Smuzhiyun lnk->wr_tx_rdmas[i].wr_tx_rdma[0].wr.sg_list =
514*4882a593Smuzhiyun lnk->wr_tx_rdma_sges[i].tx_rdma_sge[0].wr_tx_rdma_sge;
515*4882a593Smuzhiyun lnk->wr_tx_rdmas[i].wr_tx_rdma[1].wr.sg_list =
516*4882a593Smuzhiyun lnk->wr_tx_rdma_sges[i].tx_rdma_sge[1].wr_tx_rdma_sge;
517*4882a593Smuzhiyun }
518*4882a593Smuzhiyun for (i = 0; i < lnk->wr_rx_cnt; i++) {
519*4882a593Smuzhiyun lnk->wr_rx_sges[i].addr =
520*4882a593Smuzhiyun lnk->wr_rx_dma_addr + i * SMC_WR_BUF_SIZE;
521*4882a593Smuzhiyun lnk->wr_rx_sges[i].length = SMC_WR_BUF_SIZE;
522*4882a593Smuzhiyun lnk->wr_rx_sges[i].lkey = lnk->roce_pd->local_dma_lkey;
523*4882a593Smuzhiyun lnk->wr_rx_ibs[i].next = NULL;
524*4882a593Smuzhiyun lnk->wr_rx_ibs[i].sg_list = &lnk->wr_rx_sges[i];
525*4882a593Smuzhiyun lnk->wr_rx_ibs[i].num_sge = 1;
526*4882a593Smuzhiyun }
527*4882a593Smuzhiyun lnk->wr_reg.wr.next = NULL;
528*4882a593Smuzhiyun lnk->wr_reg.wr.num_sge = 0;
529*4882a593Smuzhiyun lnk->wr_reg.wr.send_flags = IB_SEND_SIGNALED;
530*4882a593Smuzhiyun lnk->wr_reg.wr.opcode = IB_WR_REG_MR;
531*4882a593Smuzhiyun lnk->wr_reg.access = IB_ACCESS_LOCAL_WRITE | IB_ACCESS_REMOTE_WRITE;
532*4882a593Smuzhiyun }
533*4882a593Smuzhiyun
smc_wr_free_link(struct smc_link * lnk)534*4882a593Smuzhiyun void smc_wr_free_link(struct smc_link *lnk)
535*4882a593Smuzhiyun {
536*4882a593Smuzhiyun struct ib_device *ibdev;
537*4882a593Smuzhiyun
538*4882a593Smuzhiyun if (!lnk->smcibdev)
539*4882a593Smuzhiyun return;
540*4882a593Smuzhiyun ibdev = lnk->smcibdev->ibdev;
541*4882a593Smuzhiyun
542*4882a593Smuzhiyun smc_wr_wakeup_reg_wait(lnk);
543*4882a593Smuzhiyun smc_wr_wakeup_tx_wait(lnk);
544*4882a593Smuzhiyun
545*4882a593Smuzhiyun smc_wr_tx_wait_no_pending_sends(lnk);
546*4882a593Smuzhiyun wait_event(lnk->wr_reg_wait, (!atomic_read(&lnk->wr_reg_refcnt)));
547*4882a593Smuzhiyun wait_event(lnk->wr_tx_wait, (!atomic_read(&lnk->wr_tx_refcnt)));
548*4882a593Smuzhiyun
549*4882a593Smuzhiyun if (lnk->wr_rx_dma_addr) {
550*4882a593Smuzhiyun ib_dma_unmap_single(ibdev, lnk->wr_rx_dma_addr,
551*4882a593Smuzhiyun SMC_WR_BUF_SIZE * lnk->wr_rx_cnt,
552*4882a593Smuzhiyun DMA_FROM_DEVICE);
553*4882a593Smuzhiyun lnk->wr_rx_dma_addr = 0;
554*4882a593Smuzhiyun }
555*4882a593Smuzhiyun if (lnk->wr_tx_dma_addr) {
556*4882a593Smuzhiyun ib_dma_unmap_single(ibdev, lnk->wr_tx_dma_addr,
557*4882a593Smuzhiyun SMC_WR_BUF_SIZE * lnk->wr_tx_cnt,
558*4882a593Smuzhiyun DMA_TO_DEVICE);
559*4882a593Smuzhiyun lnk->wr_tx_dma_addr = 0;
560*4882a593Smuzhiyun }
561*4882a593Smuzhiyun }
562*4882a593Smuzhiyun
smc_wr_free_link_mem(struct smc_link * lnk)563*4882a593Smuzhiyun void smc_wr_free_link_mem(struct smc_link *lnk)
564*4882a593Smuzhiyun {
565*4882a593Smuzhiyun kfree(lnk->wr_tx_compl);
566*4882a593Smuzhiyun lnk->wr_tx_compl = NULL;
567*4882a593Smuzhiyun kfree(lnk->wr_tx_pends);
568*4882a593Smuzhiyun lnk->wr_tx_pends = NULL;
569*4882a593Smuzhiyun kfree(lnk->wr_tx_mask);
570*4882a593Smuzhiyun lnk->wr_tx_mask = NULL;
571*4882a593Smuzhiyun kfree(lnk->wr_tx_sges);
572*4882a593Smuzhiyun lnk->wr_tx_sges = NULL;
573*4882a593Smuzhiyun kfree(lnk->wr_tx_rdma_sges);
574*4882a593Smuzhiyun lnk->wr_tx_rdma_sges = NULL;
575*4882a593Smuzhiyun kfree(lnk->wr_rx_sges);
576*4882a593Smuzhiyun lnk->wr_rx_sges = NULL;
577*4882a593Smuzhiyun kfree(lnk->wr_tx_rdmas);
578*4882a593Smuzhiyun lnk->wr_tx_rdmas = NULL;
579*4882a593Smuzhiyun kfree(lnk->wr_rx_ibs);
580*4882a593Smuzhiyun lnk->wr_rx_ibs = NULL;
581*4882a593Smuzhiyun kfree(lnk->wr_tx_ibs);
582*4882a593Smuzhiyun lnk->wr_tx_ibs = NULL;
583*4882a593Smuzhiyun kfree(lnk->wr_tx_bufs);
584*4882a593Smuzhiyun lnk->wr_tx_bufs = NULL;
585*4882a593Smuzhiyun kfree(lnk->wr_rx_bufs);
586*4882a593Smuzhiyun lnk->wr_rx_bufs = NULL;
587*4882a593Smuzhiyun }
588*4882a593Smuzhiyun
smc_wr_alloc_link_mem(struct smc_link * link)589*4882a593Smuzhiyun int smc_wr_alloc_link_mem(struct smc_link *link)
590*4882a593Smuzhiyun {
591*4882a593Smuzhiyun /* allocate link related memory */
592*4882a593Smuzhiyun link->wr_tx_bufs = kcalloc(SMC_WR_BUF_CNT, SMC_WR_BUF_SIZE, GFP_KERNEL);
593*4882a593Smuzhiyun if (!link->wr_tx_bufs)
594*4882a593Smuzhiyun goto no_mem;
595*4882a593Smuzhiyun link->wr_rx_bufs = kcalloc(SMC_WR_BUF_CNT * 3, SMC_WR_BUF_SIZE,
596*4882a593Smuzhiyun GFP_KERNEL);
597*4882a593Smuzhiyun if (!link->wr_rx_bufs)
598*4882a593Smuzhiyun goto no_mem_wr_tx_bufs;
599*4882a593Smuzhiyun link->wr_tx_ibs = kcalloc(SMC_WR_BUF_CNT, sizeof(link->wr_tx_ibs[0]),
600*4882a593Smuzhiyun GFP_KERNEL);
601*4882a593Smuzhiyun if (!link->wr_tx_ibs)
602*4882a593Smuzhiyun goto no_mem_wr_rx_bufs;
603*4882a593Smuzhiyun link->wr_rx_ibs = kcalloc(SMC_WR_BUF_CNT * 3,
604*4882a593Smuzhiyun sizeof(link->wr_rx_ibs[0]),
605*4882a593Smuzhiyun GFP_KERNEL);
606*4882a593Smuzhiyun if (!link->wr_rx_ibs)
607*4882a593Smuzhiyun goto no_mem_wr_tx_ibs;
608*4882a593Smuzhiyun link->wr_tx_rdmas = kcalloc(SMC_WR_BUF_CNT,
609*4882a593Smuzhiyun sizeof(link->wr_tx_rdmas[0]),
610*4882a593Smuzhiyun GFP_KERNEL);
611*4882a593Smuzhiyun if (!link->wr_tx_rdmas)
612*4882a593Smuzhiyun goto no_mem_wr_rx_ibs;
613*4882a593Smuzhiyun link->wr_tx_rdma_sges = kcalloc(SMC_WR_BUF_CNT,
614*4882a593Smuzhiyun sizeof(link->wr_tx_rdma_sges[0]),
615*4882a593Smuzhiyun GFP_KERNEL);
616*4882a593Smuzhiyun if (!link->wr_tx_rdma_sges)
617*4882a593Smuzhiyun goto no_mem_wr_tx_rdmas;
618*4882a593Smuzhiyun link->wr_tx_sges = kcalloc(SMC_WR_BUF_CNT, sizeof(link->wr_tx_sges[0]),
619*4882a593Smuzhiyun GFP_KERNEL);
620*4882a593Smuzhiyun if (!link->wr_tx_sges)
621*4882a593Smuzhiyun goto no_mem_wr_tx_rdma_sges;
622*4882a593Smuzhiyun link->wr_rx_sges = kcalloc(SMC_WR_BUF_CNT * 3,
623*4882a593Smuzhiyun sizeof(link->wr_rx_sges[0]),
624*4882a593Smuzhiyun GFP_KERNEL);
625*4882a593Smuzhiyun if (!link->wr_rx_sges)
626*4882a593Smuzhiyun goto no_mem_wr_tx_sges;
627*4882a593Smuzhiyun link->wr_tx_mask = kcalloc(BITS_TO_LONGS(SMC_WR_BUF_CNT),
628*4882a593Smuzhiyun sizeof(*link->wr_tx_mask),
629*4882a593Smuzhiyun GFP_KERNEL);
630*4882a593Smuzhiyun if (!link->wr_tx_mask)
631*4882a593Smuzhiyun goto no_mem_wr_rx_sges;
632*4882a593Smuzhiyun link->wr_tx_pends = kcalloc(SMC_WR_BUF_CNT,
633*4882a593Smuzhiyun sizeof(link->wr_tx_pends[0]),
634*4882a593Smuzhiyun GFP_KERNEL);
635*4882a593Smuzhiyun if (!link->wr_tx_pends)
636*4882a593Smuzhiyun goto no_mem_wr_tx_mask;
637*4882a593Smuzhiyun link->wr_tx_compl = kcalloc(SMC_WR_BUF_CNT,
638*4882a593Smuzhiyun sizeof(link->wr_tx_compl[0]),
639*4882a593Smuzhiyun GFP_KERNEL);
640*4882a593Smuzhiyun if (!link->wr_tx_compl)
641*4882a593Smuzhiyun goto no_mem_wr_tx_pends;
642*4882a593Smuzhiyun return 0;
643*4882a593Smuzhiyun
644*4882a593Smuzhiyun no_mem_wr_tx_pends:
645*4882a593Smuzhiyun kfree(link->wr_tx_pends);
646*4882a593Smuzhiyun no_mem_wr_tx_mask:
647*4882a593Smuzhiyun kfree(link->wr_tx_mask);
648*4882a593Smuzhiyun no_mem_wr_rx_sges:
649*4882a593Smuzhiyun kfree(link->wr_rx_sges);
650*4882a593Smuzhiyun no_mem_wr_tx_sges:
651*4882a593Smuzhiyun kfree(link->wr_tx_sges);
652*4882a593Smuzhiyun no_mem_wr_tx_rdma_sges:
653*4882a593Smuzhiyun kfree(link->wr_tx_rdma_sges);
654*4882a593Smuzhiyun no_mem_wr_tx_rdmas:
655*4882a593Smuzhiyun kfree(link->wr_tx_rdmas);
656*4882a593Smuzhiyun no_mem_wr_rx_ibs:
657*4882a593Smuzhiyun kfree(link->wr_rx_ibs);
658*4882a593Smuzhiyun no_mem_wr_tx_ibs:
659*4882a593Smuzhiyun kfree(link->wr_tx_ibs);
660*4882a593Smuzhiyun no_mem_wr_rx_bufs:
661*4882a593Smuzhiyun kfree(link->wr_rx_bufs);
662*4882a593Smuzhiyun no_mem_wr_tx_bufs:
663*4882a593Smuzhiyun kfree(link->wr_tx_bufs);
664*4882a593Smuzhiyun no_mem:
665*4882a593Smuzhiyun return -ENOMEM;
666*4882a593Smuzhiyun }
667*4882a593Smuzhiyun
smc_wr_remove_dev(struct smc_ib_device * smcibdev)668*4882a593Smuzhiyun void smc_wr_remove_dev(struct smc_ib_device *smcibdev)
669*4882a593Smuzhiyun {
670*4882a593Smuzhiyun tasklet_kill(&smcibdev->recv_tasklet);
671*4882a593Smuzhiyun tasklet_kill(&smcibdev->send_tasklet);
672*4882a593Smuzhiyun }
673*4882a593Smuzhiyun
smc_wr_add_dev(struct smc_ib_device * smcibdev)674*4882a593Smuzhiyun void smc_wr_add_dev(struct smc_ib_device *smcibdev)
675*4882a593Smuzhiyun {
676*4882a593Smuzhiyun tasklet_init(&smcibdev->recv_tasklet, smc_wr_rx_tasklet_fn,
677*4882a593Smuzhiyun (unsigned long)smcibdev);
678*4882a593Smuzhiyun tasklet_init(&smcibdev->send_tasklet, smc_wr_tx_tasklet_fn,
679*4882a593Smuzhiyun (unsigned long)smcibdev);
680*4882a593Smuzhiyun }
681*4882a593Smuzhiyun
smc_wr_create_link(struct smc_link * lnk)682*4882a593Smuzhiyun int smc_wr_create_link(struct smc_link *lnk)
683*4882a593Smuzhiyun {
684*4882a593Smuzhiyun struct ib_device *ibdev = lnk->smcibdev->ibdev;
685*4882a593Smuzhiyun int rc = 0;
686*4882a593Smuzhiyun
687*4882a593Smuzhiyun smc_wr_tx_set_wr_id(&lnk->wr_tx_id, 0);
688*4882a593Smuzhiyun lnk->wr_rx_id = 0;
689*4882a593Smuzhiyun lnk->wr_rx_dma_addr = ib_dma_map_single(
690*4882a593Smuzhiyun ibdev, lnk->wr_rx_bufs, SMC_WR_BUF_SIZE * lnk->wr_rx_cnt,
691*4882a593Smuzhiyun DMA_FROM_DEVICE);
692*4882a593Smuzhiyun if (ib_dma_mapping_error(ibdev, lnk->wr_rx_dma_addr)) {
693*4882a593Smuzhiyun lnk->wr_rx_dma_addr = 0;
694*4882a593Smuzhiyun rc = -EIO;
695*4882a593Smuzhiyun goto out;
696*4882a593Smuzhiyun }
697*4882a593Smuzhiyun lnk->wr_tx_dma_addr = ib_dma_map_single(
698*4882a593Smuzhiyun ibdev, lnk->wr_tx_bufs, SMC_WR_BUF_SIZE * lnk->wr_tx_cnt,
699*4882a593Smuzhiyun DMA_TO_DEVICE);
700*4882a593Smuzhiyun if (ib_dma_mapping_error(ibdev, lnk->wr_tx_dma_addr)) {
701*4882a593Smuzhiyun rc = -EIO;
702*4882a593Smuzhiyun goto dma_unmap;
703*4882a593Smuzhiyun }
704*4882a593Smuzhiyun smc_wr_init_sge(lnk);
705*4882a593Smuzhiyun memset(lnk->wr_tx_mask, 0,
706*4882a593Smuzhiyun BITS_TO_LONGS(SMC_WR_BUF_CNT) * sizeof(*lnk->wr_tx_mask));
707*4882a593Smuzhiyun init_waitqueue_head(&lnk->wr_tx_wait);
708*4882a593Smuzhiyun atomic_set(&lnk->wr_tx_refcnt, 0);
709*4882a593Smuzhiyun init_waitqueue_head(&lnk->wr_reg_wait);
710*4882a593Smuzhiyun atomic_set(&lnk->wr_reg_refcnt, 0);
711*4882a593Smuzhiyun return rc;
712*4882a593Smuzhiyun
713*4882a593Smuzhiyun dma_unmap:
714*4882a593Smuzhiyun ib_dma_unmap_single(ibdev, lnk->wr_rx_dma_addr,
715*4882a593Smuzhiyun SMC_WR_BUF_SIZE * lnk->wr_rx_cnt,
716*4882a593Smuzhiyun DMA_FROM_DEVICE);
717*4882a593Smuzhiyun lnk->wr_rx_dma_addr = 0;
718*4882a593Smuzhiyun out:
719*4882a593Smuzhiyun return rc;
720*4882a593Smuzhiyun }
721