1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-or-later
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * Copyright (C) 1999 ARM Limited
4*4882a593Smuzhiyun * Copyright (C) 2000 Deep Blue Solutions Ltd
5*4882a593Smuzhiyun * Copyright 2006-2007,2010 Freescale Semiconductor, Inc. All Rights Reserved.
6*4882a593Smuzhiyun * Copyright 2008 Juergen Beisert, kernel@pengutronix.de
7*4882a593Smuzhiyun * Copyright 2009 Ilya Yanok, Emcraft Systems Ltd, yanok@emcraft.com
8*4882a593Smuzhiyun * Copyright (C) 2011 Wolfram Sang, Pengutronix e.K.
9*4882a593Smuzhiyun */
10*4882a593Smuzhiyun
11*4882a593Smuzhiyun #include <linux/io.h>
12*4882a593Smuzhiyun #include <linux/errno.h>
13*4882a593Smuzhiyun #include <linux/delay.h>
14*4882a593Smuzhiyun #include <linux/compiler.h>
15*4882a593Smuzhiyun #include <linux/export.h>
16*4882a593Smuzhiyun #include <linux/stmp_device.h>
17*4882a593Smuzhiyun
18*4882a593Smuzhiyun #define STMP_MODULE_CLKGATE (1 << 30)
19*4882a593Smuzhiyun #define STMP_MODULE_SFTRST (1 << 31)
20*4882a593Smuzhiyun
21*4882a593Smuzhiyun /*
22*4882a593Smuzhiyun * Clear the bit and poll it cleared. This is usually called with
23*4882a593Smuzhiyun * a reset address and mask being either SFTRST(bit 31) or CLKGATE
24*4882a593Smuzhiyun * (bit 30).
25*4882a593Smuzhiyun */
stmp_clear_poll_bit(void __iomem * addr,u32 mask)26*4882a593Smuzhiyun static int stmp_clear_poll_bit(void __iomem *addr, u32 mask)
27*4882a593Smuzhiyun {
28*4882a593Smuzhiyun int timeout = 0x400;
29*4882a593Smuzhiyun
30*4882a593Smuzhiyun writel(mask, addr + STMP_OFFSET_REG_CLR);
31*4882a593Smuzhiyun udelay(1);
32*4882a593Smuzhiyun while ((readl(addr) & mask) && --timeout)
33*4882a593Smuzhiyun /* nothing */;
34*4882a593Smuzhiyun
35*4882a593Smuzhiyun return !timeout;
36*4882a593Smuzhiyun }
37*4882a593Smuzhiyun
stmp_reset_block(void __iomem * reset_addr)38*4882a593Smuzhiyun int stmp_reset_block(void __iomem *reset_addr)
39*4882a593Smuzhiyun {
40*4882a593Smuzhiyun int ret;
41*4882a593Smuzhiyun int timeout = 0x400;
42*4882a593Smuzhiyun
43*4882a593Smuzhiyun /* clear and poll SFTRST */
44*4882a593Smuzhiyun ret = stmp_clear_poll_bit(reset_addr, STMP_MODULE_SFTRST);
45*4882a593Smuzhiyun if (unlikely(ret))
46*4882a593Smuzhiyun goto error;
47*4882a593Smuzhiyun
48*4882a593Smuzhiyun /* clear CLKGATE */
49*4882a593Smuzhiyun writel(STMP_MODULE_CLKGATE, reset_addr + STMP_OFFSET_REG_CLR);
50*4882a593Smuzhiyun
51*4882a593Smuzhiyun /* set SFTRST to reset the block */
52*4882a593Smuzhiyun writel(STMP_MODULE_SFTRST, reset_addr + STMP_OFFSET_REG_SET);
53*4882a593Smuzhiyun udelay(1);
54*4882a593Smuzhiyun
55*4882a593Smuzhiyun /* poll CLKGATE becoming set */
56*4882a593Smuzhiyun while ((!(readl(reset_addr) & STMP_MODULE_CLKGATE)) && --timeout)
57*4882a593Smuzhiyun /* nothing */;
58*4882a593Smuzhiyun if (unlikely(!timeout))
59*4882a593Smuzhiyun goto error;
60*4882a593Smuzhiyun
61*4882a593Smuzhiyun /* clear and poll SFTRST */
62*4882a593Smuzhiyun ret = stmp_clear_poll_bit(reset_addr, STMP_MODULE_SFTRST);
63*4882a593Smuzhiyun if (unlikely(ret))
64*4882a593Smuzhiyun goto error;
65*4882a593Smuzhiyun
66*4882a593Smuzhiyun /* clear and poll CLKGATE */
67*4882a593Smuzhiyun ret = stmp_clear_poll_bit(reset_addr, STMP_MODULE_CLKGATE);
68*4882a593Smuzhiyun if (unlikely(ret))
69*4882a593Smuzhiyun goto error;
70*4882a593Smuzhiyun
71*4882a593Smuzhiyun return 0;
72*4882a593Smuzhiyun
73*4882a593Smuzhiyun error:
74*4882a593Smuzhiyun pr_err("%s(%p): module reset timeout\n", __func__, reset_addr);
75*4882a593Smuzhiyun return -ETIMEDOUT;
76*4882a593Smuzhiyun }
77*4882a593Smuzhiyun EXPORT_SYMBOL(stmp_reset_block);
78