1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-or-later */ 2*4882a593Smuzhiyun /* ----------------------------------------------------------------------- * 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * Copyright 2002-2004 H. Peter Anvin - All Rights Reserved 5*4882a593Smuzhiyun * 6*4882a593Smuzhiyun * ----------------------------------------------------------------------- */ 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun /* 9*4882a593Smuzhiyun * raid6/x86.h 10*4882a593Smuzhiyun * 11*4882a593Smuzhiyun * Definitions common to x86 and x86-64 RAID-6 code only 12*4882a593Smuzhiyun */ 13*4882a593Smuzhiyun 14*4882a593Smuzhiyun #ifndef LINUX_RAID_RAID6X86_H 15*4882a593Smuzhiyun #define LINUX_RAID_RAID6X86_H 16*4882a593Smuzhiyun 17*4882a593Smuzhiyun #if (defined(__i386__) || defined(__x86_64__)) && !defined(__arch_um__) 18*4882a593Smuzhiyun 19*4882a593Smuzhiyun #ifdef __KERNEL__ /* Real code */ 20*4882a593Smuzhiyun 21*4882a593Smuzhiyun #include <asm/fpu/api.h> 22*4882a593Smuzhiyun 23*4882a593Smuzhiyun #else /* Dummy code for user space testing */ 24*4882a593Smuzhiyun kernel_fpu_begin(void)25*4882a593Smuzhiyunstatic inline void kernel_fpu_begin(void) 26*4882a593Smuzhiyun { 27*4882a593Smuzhiyun } 28*4882a593Smuzhiyun kernel_fpu_end(void)29*4882a593Smuzhiyunstatic inline void kernel_fpu_end(void) 30*4882a593Smuzhiyun { 31*4882a593Smuzhiyun } 32*4882a593Smuzhiyun 33*4882a593Smuzhiyun #define __aligned(x) __attribute__((aligned(x))) 34*4882a593Smuzhiyun 35*4882a593Smuzhiyun #define X86_FEATURE_MMX (0*32+23) /* Multimedia Extensions */ 36*4882a593Smuzhiyun #define X86_FEATURE_FXSR (0*32+24) /* FXSAVE and FXRSTOR instructions 37*4882a593Smuzhiyun * (fast save and restore) */ 38*4882a593Smuzhiyun #define X86_FEATURE_XMM (0*32+25) /* Streaming SIMD Extensions */ 39*4882a593Smuzhiyun #define X86_FEATURE_XMM2 (0*32+26) /* Streaming SIMD Extensions-2 */ 40*4882a593Smuzhiyun #define X86_FEATURE_XMM3 (4*32+ 0) /* "pni" SSE-3 */ 41*4882a593Smuzhiyun #define X86_FEATURE_SSSE3 (4*32+ 9) /* Supplemental SSE-3 */ 42*4882a593Smuzhiyun #define X86_FEATURE_AVX (4*32+28) /* Advanced Vector Extensions */ 43*4882a593Smuzhiyun #define X86_FEATURE_AVX2 (9*32+ 5) /* AVX2 instructions */ 44*4882a593Smuzhiyun #define X86_FEATURE_AVX512F (9*32+16) /* AVX-512 Foundation */ 45*4882a593Smuzhiyun #define X86_FEATURE_AVX512DQ (9*32+17) /* AVX-512 DQ (Double/Quad granular) 46*4882a593Smuzhiyun * Instructions 47*4882a593Smuzhiyun */ 48*4882a593Smuzhiyun #define X86_FEATURE_AVX512BW (9*32+30) /* AVX-512 BW (Byte/Word granular) 49*4882a593Smuzhiyun * Instructions 50*4882a593Smuzhiyun */ 51*4882a593Smuzhiyun #define X86_FEATURE_AVX512VL (9*32+31) /* AVX-512 VL (128/256 Vector Length) 52*4882a593Smuzhiyun * Extensions 53*4882a593Smuzhiyun */ 54*4882a593Smuzhiyun #define X86_FEATURE_MMXEXT (1*32+22) /* AMD MMX extensions */ 55*4882a593Smuzhiyun 56*4882a593Smuzhiyun /* Should work well enough on modern CPUs for testing */ boot_cpu_has(int flag)57*4882a593Smuzhiyunstatic inline int boot_cpu_has(int flag) 58*4882a593Smuzhiyun { 59*4882a593Smuzhiyun u32 eax, ebx, ecx, edx; 60*4882a593Smuzhiyun 61*4882a593Smuzhiyun eax = (flag & 0x100) ? 7 : 62*4882a593Smuzhiyun (flag & 0x20) ? 0x80000001 : 1; 63*4882a593Smuzhiyun ecx = 0; 64*4882a593Smuzhiyun 65*4882a593Smuzhiyun asm volatile("cpuid" 66*4882a593Smuzhiyun : "+a" (eax), "=b" (ebx), "=d" (edx), "+c" (ecx)); 67*4882a593Smuzhiyun 68*4882a593Smuzhiyun return ((flag & 0x100 ? ebx : 69*4882a593Smuzhiyun (flag & 0x80) ? ecx : edx) >> (flag & 31)) & 1; 70*4882a593Smuzhiyun } 71*4882a593Smuzhiyun 72*4882a593Smuzhiyun #endif /* ndef __KERNEL__ */ 73*4882a593Smuzhiyun 74*4882a593Smuzhiyun #endif 75*4882a593Smuzhiyun #endif 76