xref: /OK3568_Linux_fs/kernel/include/xen/interface/physdev.h (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun  * Permission is hereby granted, free of charge, to any person obtaining a copy
3*4882a593Smuzhiyun  * of this software and associated documentation files (the "Software"), to
4*4882a593Smuzhiyun  * deal in the Software without restriction, including without limitation the
5*4882a593Smuzhiyun  * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
6*4882a593Smuzhiyun  * sell copies of the Software, and to permit persons to whom the Software is
7*4882a593Smuzhiyun  * furnished to do so, subject to the following conditions:
8*4882a593Smuzhiyun  *
9*4882a593Smuzhiyun  * The above copyright notice and this permission notice shall be included in
10*4882a593Smuzhiyun  * all copies or substantial portions of the Software.
11*4882a593Smuzhiyun  *
12*4882a593Smuzhiyun  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
13*4882a593Smuzhiyun  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
14*4882a593Smuzhiyun  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
15*4882a593Smuzhiyun  * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
16*4882a593Smuzhiyun  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
17*4882a593Smuzhiyun  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
18*4882a593Smuzhiyun  * DEALINGS IN THE SOFTWARE.
19*4882a593Smuzhiyun  */
20*4882a593Smuzhiyun 
21*4882a593Smuzhiyun #ifndef __XEN_PUBLIC_PHYSDEV_H__
22*4882a593Smuzhiyun #define __XEN_PUBLIC_PHYSDEV_H__
23*4882a593Smuzhiyun 
24*4882a593Smuzhiyun /*
25*4882a593Smuzhiyun  * Prototype for this hypercall is:
26*4882a593Smuzhiyun  *  int physdev_op(int cmd, void *args)
27*4882a593Smuzhiyun  * @cmd	 == PHYSDEVOP_??? (physdev operation).
28*4882a593Smuzhiyun  * @args == Operation-specific extra arguments (NULL if none).
29*4882a593Smuzhiyun  */
30*4882a593Smuzhiyun 
31*4882a593Smuzhiyun /*
32*4882a593Smuzhiyun  * Notify end-of-interrupt (EOI) for the specified IRQ.
33*4882a593Smuzhiyun  * @arg == pointer to physdev_eoi structure.
34*4882a593Smuzhiyun  */
35*4882a593Smuzhiyun #define PHYSDEVOP_eoi			12
36*4882a593Smuzhiyun struct physdev_eoi {
37*4882a593Smuzhiyun 	/* IN */
38*4882a593Smuzhiyun 	uint32_t irq;
39*4882a593Smuzhiyun };
40*4882a593Smuzhiyun 
41*4882a593Smuzhiyun /*
42*4882a593Smuzhiyun  * Register a shared page for the hypervisor to indicate whether the guest
43*4882a593Smuzhiyun  * must issue PHYSDEVOP_eoi. The semantics of PHYSDEVOP_eoi change slightly
44*4882a593Smuzhiyun  * once the guest used this function in that the associated event channel
45*4882a593Smuzhiyun  * will automatically get unmasked. The page registered is used as a bit
46*4882a593Smuzhiyun  * array indexed by Xen's PIRQ value.
47*4882a593Smuzhiyun  */
48*4882a593Smuzhiyun #define PHYSDEVOP_pirq_eoi_gmfn_v1       17
49*4882a593Smuzhiyun /*
50*4882a593Smuzhiyun  * Register a shared page for the hypervisor to indicate whether the
51*4882a593Smuzhiyun  * guest must issue PHYSDEVOP_eoi. This hypercall is very similar to
52*4882a593Smuzhiyun  * PHYSDEVOP_pirq_eoi_gmfn_v1 but it doesn't change the semantics of
53*4882a593Smuzhiyun  * PHYSDEVOP_eoi. The page registered is used as a bit array indexed by
54*4882a593Smuzhiyun  * Xen's PIRQ value.
55*4882a593Smuzhiyun  */
56*4882a593Smuzhiyun #define PHYSDEVOP_pirq_eoi_gmfn_v2       28
57*4882a593Smuzhiyun struct physdev_pirq_eoi_gmfn {
58*4882a593Smuzhiyun     /* IN */
59*4882a593Smuzhiyun     xen_ulong_t gmfn;
60*4882a593Smuzhiyun };
61*4882a593Smuzhiyun 
62*4882a593Smuzhiyun /*
63*4882a593Smuzhiyun  * Query the status of an IRQ line.
64*4882a593Smuzhiyun  * @arg == pointer to physdev_irq_status_query structure.
65*4882a593Smuzhiyun  */
66*4882a593Smuzhiyun #define PHYSDEVOP_irq_status_query	 5
67*4882a593Smuzhiyun struct physdev_irq_status_query {
68*4882a593Smuzhiyun 	/* IN */
69*4882a593Smuzhiyun 	uint32_t irq;
70*4882a593Smuzhiyun 	/* OUT */
71*4882a593Smuzhiyun 	uint32_t flags; /* XENIRQSTAT_* */
72*4882a593Smuzhiyun };
73*4882a593Smuzhiyun 
74*4882a593Smuzhiyun /* Need to call PHYSDEVOP_eoi when the IRQ has been serviced? */
75*4882a593Smuzhiyun #define _XENIRQSTAT_needs_eoi	(0)
76*4882a593Smuzhiyun #define	 XENIRQSTAT_needs_eoi	(1U<<_XENIRQSTAT_needs_eoi)
77*4882a593Smuzhiyun 
78*4882a593Smuzhiyun /* IRQ shared by multiple guests? */
79*4882a593Smuzhiyun #define _XENIRQSTAT_shared	(1)
80*4882a593Smuzhiyun #define	 XENIRQSTAT_shared	(1U<<_XENIRQSTAT_shared)
81*4882a593Smuzhiyun 
82*4882a593Smuzhiyun /*
83*4882a593Smuzhiyun  * Set the current VCPU's I/O privilege level.
84*4882a593Smuzhiyun  * @arg == pointer to physdev_set_iopl structure.
85*4882a593Smuzhiyun  */
86*4882a593Smuzhiyun #define PHYSDEVOP_set_iopl		 6
87*4882a593Smuzhiyun struct physdev_set_iopl {
88*4882a593Smuzhiyun 	/* IN */
89*4882a593Smuzhiyun 	uint32_t iopl;
90*4882a593Smuzhiyun };
91*4882a593Smuzhiyun 
92*4882a593Smuzhiyun /*
93*4882a593Smuzhiyun  * Set the current VCPU's I/O-port permissions bitmap.
94*4882a593Smuzhiyun  * @arg == pointer to physdev_set_iobitmap structure.
95*4882a593Smuzhiyun  */
96*4882a593Smuzhiyun #define PHYSDEVOP_set_iobitmap		 7
97*4882a593Smuzhiyun struct physdev_set_iobitmap {
98*4882a593Smuzhiyun 	/* IN */
99*4882a593Smuzhiyun 	uint8_t * bitmap;
100*4882a593Smuzhiyun 	uint32_t nr_ports;
101*4882a593Smuzhiyun };
102*4882a593Smuzhiyun 
103*4882a593Smuzhiyun /*
104*4882a593Smuzhiyun  * Read or write an IO-APIC register.
105*4882a593Smuzhiyun  * @arg == pointer to physdev_apic structure.
106*4882a593Smuzhiyun  */
107*4882a593Smuzhiyun #define PHYSDEVOP_apic_read		 8
108*4882a593Smuzhiyun #define PHYSDEVOP_apic_write		 9
109*4882a593Smuzhiyun struct physdev_apic {
110*4882a593Smuzhiyun 	/* IN */
111*4882a593Smuzhiyun 	unsigned long apic_physbase;
112*4882a593Smuzhiyun 	uint32_t reg;
113*4882a593Smuzhiyun 	/* IN or OUT */
114*4882a593Smuzhiyun 	uint32_t value;
115*4882a593Smuzhiyun };
116*4882a593Smuzhiyun 
117*4882a593Smuzhiyun /*
118*4882a593Smuzhiyun  * Allocate or free a physical upcall vector for the specified IRQ line.
119*4882a593Smuzhiyun  * @arg == pointer to physdev_irq structure.
120*4882a593Smuzhiyun  */
121*4882a593Smuzhiyun #define PHYSDEVOP_alloc_irq_vector	10
122*4882a593Smuzhiyun #define PHYSDEVOP_free_irq_vector	11
123*4882a593Smuzhiyun struct physdev_irq {
124*4882a593Smuzhiyun 	/* IN */
125*4882a593Smuzhiyun 	uint32_t irq;
126*4882a593Smuzhiyun 	/* IN or OUT */
127*4882a593Smuzhiyun 	uint32_t vector;
128*4882a593Smuzhiyun };
129*4882a593Smuzhiyun 
130*4882a593Smuzhiyun #define MAP_PIRQ_TYPE_MSI		0x0
131*4882a593Smuzhiyun #define MAP_PIRQ_TYPE_GSI		0x1
132*4882a593Smuzhiyun #define MAP_PIRQ_TYPE_UNKNOWN		0x2
133*4882a593Smuzhiyun #define MAP_PIRQ_TYPE_MSI_SEG		0x3
134*4882a593Smuzhiyun #define MAP_PIRQ_TYPE_MULTI_MSI		0x4
135*4882a593Smuzhiyun 
136*4882a593Smuzhiyun #define PHYSDEVOP_map_pirq		13
137*4882a593Smuzhiyun struct physdev_map_pirq {
138*4882a593Smuzhiyun     domid_t domid;
139*4882a593Smuzhiyun     /* IN */
140*4882a593Smuzhiyun     int type;
141*4882a593Smuzhiyun     /* IN */
142*4882a593Smuzhiyun     int index;
143*4882a593Smuzhiyun     /* IN or OUT */
144*4882a593Smuzhiyun     int pirq;
145*4882a593Smuzhiyun     /* IN - high 16 bits hold segment for ..._MSI_SEG and ..._MULTI_MSI */
146*4882a593Smuzhiyun     int bus;
147*4882a593Smuzhiyun     /* IN */
148*4882a593Smuzhiyun     int devfn;
149*4882a593Smuzhiyun     /* IN
150*4882a593Smuzhiyun      * - For MSI-X contains entry number.
151*4882a593Smuzhiyun      * - For MSI with ..._MULTI_MSI contains number of vectors.
152*4882a593Smuzhiyun      * OUT (..._MULTI_MSI only)
153*4882a593Smuzhiyun      * - Number of vectors allocated.
154*4882a593Smuzhiyun      */
155*4882a593Smuzhiyun     int entry_nr;
156*4882a593Smuzhiyun     /* IN */
157*4882a593Smuzhiyun     uint64_t table_base;
158*4882a593Smuzhiyun };
159*4882a593Smuzhiyun 
160*4882a593Smuzhiyun #define PHYSDEVOP_unmap_pirq		14
161*4882a593Smuzhiyun struct physdev_unmap_pirq {
162*4882a593Smuzhiyun     domid_t domid;
163*4882a593Smuzhiyun     /* IN */
164*4882a593Smuzhiyun     int pirq;
165*4882a593Smuzhiyun };
166*4882a593Smuzhiyun 
167*4882a593Smuzhiyun #define PHYSDEVOP_manage_pci_add	15
168*4882a593Smuzhiyun #define PHYSDEVOP_manage_pci_remove	16
169*4882a593Smuzhiyun struct physdev_manage_pci {
170*4882a593Smuzhiyun 	/* IN */
171*4882a593Smuzhiyun 	uint8_t bus;
172*4882a593Smuzhiyun 	uint8_t devfn;
173*4882a593Smuzhiyun };
174*4882a593Smuzhiyun 
175*4882a593Smuzhiyun #define PHYSDEVOP_restore_msi            19
176*4882a593Smuzhiyun struct physdev_restore_msi {
177*4882a593Smuzhiyun 	/* IN */
178*4882a593Smuzhiyun 	uint8_t bus;
179*4882a593Smuzhiyun 	uint8_t devfn;
180*4882a593Smuzhiyun };
181*4882a593Smuzhiyun 
182*4882a593Smuzhiyun #define PHYSDEVOP_manage_pci_add_ext	20
183*4882a593Smuzhiyun struct physdev_manage_pci_ext {
184*4882a593Smuzhiyun 	/* IN */
185*4882a593Smuzhiyun 	uint8_t bus;
186*4882a593Smuzhiyun 	uint8_t devfn;
187*4882a593Smuzhiyun 	unsigned is_extfn;
188*4882a593Smuzhiyun 	unsigned is_virtfn;
189*4882a593Smuzhiyun 	struct {
190*4882a593Smuzhiyun 		uint8_t bus;
191*4882a593Smuzhiyun 		uint8_t devfn;
192*4882a593Smuzhiyun 	} physfn;
193*4882a593Smuzhiyun };
194*4882a593Smuzhiyun 
195*4882a593Smuzhiyun /*
196*4882a593Smuzhiyun  * Argument to physdev_op_compat() hypercall. Superceded by new physdev_op()
197*4882a593Smuzhiyun  * hypercall since 0x00030202.
198*4882a593Smuzhiyun  */
199*4882a593Smuzhiyun struct physdev_op {
200*4882a593Smuzhiyun 	uint32_t cmd;
201*4882a593Smuzhiyun 	union {
202*4882a593Smuzhiyun 		struct physdev_irq_status_query	     irq_status_query;
203*4882a593Smuzhiyun 		struct physdev_set_iopl		     set_iopl;
204*4882a593Smuzhiyun 		struct physdev_set_iobitmap	     set_iobitmap;
205*4882a593Smuzhiyun 		struct physdev_apic		     apic_op;
206*4882a593Smuzhiyun 		struct physdev_irq		     irq_op;
207*4882a593Smuzhiyun 	} u;
208*4882a593Smuzhiyun };
209*4882a593Smuzhiyun 
210*4882a593Smuzhiyun #define PHYSDEVOP_setup_gsi    21
211*4882a593Smuzhiyun struct physdev_setup_gsi {
212*4882a593Smuzhiyun     int gsi;
213*4882a593Smuzhiyun     /* IN */
214*4882a593Smuzhiyun     uint8_t triggering;
215*4882a593Smuzhiyun     /* IN */
216*4882a593Smuzhiyun     uint8_t polarity;
217*4882a593Smuzhiyun     /* IN */
218*4882a593Smuzhiyun };
219*4882a593Smuzhiyun 
220*4882a593Smuzhiyun #define PHYSDEVOP_get_nr_pirqs    22
221*4882a593Smuzhiyun struct physdev_nr_pirqs {
222*4882a593Smuzhiyun     /* OUT */
223*4882a593Smuzhiyun     uint32_t nr_pirqs;
224*4882a593Smuzhiyun };
225*4882a593Smuzhiyun 
226*4882a593Smuzhiyun /* type is MAP_PIRQ_TYPE_GSI or MAP_PIRQ_TYPE_MSI
227*4882a593Smuzhiyun  * the hypercall returns a free pirq */
228*4882a593Smuzhiyun #define PHYSDEVOP_get_free_pirq    23
229*4882a593Smuzhiyun struct physdev_get_free_pirq {
230*4882a593Smuzhiyun     /* IN */
231*4882a593Smuzhiyun     int type;
232*4882a593Smuzhiyun     /* OUT */
233*4882a593Smuzhiyun     uint32_t pirq;
234*4882a593Smuzhiyun };
235*4882a593Smuzhiyun 
236*4882a593Smuzhiyun #define XEN_PCI_DEV_EXTFN              0x1
237*4882a593Smuzhiyun #define XEN_PCI_DEV_VIRTFN             0x2
238*4882a593Smuzhiyun #define XEN_PCI_DEV_PXM                0x4
239*4882a593Smuzhiyun 
240*4882a593Smuzhiyun #define XEN_PCI_MMCFG_RESERVED         0x1
241*4882a593Smuzhiyun 
242*4882a593Smuzhiyun #define PHYSDEVOP_pci_mmcfg_reserved    24
243*4882a593Smuzhiyun struct physdev_pci_mmcfg_reserved {
244*4882a593Smuzhiyun     uint64_t address;
245*4882a593Smuzhiyun     uint16_t segment;
246*4882a593Smuzhiyun     uint8_t start_bus;
247*4882a593Smuzhiyun     uint8_t end_bus;
248*4882a593Smuzhiyun     uint32_t flags;
249*4882a593Smuzhiyun };
250*4882a593Smuzhiyun 
251*4882a593Smuzhiyun #define PHYSDEVOP_pci_device_add        25
252*4882a593Smuzhiyun struct physdev_pci_device_add {
253*4882a593Smuzhiyun     /* IN */
254*4882a593Smuzhiyun     uint16_t seg;
255*4882a593Smuzhiyun     uint8_t bus;
256*4882a593Smuzhiyun     uint8_t devfn;
257*4882a593Smuzhiyun     uint32_t flags;
258*4882a593Smuzhiyun     struct {
259*4882a593Smuzhiyun         uint8_t bus;
260*4882a593Smuzhiyun         uint8_t devfn;
261*4882a593Smuzhiyun     } physfn;
262*4882a593Smuzhiyun #if defined(__STDC_VERSION__) && __STDC_VERSION__ >= 199901L
263*4882a593Smuzhiyun     uint32_t optarr[];
264*4882a593Smuzhiyun #elif defined(__GNUC__)
265*4882a593Smuzhiyun     uint32_t optarr[0];
266*4882a593Smuzhiyun #endif
267*4882a593Smuzhiyun };
268*4882a593Smuzhiyun 
269*4882a593Smuzhiyun #define PHYSDEVOP_pci_device_remove     26
270*4882a593Smuzhiyun #define PHYSDEVOP_restore_msi_ext       27
271*4882a593Smuzhiyun /*
272*4882a593Smuzhiyun  * Dom0 should use these two to announce MMIO resources assigned to
273*4882a593Smuzhiyun  * MSI-X capable devices won't (prepare) or may (release) change.
274*4882a593Smuzhiyun  */
275*4882a593Smuzhiyun #define PHYSDEVOP_prepare_msix          30
276*4882a593Smuzhiyun #define PHYSDEVOP_release_msix          31
277*4882a593Smuzhiyun struct physdev_pci_device {
278*4882a593Smuzhiyun     /* IN */
279*4882a593Smuzhiyun     uint16_t seg;
280*4882a593Smuzhiyun     uint8_t bus;
281*4882a593Smuzhiyun     uint8_t devfn;
282*4882a593Smuzhiyun };
283*4882a593Smuzhiyun 
284*4882a593Smuzhiyun #define PHYSDEVOP_DBGP_RESET_PREPARE    1
285*4882a593Smuzhiyun #define PHYSDEVOP_DBGP_RESET_DONE       2
286*4882a593Smuzhiyun 
287*4882a593Smuzhiyun #define PHYSDEVOP_DBGP_BUS_UNKNOWN      0
288*4882a593Smuzhiyun #define PHYSDEVOP_DBGP_BUS_PCI          1
289*4882a593Smuzhiyun 
290*4882a593Smuzhiyun #define PHYSDEVOP_dbgp_op               29
291*4882a593Smuzhiyun struct physdev_dbgp_op {
292*4882a593Smuzhiyun     /* IN */
293*4882a593Smuzhiyun     uint8_t op;
294*4882a593Smuzhiyun     uint8_t bus;
295*4882a593Smuzhiyun     union {
296*4882a593Smuzhiyun         struct physdev_pci_device pci;
297*4882a593Smuzhiyun     } u;
298*4882a593Smuzhiyun };
299*4882a593Smuzhiyun 
300*4882a593Smuzhiyun /*
301*4882a593Smuzhiyun  * Notify that some PIRQ-bound event channels have been unmasked.
302*4882a593Smuzhiyun  * ** This command is obsolete since interface version 0x00030202 and is **
303*4882a593Smuzhiyun  * ** unsupported by newer versions of Xen.				 **
304*4882a593Smuzhiyun  */
305*4882a593Smuzhiyun #define PHYSDEVOP_IRQ_UNMASK_NOTIFY	 4
306*4882a593Smuzhiyun 
307*4882a593Smuzhiyun /*
308*4882a593Smuzhiyun  * These all-capitals physdev operation names are superceded by the new names
309*4882a593Smuzhiyun  * (defined above) since interface version 0x00030202.
310*4882a593Smuzhiyun  */
311*4882a593Smuzhiyun #define PHYSDEVOP_IRQ_STATUS_QUERY	 PHYSDEVOP_irq_status_query
312*4882a593Smuzhiyun #define PHYSDEVOP_SET_IOPL		 PHYSDEVOP_set_iopl
313*4882a593Smuzhiyun #define PHYSDEVOP_SET_IOBITMAP		 PHYSDEVOP_set_iobitmap
314*4882a593Smuzhiyun #define PHYSDEVOP_APIC_READ		 PHYSDEVOP_apic_read
315*4882a593Smuzhiyun #define PHYSDEVOP_APIC_WRITE		 PHYSDEVOP_apic_write
316*4882a593Smuzhiyun #define PHYSDEVOP_ASSIGN_VECTOR		 PHYSDEVOP_alloc_irq_vector
317*4882a593Smuzhiyun #define PHYSDEVOP_FREE_VECTOR		 PHYSDEVOP_free_irq_vector
318*4882a593Smuzhiyun #define PHYSDEVOP_IRQ_NEEDS_UNMASK_NOTIFY XENIRQSTAT_needs_eoi
319*4882a593Smuzhiyun #define PHYSDEVOP_IRQ_SHARED		 XENIRQSTAT_shared
320*4882a593Smuzhiyun 
321*4882a593Smuzhiyun #endif /* __XEN_PUBLIC_PHYSDEV_H__ */
322