1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * PCI Backend/Frontend Common Data Structures & Macros 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * Permission is hereby granted, free of charge, to any person obtaining a copy 5*4882a593Smuzhiyun * of this software and associated documentation files (the "Software"), to 6*4882a593Smuzhiyun * deal in the Software without restriction, including without limitation the 7*4882a593Smuzhiyun * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or 8*4882a593Smuzhiyun * sell copies of the Software, and to permit persons to whom the Software is 9*4882a593Smuzhiyun * furnished to do so, subject to the following conditions: 10*4882a593Smuzhiyun * 11*4882a593Smuzhiyun * The above copyright notice and this permission notice shall be included in 12*4882a593Smuzhiyun * all copies or substantial portions of the Software. 13*4882a593Smuzhiyun * 14*4882a593Smuzhiyun * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15*4882a593Smuzhiyun * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16*4882a593Smuzhiyun * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 17*4882a593Smuzhiyun * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 18*4882a593Smuzhiyun * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 19*4882a593Smuzhiyun * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 20*4882a593Smuzhiyun * DEALINGS IN THE SOFTWARE. 21*4882a593Smuzhiyun * 22*4882a593Smuzhiyun * Author: Ryan Wilson <hap9@epoch.ncsc.mil> 23*4882a593Smuzhiyun */ 24*4882a593Smuzhiyun #ifndef __XEN_PCI_COMMON_H__ 25*4882a593Smuzhiyun #define __XEN_PCI_COMMON_H__ 26*4882a593Smuzhiyun 27*4882a593Smuzhiyun /* Be sure to bump this number if you change this file */ 28*4882a593Smuzhiyun #define XEN_PCI_MAGIC "7" 29*4882a593Smuzhiyun 30*4882a593Smuzhiyun /* xen_pci_sharedinfo flags */ 31*4882a593Smuzhiyun #define _XEN_PCIF_active (0) 32*4882a593Smuzhiyun #define XEN_PCIF_active (1<<_XEN_PCIF_active) 33*4882a593Smuzhiyun #define _XEN_PCIB_AERHANDLER (1) 34*4882a593Smuzhiyun #define XEN_PCIB_AERHANDLER (1<<_XEN_PCIB_AERHANDLER) 35*4882a593Smuzhiyun #define _XEN_PCIB_active (2) 36*4882a593Smuzhiyun #define XEN_PCIB_active (1<<_XEN_PCIB_active) 37*4882a593Smuzhiyun 38*4882a593Smuzhiyun /* xen_pci_op commands */ 39*4882a593Smuzhiyun #define XEN_PCI_OP_conf_read (0) 40*4882a593Smuzhiyun #define XEN_PCI_OP_conf_write (1) 41*4882a593Smuzhiyun #define XEN_PCI_OP_enable_msi (2) 42*4882a593Smuzhiyun #define XEN_PCI_OP_disable_msi (3) 43*4882a593Smuzhiyun #define XEN_PCI_OP_enable_msix (4) 44*4882a593Smuzhiyun #define XEN_PCI_OP_disable_msix (5) 45*4882a593Smuzhiyun #define XEN_PCI_OP_aer_detected (6) 46*4882a593Smuzhiyun #define XEN_PCI_OP_aer_resume (7) 47*4882a593Smuzhiyun #define XEN_PCI_OP_aer_mmio (8) 48*4882a593Smuzhiyun #define XEN_PCI_OP_aer_slotreset (9) 49*4882a593Smuzhiyun 50*4882a593Smuzhiyun /* xen_pci_op error numbers */ 51*4882a593Smuzhiyun #define XEN_PCI_ERR_success (0) 52*4882a593Smuzhiyun #define XEN_PCI_ERR_dev_not_found (-1) 53*4882a593Smuzhiyun #define XEN_PCI_ERR_invalid_offset (-2) 54*4882a593Smuzhiyun #define XEN_PCI_ERR_access_denied (-3) 55*4882a593Smuzhiyun #define XEN_PCI_ERR_not_implemented (-4) 56*4882a593Smuzhiyun /* XEN_PCI_ERR_op_failed - backend failed to complete the operation */ 57*4882a593Smuzhiyun #define XEN_PCI_ERR_op_failed (-5) 58*4882a593Smuzhiyun 59*4882a593Smuzhiyun /* 60*4882a593Smuzhiyun * it should be PAGE_SIZE-sizeof(struct xen_pci_op))/sizeof(struct msix_entry)) 61*4882a593Smuzhiyun * Should not exceed 128 62*4882a593Smuzhiyun */ 63*4882a593Smuzhiyun #define SH_INFO_MAX_VEC 128 64*4882a593Smuzhiyun 65*4882a593Smuzhiyun struct xen_msix_entry { 66*4882a593Smuzhiyun uint16_t vector; 67*4882a593Smuzhiyun uint16_t entry; 68*4882a593Smuzhiyun }; 69*4882a593Smuzhiyun struct xen_pci_op { 70*4882a593Smuzhiyun /* IN: what action to perform: XEN_PCI_OP_* */ 71*4882a593Smuzhiyun uint32_t cmd; 72*4882a593Smuzhiyun 73*4882a593Smuzhiyun /* OUT: will contain an error number (if any) from errno.h */ 74*4882a593Smuzhiyun int32_t err; 75*4882a593Smuzhiyun 76*4882a593Smuzhiyun /* IN: which device to touch */ 77*4882a593Smuzhiyun uint32_t domain; /* PCI Domain/Segment */ 78*4882a593Smuzhiyun uint32_t bus; 79*4882a593Smuzhiyun uint32_t devfn; 80*4882a593Smuzhiyun 81*4882a593Smuzhiyun /* IN: which configuration registers to touch */ 82*4882a593Smuzhiyun int32_t offset; 83*4882a593Smuzhiyun int32_t size; 84*4882a593Smuzhiyun 85*4882a593Smuzhiyun /* IN/OUT: Contains the result after a READ or the value to WRITE */ 86*4882a593Smuzhiyun uint32_t value; 87*4882a593Smuzhiyun /* IN: Contains extra infor for this operation */ 88*4882a593Smuzhiyun uint32_t info; 89*4882a593Smuzhiyun /*IN: param for msi-x */ 90*4882a593Smuzhiyun struct xen_msix_entry msix_entries[SH_INFO_MAX_VEC]; 91*4882a593Smuzhiyun }; 92*4882a593Smuzhiyun 93*4882a593Smuzhiyun /*used for pcie aer handling*/ 94*4882a593Smuzhiyun struct xen_pcie_aer_op { 95*4882a593Smuzhiyun /* IN: what action to perform: XEN_PCI_OP_* */ 96*4882a593Smuzhiyun uint32_t cmd; 97*4882a593Smuzhiyun /*IN/OUT: return aer_op result or carry error_detected state as input*/ 98*4882a593Smuzhiyun int32_t err; 99*4882a593Smuzhiyun 100*4882a593Smuzhiyun /* IN: which device to touch */ 101*4882a593Smuzhiyun uint32_t domain; /* PCI Domain/Segment*/ 102*4882a593Smuzhiyun uint32_t bus; 103*4882a593Smuzhiyun uint32_t devfn; 104*4882a593Smuzhiyun }; 105*4882a593Smuzhiyun struct xen_pci_sharedinfo { 106*4882a593Smuzhiyun /* flags - XEN_PCIF_* */ 107*4882a593Smuzhiyun uint32_t flags; 108*4882a593Smuzhiyun struct xen_pci_op op; 109*4882a593Smuzhiyun struct xen_pcie_aer_op aer_op; 110*4882a593Smuzhiyun }; 111*4882a593Smuzhiyun 112*4882a593Smuzhiyun #endif /* __XEN_PCI_COMMON_H__ */ 113