1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * Permission is hereby granted, free of charge, to any person obtaining a copy 3*4882a593Smuzhiyun * of this software and associated documentation files (the "Software"), to 4*4882a593Smuzhiyun * deal in the Software without restriction, including without limitation the 5*4882a593Smuzhiyun * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or 6*4882a593Smuzhiyun * sell copies of the Software, and to permit persons to whom the Software is 7*4882a593Smuzhiyun * furnished to do so, subject to the following conditions: 8*4882a593Smuzhiyun * 9*4882a593Smuzhiyun * The above copyright notice and this permission notice shall be included in 10*4882a593Smuzhiyun * all copies or substantial portions of the Software. 11*4882a593Smuzhiyun * 12*4882a593Smuzhiyun * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 13*4882a593Smuzhiyun * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 14*4882a593Smuzhiyun * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 15*4882a593Smuzhiyun * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 16*4882a593Smuzhiyun * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 17*4882a593Smuzhiyun * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 18*4882a593Smuzhiyun * DEALINGS IN THE SOFTWARE. 19*4882a593Smuzhiyun */ 20*4882a593Smuzhiyun 21*4882a593Smuzhiyun #ifndef __XEN_PUBLIC_HVM_PARAMS_H__ 22*4882a593Smuzhiyun #define __XEN_PUBLIC_HVM_PARAMS_H__ 23*4882a593Smuzhiyun 24*4882a593Smuzhiyun #include <xen/interface/hvm/hvm_op.h> 25*4882a593Smuzhiyun 26*4882a593Smuzhiyun /* 27*4882a593Smuzhiyun * Parameter space for HVMOP_{set,get}_param. 28*4882a593Smuzhiyun */ 29*4882a593Smuzhiyun 30*4882a593Smuzhiyun #define HVM_PARAM_CALLBACK_IRQ 0 31*4882a593Smuzhiyun /* 32*4882a593Smuzhiyun * How should CPU0 event-channel notifications be delivered? 33*4882a593Smuzhiyun * 34*4882a593Smuzhiyun * If val == 0 then CPU0 event-channel notifications are not delivered. 35*4882a593Smuzhiyun * If val != 0, val[63:56] encodes the type, as follows: 36*4882a593Smuzhiyun */ 37*4882a593Smuzhiyun 38*4882a593Smuzhiyun #define HVM_PARAM_CALLBACK_TYPE_GSI 0 39*4882a593Smuzhiyun /* 40*4882a593Smuzhiyun * val[55:0] is a delivery GSI. GSI 0 cannot be used, as it aliases val == 0, 41*4882a593Smuzhiyun * and disables all notifications. 42*4882a593Smuzhiyun */ 43*4882a593Smuzhiyun 44*4882a593Smuzhiyun #define HVM_PARAM_CALLBACK_TYPE_PCI_INTX 1 45*4882a593Smuzhiyun /* 46*4882a593Smuzhiyun * val[55:0] is a delivery PCI INTx line: 47*4882a593Smuzhiyun * Domain = val[47:32], Bus = val[31:16] DevFn = val[15:8], IntX = val[1:0] 48*4882a593Smuzhiyun */ 49*4882a593Smuzhiyun 50*4882a593Smuzhiyun #if defined(__i386__) || defined(__x86_64__) 51*4882a593Smuzhiyun #define HVM_PARAM_CALLBACK_TYPE_VECTOR 2 52*4882a593Smuzhiyun /* 53*4882a593Smuzhiyun * val[7:0] is a vector number. Check for XENFEAT_hvm_callback_vector to know 54*4882a593Smuzhiyun * if this delivery method is available. 55*4882a593Smuzhiyun */ 56*4882a593Smuzhiyun #elif defined(__arm__) || defined(__aarch64__) 57*4882a593Smuzhiyun #define HVM_PARAM_CALLBACK_TYPE_PPI 2 58*4882a593Smuzhiyun /* 59*4882a593Smuzhiyun * val[55:16] needs to be zero. 60*4882a593Smuzhiyun * val[15:8] is interrupt flag of the PPI used by event-channel: 61*4882a593Smuzhiyun * bit 8: the PPI is edge(1) or level(0) triggered 62*4882a593Smuzhiyun * bit 9: the PPI is active low(1) or high(0) 63*4882a593Smuzhiyun * val[7:0] is a PPI number used by event-channel. 64*4882a593Smuzhiyun * This is only used by ARM/ARM64 and masking/eoi the interrupt associated to 65*4882a593Smuzhiyun * the notification is handled by the interrupt controller. 66*4882a593Smuzhiyun */ 67*4882a593Smuzhiyun #endif 68*4882a593Smuzhiyun 69*4882a593Smuzhiyun #define HVM_PARAM_STORE_PFN 1 70*4882a593Smuzhiyun #define HVM_PARAM_STORE_EVTCHN 2 71*4882a593Smuzhiyun 72*4882a593Smuzhiyun #define HVM_PARAM_PAE_ENABLED 4 73*4882a593Smuzhiyun 74*4882a593Smuzhiyun #define HVM_PARAM_IOREQ_PFN 5 75*4882a593Smuzhiyun 76*4882a593Smuzhiyun #define HVM_PARAM_BUFIOREQ_PFN 6 77*4882a593Smuzhiyun 78*4882a593Smuzhiyun /* 79*4882a593Smuzhiyun * Set mode for virtual timers (currently x86 only): 80*4882a593Smuzhiyun * delay_for_missed_ticks (default): 81*4882a593Smuzhiyun * Do not advance a vcpu's time beyond the correct delivery time for 82*4882a593Smuzhiyun * interrupts that have been missed due to preemption. Deliver missed 83*4882a593Smuzhiyun * interrupts when the vcpu is rescheduled and advance the vcpu's virtual 84*4882a593Smuzhiyun * time stepwise for each one. 85*4882a593Smuzhiyun * no_delay_for_missed_ticks: 86*4882a593Smuzhiyun * As above, missed interrupts are delivered, but guest time always tracks 87*4882a593Smuzhiyun * wallclock (i.e., real) time while doing so. 88*4882a593Smuzhiyun * no_missed_ticks_pending: 89*4882a593Smuzhiyun * No missed interrupts are held pending. Instead, to ensure ticks are 90*4882a593Smuzhiyun * delivered at some non-zero rate, if we detect missed ticks then the 91*4882a593Smuzhiyun * internal tick alarm is not disabled if the VCPU is preempted during the 92*4882a593Smuzhiyun * next tick period. 93*4882a593Smuzhiyun * one_missed_tick_pending: 94*4882a593Smuzhiyun * Missed interrupts are collapsed together and delivered as one 'late tick'. 95*4882a593Smuzhiyun * Guest time always tracks wallclock (i.e., real) time. 96*4882a593Smuzhiyun */ 97*4882a593Smuzhiyun #define HVM_PARAM_TIMER_MODE 10 98*4882a593Smuzhiyun #define HVMPTM_delay_for_missed_ticks 0 99*4882a593Smuzhiyun #define HVMPTM_no_delay_for_missed_ticks 1 100*4882a593Smuzhiyun #define HVMPTM_no_missed_ticks_pending 2 101*4882a593Smuzhiyun #define HVMPTM_one_missed_tick_pending 3 102*4882a593Smuzhiyun 103*4882a593Smuzhiyun /* Boolean: Enable virtual HPET (high-precision event timer)? (x86-only) */ 104*4882a593Smuzhiyun #define HVM_PARAM_HPET_ENABLED 11 105*4882a593Smuzhiyun 106*4882a593Smuzhiyun /* Identity-map page directory used by Intel EPT when CR0.PG=0. */ 107*4882a593Smuzhiyun #define HVM_PARAM_IDENT_PT 12 108*4882a593Smuzhiyun 109*4882a593Smuzhiyun /* Device Model domain, defaults to 0. */ 110*4882a593Smuzhiyun #define HVM_PARAM_DM_DOMAIN 13 111*4882a593Smuzhiyun 112*4882a593Smuzhiyun /* ACPI S state: currently support S0 and S3 on x86. */ 113*4882a593Smuzhiyun #define HVM_PARAM_ACPI_S_STATE 14 114*4882a593Smuzhiyun 115*4882a593Smuzhiyun /* TSS used on Intel when CR0.PE=0. */ 116*4882a593Smuzhiyun #define HVM_PARAM_VM86_TSS 15 117*4882a593Smuzhiyun 118*4882a593Smuzhiyun /* Boolean: Enable aligning all periodic vpts to reduce interrupts */ 119*4882a593Smuzhiyun #define HVM_PARAM_VPT_ALIGN 16 120*4882a593Smuzhiyun 121*4882a593Smuzhiyun /* Console debug shared memory ring and event channel */ 122*4882a593Smuzhiyun #define HVM_PARAM_CONSOLE_PFN 17 123*4882a593Smuzhiyun #define HVM_PARAM_CONSOLE_EVTCHN 18 124*4882a593Smuzhiyun 125*4882a593Smuzhiyun #define HVM_NR_PARAMS 19 126*4882a593Smuzhiyun 127*4882a593Smuzhiyun #endif /* __XEN_PUBLIC_HVM_PARAMS_H__ */ 128