xref: /OK3568_Linux_fs/kernel/include/video/w100fb.h (revision 4882a59341e53eb6f0b4789bf948001014eff981) 
1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-only */
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun  *  Support for the w100 frame buffer.
4*4882a593Smuzhiyun  *
5*4882a593Smuzhiyun  *  Copyright (c) 2004-2005 Richard Purdie
6*4882a593Smuzhiyun  *  Copyright (c) 2005 Ian Molton
7*4882a593Smuzhiyun  */
8*4882a593Smuzhiyun 
9*4882a593Smuzhiyun #define W100_GPIO_PORT_A	0
10*4882a593Smuzhiyun #define W100_GPIO_PORT_B	1
11*4882a593Smuzhiyun 
12*4882a593Smuzhiyun #define CLK_SRC_XTAL  0
13*4882a593Smuzhiyun #define CLK_SRC_PLL   1
14*4882a593Smuzhiyun 
15*4882a593Smuzhiyun struct w100fb_par;
16*4882a593Smuzhiyun 
17*4882a593Smuzhiyun unsigned long w100fb_gpio_read(int port);
18*4882a593Smuzhiyun void w100fb_gpio_write(int port, unsigned long value);
19*4882a593Smuzhiyun unsigned long w100fb_get_hsynclen(struct device *dev);
20*4882a593Smuzhiyun 
21*4882a593Smuzhiyun /* LCD Specific Routines and Config */
22*4882a593Smuzhiyun struct w100_tg_info {
23*4882a593Smuzhiyun 	void (*change)(struct w100fb_par*);
24*4882a593Smuzhiyun 	void (*suspend)(struct w100fb_par*);
25*4882a593Smuzhiyun 	void (*resume)(struct w100fb_par*);
26*4882a593Smuzhiyun };
27*4882a593Smuzhiyun 
28*4882a593Smuzhiyun /* General Platform Specific w100 Register Values */
29*4882a593Smuzhiyun struct w100_gen_regs {
30*4882a593Smuzhiyun 	unsigned long lcd_format;
31*4882a593Smuzhiyun 	unsigned long lcdd_cntl1;
32*4882a593Smuzhiyun 	unsigned long lcdd_cntl2;
33*4882a593Smuzhiyun 	unsigned long genlcd_cntl1;
34*4882a593Smuzhiyun 	unsigned long genlcd_cntl2;
35*4882a593Smuzhiyun 	unsigned long genlcd_cntl3;
36*4882a593Smuzhiyun };
37*4882a593Smuzhiyun 
38*4882a593Smuzhiyun struct w100_gpio_regs {
39*4882a593Smuzhiyun 	unsigned long init_data1;
40*4882a593Smuzhiyun 	unsigned long init_data2;
41*4882a593Smuzhiyun 	unsigned long gpio_dir1;
42*4882a593Smuzhiyun 	unsigned long gpio_oe1;
43*4882a593Smuzhiyun 	unsigned long gpio_dir2;
44*4882a593Smuzhiyun 	unsigned long gpio_oe2;
45*4882a593Smuzhiyun };
46*4882a593Smuzhiyun 
47*4882a593Smuzhiyun /* Optional External Memory Configuration */
48*4882a593Smuzhiyun struct w100_mem_info {
49*4882a593Smuzhiyun 	unsigned long ext_cntl;
50*4882a593Smuzhiyun 	unsigned long sdram_mode_reg;
51*4882a593Smuzhiyun 	unsigned long ext_timing_cntl;
52*4882a593Smuzhiyun 	unsigned long io_cntl;
53*4882a593Smuzhiyun 	unsigned int size;
54*4882a593Smuzhiyun };
55*4882a593Smuzhiyun 
56*4882a593Smuzhiyun struct w100_bm_mem_info {
57*4882a593Smuzhiyun 	unsigned long ext_mem_bw;
58*4882a593Smuzhiyun 	unsigned long offset;
59*4882a593Smuzhiyun 	unsigned long ext_timing_ctl;
60*4882a593Smuzhiyun 	unsigned long ext_cntl;
61*4882a593Smuzhiyun 	unsigned long mode_reg;
62*4882a593Smuzhiyun 	unsigned long io_cntl;
63*4882a593Smuzhiyun 	unsigned long config;
64*4882a593Smuzhiyun };
65*4882a593Smuzhiyun 
66*4882a593Smuzhiyun /* LCD Mode definition */
67*4882a593Smuzhiyun struct w100_mode {
68*4882a593Smuzhiyun 	unsigned int xres;
69*4882a593Smuzhiyun 	unsigned int yres;
70*4882a593Smuzhiyun 	unsigned short left_margin;
71*4882a593Smuzhiyun 	unsigned short right_margin;
72*4882a593Smuzhiyun 	unsigned short upper_margin;
73*4882a593Smuzhiyun 	unsigned short lower_margin;
74*4882a593Smuzhiyun 	unsigned long crtc_ss;
75*4882a593Smuzhiyun 	unsigned long crtc_ls;
76*4882a593Smuzhiyun 	unsigned long crtc_gs;
77*4882a593Smuzhiyun 	unsigned long crtc_vpos_gs;
78*4882a593Smuzhiyun 	unsigned long crtc_rev;
79*4882a593Smuzhiyun 	unsigned long crtc_dclk;
80*4882a593Smuzhiyun 	unsigned long crtc_gclk;
81*4882a593Smuzhiyun 	unsigned long crtc_goe;
82*4882a593Smuzhiyun 	unsigned long crtc_ps1_active;
83*4882a593Smuzhiyun 	char pll_freq;
84*4882a593Smuzhiyun 	char fast_pll_freq;
85*4882a593Smuzhiyun 	int sysclk_src;
86*4882a593Smuzhiyun 	int sysclk_divider;
87*4882a593Smuzhiyun 	int pixclk_src;
88*4882a593Smuzhiyun 	int pixclk_divider;
89*4882a593Smuzhiyun 	int pixclk_divider_rotated;
90*4882a593Smuzhiyun };
91*4882a593Smuzhiyun 
92*4882a593Smuzhiyun struct w100_pll_info {
93*4882a593Smuzhiyun 	uint16_t freq;  /* desired Fout for PLL (Mhz) */
94*4882a593Smuzhiyun 	uint8_t M;      /* input divider */
95*4882a593Smuzhiyun 	uint8_t N_int;  /* VCO multiplier */
96*4882a593Smuzhiyun 	uint8_t N_fac;  /* VCO multiplier fractional part */
97*4882a593Smuzhiyun 	uint8_t tfgoal;
98*4882a593Smuzhiyun 	uint8_t lock_time;
99*4882a593Smuzhiyun };
100*4882a593Smuzhiyun 
101*4882a593Smuzhiyun /* Initial Video mode orientation flags */
102*4882a593Smuzhiyun #define INIT_MODE_ROTATED  0x1
103*4882a593Smuzhiyun #define INIT_MODE_FLIPPED  0x2
104*4882a593Smuzhiyun 
105*4882a593Smuzhiyun /*
106*4882a593Smuzhiyun  * This structure describes the machine which we are running on.
107*4882a593Smuzhiyun  * It is set by machine specific code and used in the probe routine
108*4882a593Smuzhiyun  * of drivers/video/w100fb.c
109*4882a593Smuzhiyun  */
110*4882a593Smuzhiyun struct w100fb_mach_info {
111*4882a593Smuzhiyun 	/* General Platform Specific Registers */
112*4882a593Smuzhiyun 	struct w100_gen_regs *regs;
113*4882a593Smuzhiyun 	/* Table of modes the LCD is capable of */
114*4882a593Smuzhiyun 	struct w100_mode *modelist;
115*4882a593Smuzhiyun 	unsigned int num_modes;
116*4882a593Smuzhiyun 	/* Hooks for any platform specific tg/lcd code (optional) */
117*4882a593Smuzhiyun 	struct w100_tg_info *tg;
118*4882a593Smuzhiyun 	/* External memory definition (if present) */
119*4882a593Smuzhiyun 	struct w100_mem_info *mem;
120*4882a593Smuzhiyun 	/* Additional External memory definition (if present) */
121*4882a593Smuzhiyun 	struct w100_bm_mem_info *bm_mem;
122*4882a593Smuzhiyun 	/* GPIO definitions (optional) */
123*4882a593Smuzhiyun 	struct w100_gpio_regs *gpio;
124*4882a593Smuzhiyun 	/* Initial Mode flags */
125*4882a593Smuzhiyun 	unsigned int init_mode;
126*4882a593Smuzhiyun 	/* Xtal Frequency */
127*4882a593Smuzhiyun 	unsigned int xtal_freq;
128*4882a593Smuzhiyun 	/* Enable Xtal input doubler (1 == enable) */
129*4882a593Smuzhiyun 	unsigned int xtal_dbl;
130*4882a593Smuzhiyun };
131*4882a593Smuzhiyun 
132*4882a593Smuzhiyun /* General frame buffer data structure */
133*4882a593Smuzhiyun struct w100fb_par {
134*4882a593Smuzhiyun 	unsigned int chip_id;
135*4882a593Smuzhiyun 	unsigned int xres;
136*4882a593Smuzhiyun 	unsigned int yres;
137*4882a593Smuzhiyun 	unsigned int extmem_active;
138*4882a593Smuzhiyun 	unsigned int flip;
139*4882a593Smuzhiyun 	unsigned int blanked;
140*4882a593Smuzhiyun 	unsigned int fastpll_mode;
141*4882a593Smuzhiyun 	unsigned long hsync_len;
142*4882a593Smuzhiyun 	struct w100_mode *mode;
143*4882a593Smuzhiyun 	struct w100_pll_info *pll_table;
144*4882a593Smuzhiyun 	struct w100fb_mach_info *mach;
145*4882a593Smuzhiyun 	uint32_t *saved_intmem;
146*4882a593Smuzhiyun 	uint32_t *saved_extmem;
147*4882a593Smuzhiyun };
148