1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */ 2*4882a593Smuzhiyun 3*4882a593Smuzhiyun #ifndef TRIDENTFB_DEBUG 4*4882a593Smuzhiyun #define TRIDENTFB_DEBUG 0 5*4882a593Smuzhiyun #endif 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun #if TRIDENTFB_DEBUG 8*4882a593Smuzhiyun #define debug(f, a...) printk("%s:" f, __func__ , ## a); 9*4882a593Smuzhiyun #else 10*4882a593Smuzhiyun #define debug(f, a...) 11*4882a593Smuzhiyun #endif 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun #define output(f, a...) pr_info("tridentfb: " f, ## a) 14*4882a593Smuzhiyun 15*4882a593Smuzhiyun #define Kb (1024) 16*4882a593Smuzhiyun #define Mb (Kb*Kb) 17*4882a593Smuzhiyun 18*4882a593Smuzhiyun /* PCI IDS of supported cards temporarily here */ 19*4882a593Smuzhiyun 20*4882a593Smuzhiyun #define CYBER9320 0x9320 21*4882a593Smuzhiyun #define CYBER9388 0x9388 22*4882a593Smuzhiyun #define CYBER9382 0x9382 /* the real PCI id for this is 9660 */ 23*4882a593Smuzhiyun #define CYBER9385 0x9385 /* ditto */ 24*4882a593Smuzhiyun #define CYBER9397 0x9397 25*4882a593Smuzhiyun #define CYBER9397DVD 0x939A 26*4882a593Smuzhiyun #define CYBER9520 0x9520 27*4882a593Smuzhiyun #define CYBER9525DVD 0x9525 28*4882a593Smuzhiyun #define TGUI9440 0x9440 29*4882a593Smuzhiyun #define TGUI9660 0x9660 30*4882a593Smuzhiyun #define PROVIDIA9685 0x9685 31*4882a593Smuzhiyun #define IMAGE975 0x9750 32*4882a593Smuzhiyun #define IMAGE985 0x9850 33*4882a593Smuzhiyun #define BLADE3D 0x9880 34*4882a593Smuzhiyun #define CYBERBLADEE4 0x9540 35*4882a593Smuzhiyun #define CYBERBLADEi7 0x8400 36*4882a593Smuzhiyun #define CYBERBLADEi7D 0x8420 37*4882a593Smuzhiyun #define CYBERBLADEi1 0x8500 38*4882a593Smuzhiyun #define CYBERBLADEi1D 0x8520 39*4882a593Smuzhiyun #define CYBERBLADEAi1 0x8600 40*4882a593Smuzhiyun #define CYBERBLADEAi1D 0x8620 41*4882a593Smuzhiyun #define CYBERBLADEXPAi1 0x8820 42*4882a593Smuzhiyun #define CYBERBLADEXPm8 0x9910 43*4882a593Smuzhiyun #define CYBERBLADEXPm16 0x9930 44*4882a593Smuzhiyun 45*4882a593Smuzhiyun /* these defines are for 'lcd' variable */ 46*4882a593Smuzhiyun #define LCD_STRETCH 0 47*4882a593Smuzhiyun #define LCD_CENTER 1 48*4882a593Smuzhiyun #define LCD_BIOS 2 49*4882a593Smuzhiyun 50*4882a593Smuzhiyun /* General Registers */ 51*4882a593Smuzhiyun #define SPR 0x1F /* Software Programming Register (videoram) */ 52*4882a593Smuzhiyun 53*4882a593Smuzhiyun /* 3C4 */ 54*4882a593Smuzhiyun #define RevisionID 0x09 55*4882a593Smuzhiyun #define OldOrNew 0x0B 56*4882a593Smuzhiyun #define ConfPort1 0x0C 57*4882a593Smuzhiyun #define ConfPort2 0x0C 58*4882a593Smuzhiyun #define NewMode2 0x0D 59*4882a593Smuzhiyun #define NewMode1 0x0E 60*4882a593Smuzhiyun #define Protection 0x11 61*4882a593Smuzhiyun #define MCLKLow 0x16 62*4882a593Smuzhiyun #define MCLKHigh 0x17 63*4882a593Smuzhiyun #define ClockLow 0x18 64*4882a593Smuzhiyun #define ClockHigh 0x19 65*4882a593Smuzhiyun #define SSetup 0x20 66*4882a593Smuzhiyun #define SKey 0x37 67*4882a593Smuzhiyun #define SPKey 0x57 68*4882a593Smuzhiyun 69*4882a593Smuzhiyun /* 3x4 */ 70*4882a593Smuzhiyun #define CRTCModuleTest 0x1E 71*4882a593Smuzhiyun #define FIFOControl 0x20 72*4882a593Smuzhiyun #define LinearAddReg 0x21 73*4882a593Smuzhiyun #define DRAMTiming 0x23 74*4882a593Smuzhiyun #define New32 0x23 75*4882a593Smuzhiyun #define RAMDACTiming 0x25 76*4882a593Smuzhiyun #define CRTHiOrd 0x27 77*4882a593Smuzhiyun #define AddColReg 0x29 78*4882a593Smuzhiyun #define InterfaceSel 0x2A 79*4882a593Smuzhiyun #define HorizOverflow 0x2B 80*4882a593Smuzhiyun #define GETest 0x2D 81*4882a593Smuzhiyun #define Performance 0x2F 82*4882a593Smuzhiyun #define GraphEngReg 0x36 83*4882a593Smuzhiyun #define I2C 0x37 84*4882a593Smuzhiyun #define PixelBusReg 0x38 85*4882a593Smuzhiyun #define PCIReg 0x39 86*4882a593Smuzhiyun #define DRAMControl 0x3A 87*4882a593Smuzhiyun #define MiscContReg 0x3C 88*4882a593Smuzhiyun #define CursorXLow 0x40 89*4882a593Smuzhiyun #define CursorXHigh 0x41 90*4882a593Smuzhiyun #define CursorYLow 0x42 91*4882a593Smuzhiyun #define CursorYHigh 0x43 92*4882a593Smuzhiyun #define CursorLocLow 0x44 93*4882a593Smuzhiyun #define CursorLocHigh 0x45 94*4882a593Smuzhiyun #define CursorXOffset 0x46 95*4882a593Smuzhiyun #define CursorYOffset 0x47 96*4882a593Smuzhiyun #define CursorFG1 0x48 97*4882a593Smuzhiyun #define CursorFG2 0x49 98*4882a593Smuzhiyun #define CursorFG3 0x4A 99*4882a593Smuzhiyun #define CursorFG4 0x4B 100*4882a593Smuzhiyun #define CursorBG1 0x4C 101*4882a593Smuzhiyun #define CursorBG2 0x4D 102*4882a593Smuzhiyun #define CursorBG3 0x4E 103*4882a593Smuzhiyun #define CursorBG4 0x4F 104*4882a593Smuzhiyun #define CursorControl 0x50 105*4882a593Smuzhiyun #define PCIRetry 0x55 106*4882a593Smuzhiyun #define PreEndControl 0x56 107*4882a593Smuzhiyun #define PreEndFetch 0x57 108*4882a593Smuzhiyun #define PCIMaster 0x60 109*4882a593Smuzhiyun #define Enhancement0 0x62 110*4882a593Smuzhiyun #define NewEDO 0x64 111*4882a593Smuzhiyun #define TVinterface 0xC0 112*4882a593Smuzhiyun #define TVMode 0xC1 113*4882a593Smuzhiyun #define ClockControl 0xCF 114*4882a593Smuzhiyun 115*4882a593Smuzhiyun 116*4882a593Smuzhiyun /* 3CE */ 117*4882a593Smuzhiyun #define MiscExtFunc 0x0F 118*4882a593Smuzhiyun #define PowerStatus 0x23 119*4882a593Smuzhiyun #define MiscIntContReg 0x2F 120*4882a593Smuzhiyun #define CyberControl 0x30 121*4882a593Smuzhiyun #define CyberEnhance 0x31 122*4882a593Smuzhiyun #define FPConfig 0x33 123*4882a593Smuzhiyun #define VertStretch 0x52 124*4882a593Smuzhiyun #define HorStretch 0x53 125*4882a593Smuzhiyun #define BiosMode 0x5c 126*4882a593Smuzhiyun #define BiosReg 0x5d 127*4882a593Smuzhiyun 128*4882a593Smuzhiyun /* Graphics Engine */ 129*4882a593Smuzhiyun #define STATUS 0x2120 130*4882a593Smuzhiyun #define OLDCMD 0x2124 131*4882a593Smuzhiyun #define DRAWFL 0x2128 132*4882a593Smuzhiyun #define OLDCLR 0x212C 133*4882a593Smuzhiyun #define OLDDST 0x2138 134*4882a593Smuzhiyun #define OLDSRC 0x213C 135*4882a593Smuzhiyun #define OLDDIM 0x2140 136*4882a593Smuzhiyun #define CMD 0x2144 137*4882a593Smuzhiyun #define ROP 0x2148 138*4882a593Smuzhiyun #define COLOR 0x2160 139*4882a593Smuzhiyun #define BGCOLOR 0x2164 140*4882a593Smuzhiyun #define SRC1 0x2100 141*4882a593Smuzhiyun #define SRC2 0x2104 142*4882a593Smuzhiyun #define DST1 0x2108 143*4882a593Smuzhiyun #define DST2 0x210C 144*4882a593Smuzhiyun 145*4882a593Smuzhiyun #define ROP_S 0xCC 146*4882a593Smuzhiyun #define ROP_P 0xF0 147*4882a593Smuzhiyun #define ROP_X 0x66 148