1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */ 2*4882a593Smuzhiyun #ifndef __ASM_SH_MOBILE_LCDC_H__ 3*4882a593Smuzhiyun #define __ASM_SH_MOBILE_LCDC_H__ 4*4882a593Smuzhiyun 5*4882a593Smuzhiyun #include <linux/fb.h> 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun /* Register definitions */ 8*4882a593Smuzhiyun #define _LDDCKR 0x410 9*4882a593Smuzhiyun #define LDDCKR_ICKSEL_BUS (0 << 16) 10*4882a593Smuzhiyun #define LDDCKR_ICKSEL_MIPI (1 << 16) 11*4882a593Smuzhiyun #define LDDCKR_ICKSEL_HDMI (2 << 16) 12*4882a593Smuzhiyun #define LDDCKR_ICKSEL_EXT (3 << 16) 13*4882a593Smuzhiyun #define LDDCKR_ICKSEL_MASK (7 << 16) 14*4882a593Smuzhiyun #define LDDCKR_MOSEL (1 << 6) 15*4882a593Smuzhiyun #define _LDDCKSTPR 0x414 16*4882a593Smuzhiyun #define _LDINTR 0x468 17*4882a593Smuzhiyun #define LDINTR_FE (1 << 10) 18*4882a593Smuzhiyun #define LDINTR_VSE (1 << 9) 19*4882a593Smuzhiyun #define LDINTR_VEE (1 << 8) 20*4882a593Smuzhiyun #define LDINTR_FS (1 << 2) 21*4882a593Smuzhiyun #define LDINTR_VSS (1 << 1) 22*4882a593Smuzhiyun #define LDINTR_VES (1 << 0) 23*4882a593Smuzhiyun #define LDINTR_STATUS_MASK (0xff << 0) 24*4882a593Smuzhiyun #define _LDSR 0x46c 25*4882a593Smuzhiyun #define LDSR_MSS (1 << 10) 26*4882a593Smuzhiyun #define LDSR_MRS (1 << 8) 27*4882a593Smuzhiyun #define LDSR_AS (1 << 1) 28*4882a593Smuzhiyun #define _LDCNT1R 0x470 29*4882a593Smuzhiyun #define LDCNT1R_DE (1 << 0) 30*4882a593Smuzhiyun #define _LDCNT2R 0x474 31*4882a593Smuzhiyun #define LDCNT2R_BR (1 << 8) 32*4882a593Smuzhiyun #define LDCNT2R_MD (1 << 3) 33*4882a593Smuzhiyun #define LDCNT2R_SE (1 << 2) 34*4882a593Smuzhiyun #define LDCNT2R_ME (1 << 1) 35*4882a593Smuzhiyun #define LDCNT2R_DO (1 << 0) 36*4882a593Smuzhiyun #define _LDRCNTR 0x478 37*4882a593Smuzhiyun #define LDRCNTR_SRS (1 << 17) 38*4882a593Smuzhiyun #define LDRCNTR_SRC (1 << 16) 39*4882a593Smuzhiyun #define LDRCNTR_MRS (1 << 1) 40*4882a593Smuzhiyun #define LDRCNTR_MRC (1 << 0) 41*4882a593Smuzhiyun #define _LDDDSR 0x47c 42*4882a593Smuzhiyun #define LDDDSR_LS (1 << 2) 43*4882a593Smuzhiyun #define LDDDSR_WS (1 << 1) 44*4882a593Smuzhiyun #define LDDDSR_BS (1 << 0) 45*4882a593Smuzhiyun 46*4882a593Smuzhiyun #define LDMT1R_VPOL (1 << 28) 47*4882a593Smuzhiyun #define LDMT1R_HPOL (1 << 27) 48*4882a593Smuzhiyun #define LDMT1R_DWPOL (1 << 26) 49*4882a593Smuzhiyun #define LDMT1R_DIPOL (1 << 25) 50*4882a593Smuzhiyun #define LDMT1R_DAPOL (1 << 24) 51*4882a593Smuzhiyun #define LDMT1R_HSCNT (1 << 17) 52*4882a593Smuzhiyun #define LDMT1R_DWCNT (1 << 16) 53*4882a593Smuzhiyun #define LDMT1R_IFM (1 << 12) 54*4882a593Smuzhiyun #define LDMT1R_MIFTYP_RGB8 (0x0 << 0) 55*4882a593Smuzhiyun #define LDMT1R_MIFTYP_RGB9 (0x4 << 0) 56*4882a593Smuzhiyun #define LDMT1R_MIFTYP_RGB12A (0x5 << 0) 57*4882a593Smuzhiyun #define LDMT1R_MIFTYP_RGB12B (0x6 << 0) 58*4882a593Smuzhiyun #define LDMT1R_MIFTYP_RGB16 (0x7 << 0) 59*4882a593Smuzhiyun #define LDMT1R_MIFTYP_RGB18 (0xa << 0) 60*4882a593Smuzhiyun #define LDMT1R_MIFTYP_RGB24 (0xb << 0) 61*4882a593Smuzhiyun #define LDMT1R_MIFTYP_YCBCR (0xf << 0) 62*4882a593Smuzhiyun #define LDMT1R_MIFTYP_SYS8A (0x0 << 0) 63*4882a593Smuzhiyun #define LDMT1R_MIFTYP_SYS8B (0x1 << 0) 64*4882a593Smuzhiyun #define LDMT1R_MIFTYP_SYS8C (0x2 << 0) 65*4882a593Smuzhiyun #define LDMT1R_MIFTYP_SYS8D (0x3 << 0) 66*4882a593Smuzhiyun #define LDMT1R_MIFTYP_SYS9 (0x4 << 0) 67*4882a593Smuzhiyun #define LDMT1R_MIFTYP_SYS12 (0x5 << 0) 68*4882a593Smuzhiyun #define LDMT1R_MIFTYP_SYS16A (0x7 << 0) 69*4882a593Smuzhiyun #define LDMT1R_MIFTYP_SYS16B (0x8 << 0) 70*4882a593Smuzhiyun #define LDMT1R_MIFTYP_SYS16C (0x9 << 0) 71*4882a593Smuzhiyun #define LDMT1R_MIFTYP_SYS18 (0xa << 0) 72*4882a593Smuzhiyun #define LDMT1R_MIFTYP_SYS24 (0xb << 0) 73*4882a593Smuzhiyun #define LDMT1R_MIFTYP_MASK (0xf << 0) 74*4882a593Smuzhiyun 75*4882a593Smuzhiyun #define LDDFR_CF1 (1 << 18) 76*4882a593Smuzhiyun #define LDDFR_CF0 (1 << 17) 77*4882a593Smuzhiyun #define LDDFR_CC (1 << 16) 78*4882a593Smuzhiyun #define LDDFR_YF_420 (0 << 8) 79*4882a593Smuzhiyun #define LDDFR_YF_422 (1 << 8) 80*4882a593Smuzhiyun #define LDDFR_YF_444 (2 << 8) 81*4882a593Smuzhiyun #define LDDFR_YF_MASK (3 << 8) 82*4882a593Smuzhiyun #define LDDFR_PKF_ARGB32 (0x00 << 0) 83*4882a593Smuzhiyun #define LDDFR_PKF_RGB16 (0x03 << 0) 84*4882a593Smuzhiyun #define LDDFR_PKF_RGB24 (0x0b << 0) 85*4882a593Smuzhiyun #define LDDFR_PKF_MASK (0x1f << 0) 86*4882a593Smuzhiyun 87*4882a593Smuzhiyun #define LDSM1R_OS (1 << 0) 88*4882a593Smuzhiyun 89*4882a593Smuzhiyun #define LDSM2R_OSTRG (1 << 0) 90*4882a593Smuzhiyun 91*4882a593Smuzhiyun #define LDPMR_LPS (3 << 0) 92*4882a593Smuzhiyun 93*4882a593Smuzhiyun #define _LDDWD0R 0x800 94*4882a593Smuzhiyun #define LDDWDxR_WDACT (1 << 28) 95*4882a593Smuzhiyun #define LDDWDxR_RSW (1 << 24) 96*4882a593Smuzhiyun #define _LDDRDR 0x840 97*4882a593Smuzhiyun #define LDDRDR_RSR (1 << 24) 98*4882a593Smuzhiyun #define LDDRDR_DRD_MASK (0x3ffff << 0) 99*4882a593Smuzhiyun #define _LDDWAR 0x900 100*4882a593Smuzhiyun #define LDDWAR_WA (1 << 0) 101*4882a593Smuzhiyun #define _LDDRAR 0x904 102*4882a593Smuzhiyun #define LDDRAR_RA (1 << 0) 103*4882a593Smuzhiyun 104*4882a593Smuzhiyun enum { 105*4882a593Smuzhiyun RGB8 = LDMT1R_MIFTYP_RGB8, /* 24bpp, 8:8:8 */ 106*4882a593Smuzhiyun RGB9 = LDMT1R_MIFTYP_RGB9, /* 18bpp, 9:9 */ 107*4882a593Smuzhiyun RGB12A = LDMT1R_MIFTYP_RGB12A, /* 24bpp, 12:12 */ 108*4882a593Smuzhiyun RGB12B = LDMT1R_MIFTYP_RGB12B, /* 12bpp */ 109*4882a593Smuzhiyun RGB16 = LDMT1R_MIFTYP_RGB16, /* 16bpp */ 110*4882a593Smuzhiyun RGB18 = LDMT1R_MIFTYP_RGB18, /* 18bpp */ 111*4882a593Smuzhiyun RGB24 = LDMT1R_MIFTYP_RGB24, /* 24bpp */ 112*4882a593Smuzhiyun YUV422 = LDMT1R_MIFTYP_YCBCR, /* 16bpp */ 113*4882a593Smuzhiyun SYS8A = LDMT1R_IFM | LDMT1R_MIFTYP_SYS8A, /* 24bpp, 8:8:8 */ 114*4882a593Smuzhiyun SYS8B = LDMT1R_IFM | LDMT1R_MIFTYP_SYS8B, /* 18bpp, 8:8:2 */ 115*4882a593Smuzhiyun SYS8C = LDMT1R_IFM | LDMT1R_MIFTYP_SYS8C, /* 18bpp, 2:8:8 */ 116*4882a593Smuzhiyun SYS8D = LDMT1R_IFM | LDMT1R_MIFTYP_SYS8D, /* 16bpp, 8:8 */ 117*4882a593Smuzhiyun SYS9 = LDMT1R_IFM | LDMT1R_MIFTYP_SYS9, /* 18bpp, 9:9 */ 118*4882a593Smuzhiyun SYS12 = LDMT1R_IFM | LDMT1R_MIFTYP_SYS12, /* 24bpp, 12:12 */ 119*4882a593Smuzhiyun SYS16A = LDMT1R_IFM | LDMT1R_MIFTYP_SYS16A, /* 16bpp */ 120*4882a593Smuzhiyun SYS16B = LDMT1R_IFM | LDMT1R_MIFTYP_SYS16B, /* 18bpp, 16:2 */ 121*4882a593Smuzhiyun SYS16C = LDMT1R_IFM | LDMT1R_MIFTYP_SYS16C, /* 18bpp, 2:16 */ 122*4882a593Smuzhiyun SYS18 = LDMT1R_IFM | LDMT1R_MIFTYP_SYS18, /* 18bpp */ 123*4882a593Smuzhiyun SYS24 = LDMT1R_IFM | LDMT1R_MIFTYP_SYS24, /* 24bpp */ 124*4882a593Smuzhiyun }; 125*4882a593Smuzhiyun 126*4882a593Smuzhiyun enum { LCDC_CHAN_DISABLED = 0, 127*4882a593Smuzhiyun LCDC_CHAN_MAINLCD, 128*4882a593Smuzhiyun LCDC_CHAN_SUBLCD }; 129*4882a593Smuzhiyun 130*4882a593Smuzhiyun enum { LCDC_CLK_BUS, LCDC_CLK_PERIPHERAL, LCDC_CLK_EXTERNAL }; 131*4882a593Smuzhiyun 132*4882a593Smuzhiyun #define LCDC_FLAGS_DWPOL (1 << 0) /* Rising edge dot clock data latch */ 133*4882a593Smuzhiyun #define LCDC_FLAGS_DIPOL (1 << 1) /* Active low display enable polarity */ 134*4882a593Smuzhiyun #define LCDC_FLAGS_DAPOL (1 << 2) /* Active low display data polarity */ 135*4882a593Smuzhiyun #define LCDC_FLAGS_HSCNT (1 << 3) /* Disable HSYNC during VBLANK */ 136*4882a593Smuzhiyun #define LCDC_FLAGS_DWCNT (1 << 4) /* Disable dotclock during blanking */ 137*4882a593Smuzhiyun 138*4882a593Smuzhiyun struct sh_mobile_lcdc_sys_bus_cfg { 139*4882a593Smuzhiyun unsigned long ldmt2r; 140*4882a593Smuzhiyun unsigned long ldmt3r; 141*4882a593Smuzhiyun unsigned long deferred_io_msec; 142*4882a593Smuzhiyun }; 143*4882a593Smuzhiyun 144*4882a593Smuzhiyun struct sh_mobile_lcdc_sys_bus_ops { 145*4882a593Smuzhiyun void (*write_index)(void *handle, unsigned long data); 146*4882a593Smuzhiyun void (*write_data)(void *handle, unsigned long data); 147*4882a593Smuzhiyun unsigned long (*read_data)(void *handle); 148*4882a593Smuzhiyun }; 149*4882a593Smuzhiyun 150*4882a593Smuzhiyun struct sh_mobile_lcdc_panel_cfg { 151*4882a593Smuzhiyun unsigned long width; /* Panel width in mm */ 152*4882a593Smuzhiyun unsigned long height; /* Panel height in mm */ 153*4882a593Smuzhiyun int (*setup_sys)(void *sys_ops_handle, 154*4882a593Smuzhiyun struct sh_mobile_lcdc_sys_bus_ops *sys_ops); 155*4882a593Smuzhiyun void (*start_transfer)(void *sys_ops_handle, 156*4882a593Smuzhiyun struct sh_mobile_lcdc_sys_bus_ops *sys_ops); 157*4882a593Smuzhiyun void (*display_on)(void); 158*4882a593Smuzhiyun void (*display_off)(void); 159*4882a593Smuzhiyun }; 160*4882a593Smuzhiyun 161*4882a593Smuzhiyun /* backlight info */ 162*4882a593Smuzhiyun struct sh_mobile_lcdc_bl_info { 163*4882a593Smuzhiyun const char *name; 164*4882a593Smuzhiyun int max_brightness; 165*4882a593Smuzhiyun int (*set_brightness)(int brightness); 166*4882a593Smuzhiyun }; 167*4882a593Smuzhiyun 168*4882a593Smuzhiyun struct sh_mobile_lcdc_overlay_cfg { 169*4882a593Smuzhiyun int fourcc; 170*4882a593Smuzhiyun unsigned int max_xres; 171*4882a593Smuzhiyun unsigned int max_yres; 172*4882a593Smuzhiyun }; 173*4882a593Smuzhiyun 174*4882a593Smuzhiyun struct sh_mobile_lcdc_chan_cfg { 175*4882a593Smuzhiyun int chan; 176*4882a593Smuzhiyun int fourcc; 177*4882a593Smuzhiyun int colorspace; 178*4882a593Smuzhiyun int interface_type; /* selects RGBn or SYSn I/F, see above */ 179*4882a593Smuzhiyun int clock_divider; 180*4882a593Smuzhiyun unsigned long flags; /* LCDC_FLAGS_... */ 181*4882a593Smuzhiyun const struct fb_videomode *lcd_modes; 182*4882a593Smuzhiyun int num_modes; 183*4882a593Smuzhiyun struct sh_mobile_lcdc_panel_cfg panel_cfg; 184*4882a593Smuzhiyun struct sh_mobile_lcdc_bl_info bl_info; 185*4882a593Smuzhiyun struct sh_mobile_lcdc_sys_bus_cfg sys_bus_cfg; /* only for SYSn I/F */ 186*4882a593Smuzhiyun 187*4882a593Smuzhiyun struct platform_device *tx_dev; /* HDMI/DSI transmitter device */ 188*4882a593Smuzhiyun }; 189*4882a593Smuzhiyun 190*4882a593Smuzhiyun struct sh_mobile_lcdc_info { 191*4882a593Smuzhiyun int clock_source; 192*4882a593Smuzhiyun struct sh_mobile_lcdc_chan_cfg ch[2]; 193*4882a593Smuzhiyun struct sh_mobile_lcdc_overlay_cfg overlays[4]; 194*4882a593Smuzhiyun }; 195*4882a593Smuzhiyun 196*4882a593Smuzhiyun #endif /* __ASM_SH_MOBILE_LCDC_H__ */ 197