1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-only */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Copyright (C) 2009 Marvell International Ltd. 4*4882a593Smuzhiyun */ 5*4882a593Smuzhiyun 6*4882a593Smuzhiyun #ifndef __ASM_MACH_PXA168FB_H 7*4882a593Smuzhiyun #define __ASM_MACH_PXA168FB_H 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun #include <linux/fb.h> 10*4882a593Smuzhiyun #include <linux/interrupt.h> 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun /* Dumb interface */ 13*4882a593Smuzhiyun #define PIN_MODE_DUMB_24 0 14*4882a593Smuzhiyun #define PIN_MODE_DUMB_18_SPI 1 15*4882a593Smuzhiyun #define PIN_MODE_DUMB_18_GPIO 2 16*4882a593Smuzhiyun #define PIN_MODE_DUMB_16_SPI 3 17*4882a593Smuzhiyun #define PIN_MODE_DUMB_16_GPIO 4 18*4882a593Smuzhiyun #define PIN_MODE_DUMB_12_SPI_GPIO 5 19*4882a593Smuzhiyun #define PIN_MODE_SMART_18_SPI 6 20*4882a593Smuzhiyun #define PIN_MODE_SMART_16_SPI 7 21*4882a593Smuzhiyun #define PIN_MODE_SMART_8_SPI_GPIO 8 22*4882a593Smuzhiyun 23*4882a593Smuzhiyun /* Dumb interface pin allocation */ 24*4882a593Smuzhiyun #define DUMB_MODE_RGB565 0 25*4882a593Smuzhiyun #define DUMB_MODE_RGB565_UPPER 1 26*4882a593Smuzhiyun #define DUMB_MODE_RGB666 2 27*4882a593Smuzhiyun #define DUMB_MODE_RGB666_UPPER 3 28*4882a593Smuzhiyun #define DUMB_MODE_RGB444 4 29*4882a593Smuzhiyun #define DUMB_MODE_RGB444_UPPER 5 30*4882a593Smuzhiyun #define DUMB_MODE_RGB888 6 31*4882a593Smuzhiyun 32*4882a593Smuzhiyun /* default fb buffer size WVGA-32bits */ 33*4882a593Smuzhiyun #define DEFAULT_FB_SIZE (800 * 480 * 4) 34*4882a593Smuzhiyun 35*4882a593Smuzhiyun /* 36*4882a593Smuzhiyun * Buffer pixel format 37*4882a593Smuzhiyun * bit0 is for rb swap. 38*4882a593Smuzhiyun * bit12 is for Y UorV swap 39*4882a593Smuzhiyun */ 40*4882a593Smuzhiyun #define PIX_FMT_RGB565 0 41*4882a593Smuzhiyun #define PIX_FMT_BGR565 1 42*4882a593Smuzhiyun #define PIX_FMT_RGB1555 2 43*4882a593Smuzhiyun #define PIX_FMT_BGR1555 3 44*4882a593Smuzhiyun #define PIX_FMT_RGB888PACK 4 45*4882a593Smuzhiyun #define PIX_FMT_BGR888PACK 5 46*4882a593Smuzhiyun #define PIX_FMT_RGB888UNPACK 6 47*4882a593Smuzhiyun #define PIX_FMT_BGR888UNPACK 7 48*4882a593Smuzhiyun #define PIX_FMT_RGBA888 8 49*4882a593Smuzhiyun #define PIX_FMT_BGRA888 9 50*4882a593Smuzhiyun #define PIX_FMT_YUV422PACK 10 51*4882a593Smuzhiyun #define PIX_FMT_YVU422PACK 11 52*4882a593Smuzhiyun #define PIX_FMT_YUV422PLANAR 12 53*4882a593Smuzhiyun #define PIX_FMT_YVU422PLANAR 13 54*4882a593Smuzhiyun #define PIX_FMT_YUV420PLANAR 14 55*4882a593Smuzhiyun #define PIX_FMT_YVU420PLANAR 15 56*4882a593Smuzhiyun #define PIX_FMT_PSEUDOCOLOR 20 57*4882a593Smuzhiyun #define PIX_FMT_UYVY422PACK (0x1000|PIX_FMT_YUV422PACK) 58*4882a593Smuzhiyun 59*4882a593Smuzhiyun /* 60*4882a593Smuzhiyun * PXA LCD controller private state. 61*4882a593Smuzhiyun */ 62*4882a593Smuzhiyun struct pxa168fb_info { 63*4882a593Smuzhiyun struct device *dev; 64*4882a593Smuzhiyun struct clk *clk; 65*4882a593Smuzhiyun struct fb_info *info; 66*4882a593Smuzhiyun 67*4882a593Smuzhiyun void __iomem *reg_base; 68*4882a593Smuzhiyun dma_addr_t fb_start_dma; 69*4882a593Smuzhiyun u32 pseudo_palette[16]; 70*4882a593Smuzhiyun 71*4882a593Smuzhiyun int pix_fmt; 72*4882a593Smuzhiyun unsigned is_blanked:1; 73*4882a593Smuzhiyun unsigned panel_rbswap:1; 74*4882a593Smuzhiyun unsigned active:1; 75*4882a593Smuzhiyun }; 76*4882a593Smuzhiyun 77*4882a593Smuzhiyun /* 78*4882a593Smuzhiyun * PXA fb machine information 79*4882a593Smuzhiyun */ 80*4882a593Smuzhiyun struct pxa168fb_mach_info { 81*4882a593Smuzhiyun char id[16]; 82*4882a593Smuzhiyun 83*4882a593Smuzhiyun int num_modes; 84*4882a593Smuzhiyun struct fb_videomode *modes; 85*4882a593Smuzhiyun 86*4882a593Smuzhiyun /* 87*4882a593Smuzhiyun * Pix_fmt 88*4882a593Smuzhiyun */ 89*4882a593Smuzhiyun unsigned pix_fmt; 90*4882a593Smuzhiyun 91*4882a593Smuzhiyun /* 92*4882a593Smuzhiyun * I/O pin allocation. 93*4882a593Smuzhiyun */ 94*4882a593Smuzhiyun unsigned io_pin_allocation_mode:4; 95*4882a593Smuzhiyun 96*4882a593Smuzhiyun /* 97*4882a593Smuzhiyun * Dumb panel -- assignment of R/G/B component info to the 24 98*4882a593Smuzhiyun * available external data lanes. 99*4882a593Smuzhiyun */ 100*4882a593Smuzhiyun unsigned dumb_mode:4; 101*4882a593Smuzhiyun unsigned panel_rgb_reverse_lanes:1; 102*4882a593Smuzhiyun 103*4882a593Smuzhiyun /* 104*4882a593Smuzhiyun * Dumb panel -- GPIO output data. 105*4882a593Smuzhiyun */ 106*4882a593Smuzhiyun unsigned gpio_output_mask:8; 107*4882a593Smuzhiyun unsigned gpio_output_data:8; 108*4882a593Smuzhiyun 109*4882a593Smuzhiyun /* 110*4882a593Smuzhiyun * Dumb panel -- configurable output signal polarity. 111*4882a593Smuzhiyun */ 112*4882a593Smuzhiyun unsigned invert_composite_blank:1; 113*4882a593Smuzhiyun unsigned invert_pix_val_ena:1; 114*4882a593Smuzhiyun unsigned invert_pixclock:1; 115*4882a593Smuzhiyun unsigned panel_rbswap:1; 116*4882a593Smuzhiyun unsigned active:1; 117*4882a593Smuzhiyun unsigned enable_lcd:1; 118*4882a593Smuzhiyun }; 119*4882a593Smuzhiyun 120*4882a593Smuzhiyun #endif /* __ASM_MACH_PXA168FB_H */ 121