1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * linux/include/video/pmagb-b-fb.h 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * TURBOchannel PMAGB-B Smart Frame Buffer (SFB) card support, 5*4882a593Smuzhiyun * Copyright (C) 1999, 2000, 2001 by 6*4882a593Smuzhiyun * Michael Engel <engel@unix-ag.org> and 7*4882a593Smuzhiyun * Karsten Merker <merker@linuxtag.org> 8*4882a593Smuzhiyun * Copyright (c) 2005 Maciej W. Rozycki 9*4882a593Smuzhiyun * 10*4882a593Smuzhiyun * This file is subject to the terms and conditions of the GNU General 11*4882a593Smuzhiyun * Public License. See the file COPYING in the main directory of this 12*4882a593Smuzhiyun * archive for more details. 13*4882a593Smuzhiyun */ 14*4882a593Smuzhiyun 15*4882a593Smuzhiyun /* IOmem resource offsets. */ 16*4882a593Smuzhiyun #define PMAGB_B_ROM 0x000000 /* REX option ROM */ 17*4882a593Smuzhiyun #define PMAGB_B_SFB 0x100000 /* SFB ASIC */ 18*4882a593Smuzhiyun #define PMAGB_B_GP0 0x140000 /* general purpose output 0 */ 19*4882a593Smuzhiyun #define PMAGB_B_GP1 0x180000 /* general purpose output 1 */ 20*4882a593Smuzhiyun #define PMAGB_B_BT459 0x1c0000 /* Bt459 RAMDAC */ 21*4882a593Smuzhiyun #define PMAGB_B_FBMEM 0x200000 /* frame buffer */ 22*4882a593Smuzhiyun #define PMAGB_B_SIZE 0x400000 /* address space size */ 23*4882a593Smuzhiyun 24*4882a593Smuzhiyun /* IOmem register offsets. */ 25*4882a593Smuzhiyun #define SFB_REG_VID_HOR 0x64 /* video horizontal setup */ 26*4882a593Smuzhiyun #define SFB_REG_VID_VER 0x68 /* video vertical setup */ 27*4882a593Smuzhiyun #define SFB_REG_VID_BASE 0x6c /* video base address */ 28*4882a593Smuzhiyun #define SFB_REG_TCCLK_COUNT 0x78 /* TURBOchannel clock count */ 29*4882a593Smuzhiyun #define SFB_REG_VIDCLK_COUNT 0x7c /* video clock count */ 30*4882a593Smuzhiyun 31*4882a593Smuzhiyun /* Video horizontal setup register constants. All bits are r/w. */ 32*4882a593Smuzhiyun #define SFB_VID_HOR_BP_SHIFT 0x15 /* back porch */ 33*4882a593Smuzhiyun #define SFB_VID_HOR_BP_MASK 0x7f 34*4882a593Smuzhiyun #define SFB_VID_HOR_SYN_SHIFT 0x0e /* sync pulse */ 35*4882a593Smuzhiyun #define SFB_VID_HOR_SYN_MASK 0x7f 36*4882a593Smuzhiyun #define SFB_VID_HOR_FP_SHIFT 0x09 /* front porch */ 37*4882a593Smuzhiyun #define SFB_VID_HOR_FP_MASK 0x1f 38*4882a593Smuzhiyun #define SFB_VID_HOR_PIX_SHIFT 0x00 /* active video */ 39*4882a593Smuzhiyun #define SFB_VID_HOR_PIX_MASK 0x1ff 40*4882a593Smuzhiyun 41*4882a593Smuzhiyun /* Video vertical setup register constants. All bits are r/w. */ 42*4882a593Smuzhiyun #define SFB_VID_VER_BP_SHIFT 0x16 /* back porch */ 43*4882a593Smuzhiyun #define SFB_VID_VER_BP_MASK 0x3f 44*4882a593Smuzhiyun #define SFB_VID_VER_SYN_SHIFT 0x10 /* sync pulse */ 45*4882a593Smuzhiyun #define SFB_VID_VER_SYN_MASK 0x3f 46*4882a593Smuzhiyun #define SFB_VID_VER_FP_SHIFT 0x0b /* front porch */ 47*4882a593Smuzhiyun #define SFB_VID_VER_FP_MASK 0x1f 48*4882a593Smuzhiyun #define SFB_VID_VER_SL_SHIFT 0x00 /* active scan lines */ 49*4882a593Smuzhiyun #define SFB_VID_VER_SL_MASK 0x7ff 50*4882a593Smuzhiyun 51*4882a593Smuzhiyun /* Video base address register constants. All bits are r/w. */ 52*4882a593Smuzhiyun #define SFB_VID_BASE_MASK 0x1ff /* video base row address */ 53*4882a593Smuzhiyun 54*4882a593Smuzhiyun /* Bt459 register offsets, byte-wide registers. */ 55*4882a593Smuzhiyun #define BT459_ADDR_LO 0x0 /* address low */ 56*4882a593Smuzhiyun #define BT459_ADDR_HI 0x4 /* address high */ 57*4882a593Smuzhiyun #define BT459_DATA 0x8 /* data window register */ 58*4882a593Smuzhiyun #define BT459_CMAP 0xc /* color map window register */ 59