1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-or-later */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * ATI Mach64 Register Definitions 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Copyright (C) 1997 Michael AK Tesch 6*4882a593Smuzhiyun * written with much help from Jon Howell 7*4882a593Smuzhiyun * 8*4882a593Smuzhiyun * Updated for 3D RAGE PRO and 3D RAGE Mobility by Geert Uytterhoeven 9*4882a593Smuzhiyun */ 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun /* 12*4882a593Smuzhiyun * most of the rest of this file comes from ATI sample code 13*4882a593Smuzhiyun */ 14*4882a593Smuzhiyun #ifndef REGMACH64_H 15*4882a593Smuzhiyun #define REGMACH64_H 16*4882a593Smuzhiyun 17*4882a593Smuzhiyun /* NON-GUI MEMORY MAPPED Registers - expressed in BYTE offsets */ 18*4882a593Smuzhiyun 19*4882a593Smuzhiyun /* Accelerator CRTC */ 20*4882a593Smuzhiyun #define CRTC_H_TOTAL_DISP 0x0000 /* Dword offset 0_00 */ 21*4882a593Smuzhiyun #define CRTC2_H_TOTAL_DISP 0x0000 /* Dword offset 0_00 */ 22*4882a593Smuzhiyun #define CRTC_H_SYNC_STRT_WID 0x0004 /* Dword offset 0_01 */ 23*4882a593Smuzhiyun #define CRTC2_H_SYNC_STRT_WID 0x0004 /* Dword offset 0_01 */ 24*4882a593Smuzhiyun #define CRTC_H_SYNC_STRT 0x0004 25*4882a593Smuzhiyun #define CRTC2_H_SYNC_STRT 0x0004 26*4882a593Smuzhiyun #define CRTC_H_SYNC_DLY 0x0005 27*4882a593Smuzhiyun #define CRTC2_H_SYNC_DLY 0x0005 28*4882a593Smuzhiyun #define CRTC_H_SYNC_WID 0x0006 29*4882a593Smuzhiyun #define CRTC2_H_SYNC_WID 0x0006 30*4882a593Smuzhiyun #define CRTC_V_TOTAL_DISP 0x0008 /* Dword offset 0_02 */ 31*4882a593Smuzhiyun #define CRTC2_V_TOTAL_DISP 0x0008 /* Dword offset 0_02 */ 32*4882a593Smuzhiyun #define CRTC_V_TOTAL 0x0008 33*4882a593Smuzhiyun #define CRTC2_V_TOTAL 0x0008 34*4882a593Smuzhiyun #define CRTC_V_DISP 0x000A 35*4882a593Smuzhiyun #define CRTC2_V_DISP 0x000A 36*4882a593Smuzhiyun #define CRTC_V_SYNC_STRT_WID 0x000C /* Dword offset 0_03 */ 37*4882a593Smuzhiyun #define CRTC2_V_SYNC_STRT_WID 0x000C /* Dword offset 0_03 */ 38*4882a593Smuzhiyun #define CRTC_V_SYNC_STRT 0x000C 39*4882a593Smuzhiyun #define CRTC2_V_SYNC_STRT 0x000C 40*4882a593Smuzhiyun #define CRTC_V_SYNC_WID 0x000E 41*4882a593Smuzhiyun #define CRTC2_V_SYNC_WID 0x000E 42*4882a593Smuzhiyun #define CRTC_VLINE_CRNT_VLINE 0x0010 /* Dword offset 0_04 */ 43*4882a593Smuzhiyun #define CRTC2_VLINE_CRNT_VLINE 0x0010 /* Dword offset 0_04 */ 44*4882a593Smuzhiyun #define CRTC_OFF_PITCH 0x0014 /* Dword offset 0_05 */ 45*4882a593Smuzhiyun #define CRTC_OFFSET 0x0014 46*4882a593Smuzhiyun #define CRTC_PITCH 0x0016 47*4882a593Smuzhiyun #define CRTC_INT_CNTL 0x0018 /* Dword offset 0_06 */ 48*4882a593Smuzhiyun #define CRTC_GEN_CNTL 0x001C /* Dword offset 0_07 */ 49*4882a593Smuzhiyun #define CRTC_PIX_WIDTH 0x001D 50*4882a593Smuzhiyun #define CRTC_FIFO 0x001E 51*4882a593Smuzhiyun #define CRTC_EXT_DISP 0x001F 52*4882a593Smuzhiyun 53*4882a593Smuzhiyun /* Memory Buffer Control */ 54*4882a593Smuzhiyun #define DSP_CONFIG 0x0020 /* Dword offset 0_08 */ 55*4882a593Smuzhiyun #define PM_DSP_CONFIG 0x0020 /* Dword offset 0_08 (Mobility Only) */ 56*4882a593Smuzhiyun #define DSP_ON_OFF 0x0024 /* Dword offset 0_09 */ 57*4882a593Smuzhiyun #define PM_DSP_ON_OFF 0x0024 /* Dword offset 0_09 (Mobility Only) */ 58*4882a593Smuzhiyun #define TIMER_CONFIG 0x0028 /* Dword offset 0_0A */ 59*4882a593Smuzhiyun #define MEM_BUF_CNTL 0x002C /* Dword offset 0_0B */ 60*4882a593Smuzhiyun #define MEM_ADDR_CONFIG 0x0034 /* Dword offset 0_0D */ 61*4882a593Smuzhiyun 62*4882a593Smuzhiyun /* Accelerator CRTC */ 63*4882a593Smuzhiyun #define CRT_TRAP 0x0038 /* Dword offset 0_0E */ 64*4882a593Smuzhiyun 65*4882a593Smuzhiyun #define I2C_CNTL_0 0x003C /* Dword offset 0_0F */ 66*4882a593Smuzhiyun 67*4882a593Smuzhiyun #define DSTN_CONTROL_LG 0x003C /* Dword offset 0_0F (LG) */ 68*4882a593Smuzhiyun 69*4882a593Smuzhiyun /* Overscan */ 70*4882a593Smuzhiyun #define OVR_CLR 0x0040 /* Dword offset 0_10 */ 71*4882a593Smuzhiyun #define OVR2_CLR 0x0040 /* Dword offset 0_10 */ 72*4882a593Smuzhiyun #define OVR_WID_LEFT_RIGHT 0x0044 /* Dword offset 0_11 */ 73*4882a593Smuzhiyun #define OVR2_WID_LEFT_RIGHT 0x0044 /* Dword offset 0_11 */ 74*4882a593Smuzhiyun #define OVR_WID_TOP_BOTTOM 0x0048 /* Dword offset 0_12 */ 75*4882a593Smuzhiyun #define OVR2_WID_TOP_BOTTOM 0x0048 /* Dword offset 0_12 */ 76*4882a593Smuzhiyun 77*4882a593Smuzhiyun /* Memory Buffer Control */ 78*4882a593Smuzhiyun #define VGA_DSP_CONFIG 0x004C /* Dword offset 0_13 */ 79*4882a593Smuzhiyun #define PM_VGA_DSP_CONFIG 0x004C /* Dword offset 0_13 (Mobility Only) */ 80*4882a593Smuzhiyun #define VGA_DSP_ON_OFF 0x0050 /* Dword offset 0_14 */ 81*4882a593Smuzhiyun #define PM_VGA_DSP_ON_OFF 0x0050 /* Dword offset 0_14 (Mobility Only) */ 82*4882a593Smuzhiyun #define DSP2_CONFIG 0x0054 /* Dword offset 0_15 */ 83*4882a593Smuzhiyun #define PM_DSP2_CONFIG 0x0054 /* Dword offset 0_15 (Mobility Only) */ 84*4882a593Smuzhiyun #define DSP2_ON_OFF 0x0058 /* Dword offset 0_16 */ 85*4882a593Smuzhiyun #define PM_DSP2_ON_OFF 0x0058 /* Dword offset 0_16 (Mobility Only) */ 86*4882a593Smuzhiyun 87*4882a593Smuzhiyun /* Accelerator CRTC */ 88*4882a593Smuzhiyun #define CRTC2_OFF_PITCH 0x005C /* Dword offset 0_17 */ 89*4882a593Smuzhiyun 90*4882a593Smuzhiyun /* Hardware Cursor */ 91*4882a593Smuzhiyun #define CUR_CLR0 0x0060 /* Dword offset 0_18 */ 92*4882a593Smuzhiyun #define CUR2_CLR0 0x0060 /* Dword offset 0_18 */ 93*4882a593Smuzhiyun #define CUR_CLR1 0x0064 /* Dword offset 0_19 */ 94*4882a593Smuzhiyun #define CUR2_CLR1 0x0064 /* Dword offset 0_19 */ 95*4882a593Smuzhiyun #define CUR_OFFSET 0x0068 /* Dword offset 0_1A */ 96*4882a593Smuzhiyun #define CUR2_OFFSET 0x0068 /* Dword offset 0_1A */ 97*4882a593Smuzhiyun #define CUR_HORZ_VERT_POSN 0x006C /* Dword offset 0_1B */ 98*4882a593Smuzhiyun #define CUR2_HORZ_VERT_POSN 0x006C /* Dword offset 0_1B */ 99*4882a593Smuzhiyun #define CUR_HORZ_VERT_OFF 0x0070 /* Dword offset 0_1C */ 100*4882a593Smuzhiyun #define CUR2_HORZ_VERT_OFF 0x0070 /* Dword offset 0_1C */ 101*4882a593Smuzhiyun 102*4882a593Smuzhiyun #define CNFG_PANEL_LG 0x0074 /* Dword offset 0_1D (LG) */ 103*4882a593Smuzhiyun 104*4882a593Smuzhiyun /* General I/O Control */ 105*4882a593Smuzhiyun #define GP_IO 0x0078 /* Dword offset 0_1E */ 106*4882a593Smuzhiyun 107*4882a593Smuzhiyun /* Test and Debug */ 108*4882a593Smuzhiyun #define HW_DEBUG 0x007C /* Dword offset 0_1F */ 109*4882a593Smuzhiyun 110*4882a593Smuzhiyun /* Scratch Pad and Test */ 111*4882a593Smuzhiyun #define SCRATCH_REG0 0x0080 /* Dword offset 0_20 */ 112*4882a593Smuzhiyun #define SCRATCH_REG1 0x0084 /* Dword offset 0_21 */ 113*4882a593Smuzhiyun #define SCRATCH_REG2 0x0088 /* Dword offset 0_22 */ 114*4882a593Smuzhiyun #define SCRATCH_REG3 0x008C /* Dword offset 0_23 */ 115*4882a593Smuzhiyun 116*4882a593Smuzhiyun /* Clock Control */ 117*4882a593Smuzhiyun #define CLOCK_CNTL 0x0090 /* Dword offset 0_24 */ 118*4882a593Smuzhiyun /* CLOCK_CNTL register constants CT LAYOUT */ 119*4882a593Smuzhiyun #define CLOCK_SEL 0x0f 120*4882a593Smuzhiyun #define CLOCK_SEL_INTERNAL 0x03 121*4882a593Smuzhiyun #define CLOCK_SEL_EXTERNAL 0x0c 122*4882a593Smuzhiyun #define CLOCK_DIV 0x30 123*4882a593Smuzhiyun #define CLOCK_DIV1 0x00 124*4882a593Smuzhiyun #define CLOCK_DIV2 0x10 125*4882a593Smuzhiyun #define CLOCK_DIV4 0x20 126*4882a593Smuzhiyun #define CLOCK_STROBE 0x40 127*4882a593Smuzhiyun /* ? 0x80 */ 128*4882a593Smuzhiyun /* CLOCK_CNTL register constants GX LAYOUT */ 129*4882a593Smuzhiyun #define CLOCK_BIT 0x04 /* For ICS2595 */ 130*4882a593Smuzhiyun #define CLOCK_PULSE 0x08 /* For ICS2595 */ 131*4882a593Smuzhiyun /*#define CLOCK_STROBE 0x40 dito as CT */ 132*4882a593Smuzhiyun #define CLOCK_DATA 0x80 133*4882a593Smuzhiyun 134*4882a593Smuzhiyun /* For internal PLL(CT) start */ 135*4882a593Smuzhiyun #define CLOCK_CNTL_ADDR CLOCK_CNTL + 1 136*4882a593Smuzhiyun #define PLL_WR_EN 0x02 137*4882a593Smuzhiyun #define PLL_ADDR 0xfc 138*4882a593Smuzhiyun #define CLOCK_CNTL_DATA CLOCK_CNTL + 2 139*4882a593Smuzhiyun #define PLL_DATA 0xff 140*4882a593Smuzhiyun /* For internal PLL(CT) end */ 141*4882a593Smuzhiyun 142*4882a593Smuzhiyun #define CLOCK_SEL_CNTL 0x0090 /* Dword offset 0_24 */ 143*4882a593Smuzhiyun 144*4882a593Smuzhiyun /* Configuration */ 145*4882a593Smuzhiyun #define CNFG_STAT1 0x0094 /* Dword offset 0_25 */ 146*4882a593Smuzhiyun #define CNFG_STAT2 0x0098 /* Dword offset 0_26 */ 147*4882a593Smuzhiyun 148*4882a593Smuzhiyun /* Bus Control */ 149*4882a593Smuzhiyun #define BUS_CNTL 0x00A0 /* Dword offset 0_28 */ 150*4882a593Smuzhiyun 151*4882a593Smuzhiyun #define LCD_INDEX 0x00A4 /* Dword offset 0_29 */ 152*4882a593Smuzhiyun #define LCD_DATA 0x00A8 /* Dword offset 0_2A */ 153*4882a593Smuzhiyun 154*4882a593Smuzhiyun #define HFB_PITCH_ADDR_LG 0x00A8 /* Dword offset 0_2A (LG) */ 155*4882a593Smuzhiyun 156*4882a593Smuzhiyun /* Memory Control */ 157*4882a593Smuzhiyun #define EXT_MEM_CNTL 0x00AC /* Dword offset 0_2B */ 158*4882a593Smuzhiyun #define MEM_CNTL 0x00B0 /* Dword offset 0_2C */ 159*4882a593Smuzhiyun #define MEM_VGA_WP_SEL 0x00B4 /* Dword offset 0_2D */ 160*4882a593Smuzhiyun #define MEM_VGA_RP_SEL 0x00B8 /* Dword offset 0_2E */ 161*4882a593Smuzhiyun 162*4882a593Smuzhiyun #define I2C_CNTL_1 0x00BC /* Dword offset 0_2F */ 163*4882a593Smuzhiyun 164*4882a593Smuzhiyun #define LT_GIO_LG 0x00BC /* Dword offset 0_2F (LG) */ 165*4882a593Smuzhiyun 166*4882a593Smuzhiyun /* DAC Control */ 167*4882a593Smuzhiyun #define DAC_REGS 0x00C0 /* Dword offset 0_30 */ 168*4882a593Smuzhiyun #define DAC_W_INDEX 0x00C0 /* Dword offset 0_30 */ 169*4882a593Smuzhiyun #define DAC_DATA 0x00C1 /* Dword offset 0_30 */ 170*4882a593Smuzhiyun #define DAC_MASK 0x00C2 /* Dword offset 0_30 */ 171*4882a593Smuzhiyun #define DAC_R_INDEX 0x00C3 /* Dword offset 0_30 */ 172*4882a593Smuzhiyun #define DAC_CNTL 0x00C4 /* Dword offset 0_31 */ 173*4882a593Smuzhiyun 174*4882a593Smuzhiyun #define EXT_DAC_REGS 0x00C8 /* Dword offset 0_32 */ 175*4882a593Smuzhiyun 176*4882a593Smuzhiyun #define HORZ_STRETCHING_LG 0x00C8 /* Dword offset 0_32 (LG) */ 177*4882a593Smuzhiyun #define VERT_STRETCHING_LG 0x00CC /* Dword offset 0_33 (LG) */ 178*4882a593Smuzhiyun 179*4882a593Smuzhiyun /* Test and Debug */ 180*4882a593Smuzhiyun #define GEN_TEST_CNTL 0x00D0 /* Dword offset 0_34 */ 181*4882a593Smuzhiyun 182*4882a593Smuzhiyun /* Custom Macros */ 183*4882a593Smuzhiyun #define CUSTOM_MACRO_CNTL 0x00D4 /* Dword offset 0_35 */ 184*4882a593Smuzhiyun 185*4882a593Smuzhiyun #define LCD_GEN_CNTL_LG 0x00D4 /* Dword offset 0_35 (LG) */ 186*4882a593Smuzhiyun #define POWER_MANAGEMENT_LG 0x00D8 /* Dword offset 0_36 (LG) */ 187*4882a593Smuzhiyun 188*4882a593Smuzhiyun /* Configuration */ 189*4882a593Smuzhiyun #define CNFG_CNTL 0x00DC /* Dword offset 0_37 (CT, ET, VT) */ 190*4882a593Smuzhiyun #define CNFG_CHIP_ID 0x00E0 /* Dword offset 0_38 */ 191*4882a593Smuzhiyun #define CNFG_STAT0 0x00E4 /* Dword offset 0_39 */ 192*4882a593Smuzhiyun 193*4882a593Smuzhiyun /* Test and Debug */ 194*4882a593Smuzhiyun #define CRC_SIG 0x00E8 /* Dword offset 0_3A */ 195*4882a593Smuzhiyun #define CRC2_SIG 0x00E8 /* Dword offset 0_3A */ 196*4882a593Smuzhiyun 197*4882a593Smuzhiyun 198*4882a593Smuzhiyun /* GUI MEMORY MAPPED Registers */ 199*4882a593Smuzhiyun 200*4882a593Smuzhiyun /* Draw Engine Destination Trajectory */ 201*4882a593Smuzhiyun #define DST_OFF_PITCH 0x0100 /* Dword offset 0_40 */ 202*4882a593Smuzhiyun #define DST_X 0x0104 /* Dword offset 0_41 */ 203*4882a593Smuzhiyun #define DST_Y 0x0108 /* Dword offset 0_42 */ 204*4882a593Smuzhiyun #define DST_Y_X 0x010C /* Dword offset 0_43 */ 205*4882a593Smuzhiyun #define DST_WIDTH 0x0110 /* Dword offset 0_44 */ 206*4882a593Smuzhiyun #define DST_HEIGHT 0x0114 /* Dword offset 0_45 */ 207*4882a593Smuzhiyun #define DST_HEIGHT_WIDTH 0x0118 /* Dword offset 0_46 */ 208*4882a593Smuzhiyun #define DST_X_WIDTH 0x011C /* Dword offset 0_47 */ 209*4882a593Smuzhiyun #define DST_BRES_LNTH 0x0120 /* Dword offset 0_48 */ 210*4882a593Smuzhiyun #define DST_BRES_ERR 0x0124 /* Dword offset 0_49 */ 211*4882a593Smuzhiyun #define DST_BRES_INC 0x0128 /* Dword offset 0_4A */ 212*4882a593Smuzhiyun #define DST_BRES_DEC 0x012C /* Dword offset 0_4B */ 213*4882a593Smuzhiyun #define DST_CNTL 0x0130 /* Dword offset 0_4C */ 214*4882a593Smuzhiyun #define DST_Y_X__ALIAS__ 0x0134 /* Dword offset 0_4D */ 215*4882a593Smuzhiyun #define TRAIL_BRES_ERR 0x0138 /* Dword offset 0_4E */ 216*4882a593Smuzhiyun #define TRAIL_BRES_INC 0x013C /* Dword offset 0_4F */ 217*4882a593Smuzhiyun #define TRAIL_BRES_DEC 0x0140 /* Dword offset 0_50 */ 218*4882a593Smuzhiyun #define LEAD_BRES_LNTH 0x0144 /* Dword offset 0_51 */ 219*4882a593Smuzhiyun #define Z_OFF_PITCH 0x0148 /* Dword offset 0_52 */ 220*4882a593Smuzhiyun #define Z_CNTL 0x014C /* Dword offset 0_53 */ 221*4882a593Smuzhiyun #define ALPHA_TST_CNTL 0x0150 /* Dword offset 0_54 */ 222*4882a593Smuzhiyun #define SECONDARY_STW_EXP 0x0158 /* Dword offset 0_56 */ 223*4882a593Smuzhiyun #define SECONDARY_S_X_INC 0x015C /* Dword offset 0_57 */ 224*4882a593Smuzhiyun #define SECONDARY_S_Y_INC 0x0160 /* Dword offset 0_58 */ 225*4882a593Smuzhiyun #define SECONDARY_S_START 0x0164 /* Dword offset 0_59 */ 226*4882a593Smuzhiyun #define SECONDARY_W_X_INC 0x0168 /* Dword offset 0_5A */ 227*4882a593Smuzhiyun #define SECONDARY_W_Y_INC 0x016C /* Dword offset 0_5B */ 228*4882a593Smuzhiyun #define SECONDARY_W_START 0x0170 /* Dword offset 0_5C */ 229*4882a593Smuzhiyun #define SECONDARY_T_X_INC 0x0174 /* Dword offset 0_5D */ 230*4882a593Smuzhiyun #define SECONDARY_T_Y_INC 0x0178 /* Dword offset 0_5E */ 231*4882a593Smuzhiyun #define SECONDARY_T_START 0x017C /* Dword offset 0_5F */ 232*4882a593Smuzhiyun 233*4882a593Smuzhiyun /* Draw Engine Source Trajectory */ 234*4882a593Smuzhiyun #define SRC_OFF_PITCH 0x0180 /* Dword offset 0_60 */ 235*4882a593Smuzhiyun #define SRC_X 0x0184 /* Dword offset 0_61 */ 236*4882a593Smuzhiyun #define SRC_Y 0x0188 /* Dword offset 0_62 */ 237*4882a593Smuzhiyun #define SRC_Y_X 0x018C /* Dword offset 0_63 */ 238*4882a593Smuzhiyun #define SRC_WIDTH1 0x0190 /* Dword offset 0_64 */ 239*4882a593Smuzhiyun #define SRC_HEIGHT1 0x0194 /* Dword offset 0_65 */ 240*4882a593Smuzhiyun #define SRC_HEIGHT1_WIDTH1 0x0198 /* Dword offset 0_66 */ 241*4882a593Smuzhiyun #define SRC_X_START 0x019C /* Dword offset 0_67 */ 242*4882a593Smuzhiyun #define SRC_Y_START 0x01A0 /* Dword offset 0_68 */ 243*4882a593Smuzhiyun #define SRC_Y_X_START 0x01A4 /* Dword offset 0_69 */ 244*4882a593Smuzhiyun #define SRC_WIDTH2 0x01A8 /* Dword offset 0_6A */ 245*4882a593Smuzhiyun #define SRC_HEIGHT2 0x01AC /* Dword offset 0_6B */ 246*4882a593Smuzhiyun #define SRC_HEIGHT2_WIDTH2 0x01B0 /* Dword offset 0_6C */ 247*4882a593Smuzhiyun #define SRC_CNTL 0x01B4 /* Dword offset 0_6D */ 248*4882a593Smuzhiyun 249*4882a593Smuzhiyun #define SCALE_OFF 0x01C0 /* Dword offset 0_70 */ 250*4882a593Smuzhiyun #define SECONDARY_SCALE_OFF 0x01C4 /* Dword offset 0_71 */ 251*4882a593Smuzhiyun 252*4882a593Smuzhiyun #define TEX_0_OFF 0x01C0 /* Dword offset 0_70 */ 253*4882a593Smuzhiyun #define TEX_1_OFF 0x01C4 /* Dword offset 0_71 */ 254*4882a593Smuzhiyun #define TEX_2_OFF 0x01C8 /* Dword offset 0_72 */ 255*4882a593Smuzhiyun #define TEX_3_OFF 0x01CC /* Dword offset 0_73 */ 256*4882a593Smuzhiyun #define TEX_4_OFF 0x01D0 /* Dword offset 0_74 */ 257*4882a593Smuzhiyun #define TEX_5_OFF 0x01D4 /* Dword offset 0_75 */ 258*4882a593Smuzhiyun #define TEX_6_OFF 0x01D8 /* Dword offset 0_76 */ 259*4882a593Smuzhiyun #define TEX_7_OFF 0x01DC /* Dword offset 0_77 */ 260*4882a593Smuzhiyun 261*4882a593Smuzhiyun #define SCALE_WIDTH 0x01DC /* Dword offset 0_77 */ 262*4882a593Smuzhiyun #define SCALE_HEIGHT 0x01E0 /* Dword offset 0_78 */ 263*4882a593Smuzhiyun 264*4882a593Smuzhiyun #define TEX_8_OFF 0x01E0 /* Dword offset 0_78 */ 265*4882a593Smuzhiyun #define TEX_9_OFF 0x01E4 /* Dword offset 0_79 */ 266*4882a593Smuzhiyun #define TEX_10_OFF 0x01E8 /* Dword offset 0_7A */ 267*4882a593Smuzhiyun #define S_Y_INC 0x01EC /* Dword offset 0_7B */ 268*4882a593Smuzhiyun 269*4882a593Smuzhiyun #define SCALE_PITCH 0x01EC /* Dword offset 0_7B */ 270*4882a593Smuzhiyun #define SCALE_X_INC 0x01F0 /* Dword offset 0_7C */ 271*4882a593Smuzhiyun 272*4882a593Smuzhiyun #define RED_X_INC 0x01F0 /* Dword offset 0_7C */ 273*4882a593Smuzhiyun #define GREEN_X_INC 0x01F4 /* Dword offset 0_7D */ 274*4882a593Smuzhiyun 275*4882a593Smuzhiyun #define SCALE_Y_INC 0x01F4 /* Dword offset 0_7D */ 276*4882a593Smuzhiyun #define SCALE_VACC 0x01F8 /* Dword offset 0_7E */ 277*4882a593Smuzhiyun #define SCALE_3D_CNTL 0x01FC /* Dword offset 0_7F */ 278*4882a593Smuzhiyun 279*4882a593Smuzhiyun /* Host Data */ 280*4882a593Smuzhiyun #define HOST_DATA0 0x0200 /* Dword offset 0_80 */ 281*4882a593Smuzhiyun #define HOST_DATA1 0x0204 /* Dword offset 0_81 */ 282*4882a593Smuzhiyun #define HOST_DATA2 0x0208 /* Dword offset 0_82 */ 283*4882a593Smuzhiyun #define HOST_DATA3 0x020C /* Dword offset 0_83 */ 284*4882a593Smuzhiyun #define HOST_DATA4 0x0210 /* Dword offset 0_84 */ 285*4882a593Smuzhiyun #define HOST_DATA5 0x0214 /* Dword offset 0_85 */ 286*4882a593Smuzhiyun #define HOST_DATA6 0x0218 /* Dword offset 0_86 */ 287*4882a593Smuzhiyun #define HOST_DATA7 0x021C /* Dword offset 0_87 */ 288*4882a593Smuzhiyun #define HOST_DATA8 0x0220 /* Dword offset 0_88 */ 289*4882a593Smuzhiyun #define HOST_DATA9 0x0224 /* Dword offset 0_89 */ 290*4882a593Smuzhiyun #define HOST_DATAA 0x0228 /* Dword offset 0_8A */ 291*4882a593Smuzhiyun #define HOST_DATAB 0x022C /* Dword offset 0_8B */ 292*4882a593Smuzhiyun #define HOST_DATAC 0x0230 /* Dword offset 0_8C */ 293*4882a593Smuzhiyun #define HOST_DATAD 0x0234 /* Dword offset 0_8D */ 294*4882a593Smuzhiyun #define HOST_DATAE 0x0238 /* Dword offset 0_8E */ 295*4882a593Smuzhiyun #define HOST_DATAF 0x023C /* Dword offset 0_8F */ 296*4882a593Smuzhiyun #define HOST_CNTL 0x0240 /* Dword offset 0_90 */ 297*4882a593Smuzhiyun 298*4882a593Smuzhiyun /* GUI Bus Mastering */ 299*4882a593Smuzhiyun #define BM_HOSTDATA 0x0244 /* Dword offset 0_91 */ 300*4882a593Smuzhiyun #define BM_ADDR 0x0248 /* Dword offset 0_92 */ 301*4882a593Smuzhiyun #define BM_DATA 0x0248 /* Dword offset 0_92 */ 302*4882a593Smuzhiyun #define BM_GUI_TABLE_CMD 0x024C /* Dword offset 0_93 */ 303*4882a593Smuzhiyun 304*4882a593Smuzhiyun /* Pattern */ 305*4882a593Smuzhiyun #define PAT_REG0 0x0280 /* Dword offset 0_A0 */ 306*4882a593Smuzhiyun #define PAT_REG1 0x0284 /* Dword offset 0_A1 */ 307*4882a593Smuzhiyun #define PAT_CNTL 0x0288 /* Dword offset 0_A2 */ 308*4882a593Smuzhiyun 309*4882a593Smuzhiyun /* Scissors */ 310*4882a593Smuzhiyun #define SC_LEFT 0x02A0 /* Dword offset 0_A8 */ 311*4882a593Smuzhiyun #define SC_RIGHT 0x02A4 /* Dword offset 0_A9 */ 312*4882a593Smuzhiyun #define SC_LEFT_RIGHT 0x02A8 /* Dword offset 0_AA */ 313*4882a593Smuzhiyun #define SC_TOP 0x02AC /* Dword offset 0_AB */ 314*4882a593Smuzhiyun #define SC_BOTTOM 0x02B0 /* Dword offset 0_AC */ 315*4882a593Smuzhiyun #define SC_TOP_BOTTOM 0x02B4 /* Dword offset 0_AD */ 316*4882a593Smuzhiyun 317*4882a593Smuzhiyun /* Data Path */ 318*4882a593Smuzhiyun #define USR1_DST_OFF_PITCH 0x02B8 /* Dword offset 0_AE */ 319*4882a593Smuzhiyun #define USR2_DST_OFF_PITCH 0x02BC /* Dword offset 0_AF */ 320*4882a593Smuzhiyun #define DP_BKGD_CLR 0x02C0 /* Dword offset 0_B0 */ 321*4882a593Smuzhiyun #define DP_FOG_CLR 0x02C4 /* Dword offset 0_B1 */ 322*4882a593Smuzhiyun #define DP_FRGD_CLR 0x02C4 /* Dword offset 0_B1 */ 323*4882a593Smuzhiyun #define DP_WRITE_MASK 0x02C8 /* Dword offset 0_B2 */ 324*4882a593Smuzhiyun #define DP_CHAIN_MASK 0x02CC /* Dword offset 0_B3 */ 325*4882a593Smuzhiyun #define DP_PIX_WIDTH 0x02D0 /* Dword offset 0_B4 */ 326*4882a593Smuzhiyun #define DP_MIX 0x02D4 /* Dword offset 0_B5 */ 327*4882a593Smuzhiyun #define DP_SRC 0x02D8 /* Dword offset 0_B6 */ 328*4882a593Smuzhiyun #define DP_FRGD_CLR_MIX 0x02DC /* Dword offset 0_B7 */ 329*4882a593Smuzhiyun #define DP_FRGD_BKGD_CLR 0x02E0 /* Dword offset 0_B8 */ 330*4882a593Smuzhiyun 331*4882a593Smuzhiyun /* Draw Engine Destination Trajectory */ 332*4882a593Smuzhiyun #define DST_X_Y 0x02E8 /* Dword offset 0_BA */ 333*4882a593Smuzhiyun #define DST_WIDTH_HEIGHT 0x02EC /* Dword offset 0_BB */ 334*4882a593Smuzhiyun 335*4882a593Smuzhiyun /* Data Path */ 336*4882a593Smuzhiyun #define USR_DST_PICTH 0x02F0 /* Dword offset 0_BC */ 337*4882a593Smuzhiyun #define DP_SET_GUI_ENGINE2 0x02F8 /* Dword offset 0_BE */ 338*4882a593Smuzhiyun #define DP_SET_GUI_ENGINE 0x02FC /* Dword offset 0_BF */ 339*4882a593Smuzhiyun 340*4882a593Smuzhiyun /* Color Compare */ 341*4882a593Smuzhiyun #define CLR_CMP_CLR 0x0300 /* Dword offset 0_C0 */ 342*4882a593Smuzhiyun #define CLR_CMP_MASK 0x0304 /* Dword offset 0_C1 */ 343*4882a593Smuzhiyun #define CLR_CMP_CNTL 0x0308 /* Dword offset 0_C2 */ 344*4882a593Smuzhiyun 345*4882a593Smuzhiyun /* Command FIFO */ 346*4882a593Smuzhiyun #define FIFO_STAT 0x0310 /* Dword offset 0_C4 */ 347*4882a593Smuzhiyun 348*4882a593Smuzhiyun #define CONTEXT_MASK 0x0320 /* Dword offset 0_C8 */ 349*4882a593Smuzhiyun #define CONTEXT_LOAD_CNTL 0x032C /* Dword offset 0_CB */ 350*4882a593Smuzhiyun 351*4882a593Smuzhiyun /* Engine Control */ 352*4882a593Smuzhiyun #define GUI_TRAJ_CNTL 0x0330 /* Dword offset 0_CC */ 353*4882a593Smuzhiyun 354*4882a593Smuzhiyun /* Engine Status/FIFO */ 355*4882a593Smuzhiyun #define GUI_STAT 0x0338 /* Dword offset 0_CE */ 356*4882a593Smuzhiyun 357*4882a593Smuzhiyun #define TEX_PALETTE_INDEX 0x0340 /* Dword offset 0_D0 */ 358*4882a593Smuzhiyun #define STW_EXP 0x0344 /* Dword offset 0_D1 */ 359*4882a593Smuzhiyun #define LOG_MAX_INC 0x0348 /* Dword offset 0_D2 */ 360*4882a593Smuzhiyun #define S_X_INC 0x034C /* Dword offset 0_D3 */ 361*4882a593Smuzhiyun #define S_Y_INC__ALIAS__ 0x0350 /* Dword offset 0_D4 */ 362*4882a593Smuzhiyun 363*4882a593Smuzhiyun #define SCALE_PITCH__ALIAS__ 0x0350 /* Dword offset 0_D4 */ 364*4882a593Smuzhiyun 365*4882a593Smuzhiyun #define S_START 0x0354 /* Dword offset 0_D5 */ 366*4882a593Smuzhiyun #define W_X_INC 0x0358 /* Dword offset 0_D6 */ 367*4882a593Smuzhiyun #define W_Y_INC 0x035C /* Dword offset 0_D7 */ 368*4882a593Smuzhiyun #define W_START 0x0360 /* Dword offset 0_D8 */ 369*4882a593Smuzhiyun #define T_X_INC 0x0364 /* Dword offset 0_D9 */ 370*4882a593Smuzhiyun #define T_Y_INC 0x0368 /* Dword offset 0_DA */ 371*4882a593Smuzhiyun 372*4882a593Smuzhiyun #define SECONDARY_SCALE_PITCH 0x0368 /* Dword offset 0_DA */ 373*4882a593Smuzhiyun 374*4882a593Smuzhiyun #define T_START 0x036C /* Dword offset 0_DB */ 375*4882a593Smuzhiyun #define TEX_SIZE_PITCH 0x0370 /* Dword offset 0_DC */ 376*4882a593Smuzhiyun #define TEX_CNTL 0x0374 /* Dword offset 0_DD */ 377*4882a593Smuzhiyun #define SECONDARY_TEX_OFFSET 0x0378 /* Dword offset 0_DE */ 378*4882a593Smuzhiyun #define TEX_PALETTE 0x037C /* Dword offset 0_DF */ 379*4882a593Smuzhiyun 380*4882a593Smuzhiyun #define SCALE_PITCH_BOTH 0x0380 /* Dword offset 0_E0 */ 381*4882a593Smuzhiyun #define SECONDARY_SCALE_OFF_ACC 0x0384 /* Dword offset 0_E1 */ 382*4882a593Smuzhiyun #define SCALE_OFF_ACC 0x0388 /* Dword offset 0_E2 */ 383*4882a593Smuzhiyun #define SCALE_DST_Y_X 0x038C /* Dword offset 0_E3 */ 384*4882a593Smuzhiyun 385*4882a593Smuzhiyun /* Draw Engine Destination Trajectory */ 386*4882a593Smuzhiyun #define COMPOSITE_SHADOW_ID 0x0398 /* Dword offset 0_E6 */ 387*4882a593Smuzhiyun 388*4882a593Smuzhiyun #define SECONDARY_SCALE_X_INC 0x039C /* Dword offset 0_E7 */ 389*4882a593Smuzhiyun 390*4882a593Smuzhiyun #define SPECULAR_RED_X_INC 0x039C /* Dword offset 0_E7 */ 391*4882a593Smuzhiyun #define SPECULAR_RED_Y_INC 0x03A0 /* Dword offset 0_E8 */ 392*4882a593Smuzhiyun #define SPECULAR_RED_START 0x03A4 /* Dword offset 0_E9 */ 393*4882a593Smuzhiyun 394*4882a593Smuzhiyun #define SECONDARY_SCALE_HACC 0x03A4 /* Dword offset 0_E9 */ 395*4882a593Smuzhiyun 396*4882a593Smuzhiyun #define SPECULAR_GREEN_X_INC 0x03A8 /* Dword offset 0_EA */ 397*4882a593Smuzhiyun #define SPECULAR_GREEN_Y_INC 0x03AC /* Dword offset 0_EB */ 398*4882a593Smuzhiyun #define SPECULAR_GREEN_START 0x03B0 /* Dword offset 0_EC */ 399*4882a593Smuzhiyun #define SPECULAR_BLUE_X_INC 0x03B4 /* Dword offset 0_ED */ 400*4882a593Smuzhiyun #define SPECULAR_BLUE_Y_INC 0x03B8 /* Dword offset 0_EE */ 401*4882a593Smuzhiyun #define SPECULAR_BLUE_START 0x03BC /* Dword offset 0_EF */ 402*4882a593Smuzhiyun 403*4882a593Smuzhiyun #define SCALE_X_INC__ALIAS__ 0x03C0 /* Dword offset 0_F0 */ 404*4882a593Smuzhiyun 405*4882a593Smuzhiyun #define RED_X_INC__ALIAS__ 0x03C0 /* Dword offset 0_F0 */ 406*4882a593Smuzhiyun #define RED_Y_INC 0x03C4 /* Dword offset 0_F1 */ 407*4882a593Smuzhiyun #define RED_START 0x03C8 /* Dword offset 0_F2 */ 408*4882a593Smuzhiyun 409*4882a593Smuzhiyun #define SCALE_HACC 0x03C8 /* Dword offset 0_F2 */ 410*4882a593Smuzhiyun #define SCALE_Y_INC__ALIAS__ 0x03CC /* Dword offset 0_F3 */ 411*4882a593Smuzhiyun 412*4882a593Smuzhiyun #define GREEN_X_INC__ALIAS__ 0x03CC /* Dword offset 0_F3 */ 413*4882a593Smuzhiyun #define GREEN_Y_INC 0x03D0 /* Dword offset 0_F4 */ 414*4882a593Smuzhiyun 415*4882a593Smuzhiyun #define SECONDARY_SCALE_Y_INC 0x03D0 /* Dword offset 0_F4 */ 416*4882a593Smuzhiyun #define SECONDARY_SCALE_VACC 0x03D4 /* Dword offset 0_F5 */ 417*4882a593Smuzhiyun 418*4882a593Smuzhiyun #define GREEN_START 0x03D4 /* Dword offset 0_F5 */ 419*4882a593Smuzhiyun #define BLUE_X_INC 0x03D8 /* Dword offset 0_F6 */ 420*4882a593Smuzhiyun #define BLUE_Y_INC 0x03DC /* Dword offset 0_F7 */ 421*4882a593Smuzhiyun #define BLUE_START 0x03E0 /* Dword offset 0_F8 */ 422*4882a593Smuzhiyun #define Z_X_INC 0x03E4 /* Dword offset 0_F9 */ 423*4882a593Smuzhiyun #define Z_Y_INC 0x03E8 /* Dword offset 0_FA */ 424*4882a593Smuzhiyun #define Z_START 0x03EC /* Dword offset 0_FB */ 425*4882a593Smuzhiyun #define ALPHA_X_INC 0x03F0 /* Dword offset 0_FC */ 426*4882a593Smuzhiyun #define FOG_X_INC 0x03F0 /* Dword offset 0_FC */ 427*4882a593Smuzhiyun #define ALPHA_Y_INC 0x03F4 /* Dword offset 0_FD */ 428*4882a593Smuzhiyun #define FOG_Y_INC 0x03F4 /* Dword offset 0_FD */ 429*4882a593Smuzhiyun #define ALPHA_START 0x03F8 /* Dword offset 0_FE */ 430*4882a593Smuzhiyun #define FOG_START 0x03F8 /* Dword offset 0_FE */ 431*4882a593Smuzhiyun 432*4882a593Smuzhiyun #define OVERLAY_Y_X_START 0x0400 /* Dword offset 1_00 */ 433*4882a593Smuzhiyun #define OVERLAY_Y_X_END 0x0404 /* Dword offset 1_01 */ 434*4882a593Smuzhiyun #define OVERLAY_VIDEO_KEY_CLR 0x0408 /* Dword offset 1_02 */ 435*4882a593Smuzhiyun #define OVERLAY_VIDEO_KEY_MSK 0x040C /* Dword offset 1_03 */ 436*4882a593Smuzhiyun #define OVERLAY_GRAPHICS_KEY_CLR 0x0410 /* Dword offset 1_04 */ 437*4882a593Smuzhiyun #define OVERLAY_GRAPHICS_KEY_MSK 0x0414 /* Dword offset 1_05 */ 438*4882a593Smuzhiyun #define OVERLAY_KEY_CNTL 0x0418 /* Dword offset 1_06 */ 439*4882a593Smuzhiyun 440*4882a593Smuzhiyun #define OVERLAY_SCALE_INC 0x0420 /* Dword offset 1_08 */ 441*4882a593Smuzhiyun #define OVERLAY_SCALE_CNTL 0x0424 /* Dword offset 1_09 */ 442*4882a593Smuzhiyun #define SCALER_HEIGHT_WIDTH 0x0428 /* Dword offset 1_0A */ 443*4882a593Smuzhiyun #define SCALER_TEST 0x042C /* Dword offset 1_0B */ 444*4882a593Smuzhiyun #define SCALER_BUF0_OFFSET 0x0434 /* Dword offset 1_0D */ 445*4882a593Smuzhiyun #define SCALER_BUF1_OFFSET 0x0438 /* Dword offset 1_0E */ 446*4882a593Smuzhiyun #define SCALE_BUF_PITCH 0x043C /* Dword offset 1_0F */ 447*4882a593Smuzhiyun 448*4882a593Smuzhiyun #define CAPTURE_START_END 0x0440 /* Dword offset 1_10 */ 449*4882a593Smuzhiyun #define CAPTURE_X_WIDTH 0x0444 /* Dword offset 1_11 */ 450*4882a593Smuzhiyun #define VIDEO_FORMAT 0x0448 /* Dword offset 1_12 */ 451*4882a593Smuzhiyun #define VBI_START_END 0x044C /* Dword offset 1_13 */ 452*4882a593Smuzhiyun #define CAPTURE_CONFIG 0x0450 /* Dword offset 1_14 */ 453*4882a593Smuzhiyun #define TRIG_CNTL 0x0454 /* Dword offset 1_15 */ 454*4882a593Smuzhiyun 455*4882a593Smuzhiyun #define OVERLAY_EXCLUSIVE_HORZ 0x0458 /* Dword offset 1_16 */ 456*4882a593Smuzhiyun #define OVERLAY_EXCLUSIVE_VERT 0x045C /* Dword offset 1_17 */ 457*4882a593Smuzhiyun 458*4882a593Smuzhiyun #define VAL_WIDTH 0x0460 /* Dword offset 1_18 */ 459*4882a593Smuzhiyun #define CAPTURE_DEBUG 0x0464 /* Dword offset 1_19 */ 460*4882a593Smuzhiyun #define VIDEO_SYNC_TEST 0x0468 /* Dword offset 1_1A */ 461*4882a593Smuzhiyun 462*4882a593Smuzhiyun /* GenLocking */ 463*4882a593Smuzhiyun #define SNAPSHOT_VH_COUNTS 0x0470 /* Dword offset 1_1C */ 464*4882a593Smuzhiyun #define SNAPSHOT_F_COUNT 0x0474 /* Dword offset 1_1D */ 465*4882a593Smuzhiyun #define N_VIF_COUNT 0x0478 /* Dword offset 1_1E */ 466*4882a593Smuzhiyun #define SNAPSHOT_VIF_COUNT 0x047C /* Dword offset 1_1F */ 467*4882a593Smuzhiyun 468*4882a593Smuzhiyun #define CAPTURE_BUF0_OFFSET 0x0480 /* Dword offset 1_20 */ 469*4882a593Smuzhiyun #define CAPTURE_BUF1_OFFSET 0x0484 /* Dword offset 1_21 */ 470*4882a593Smuzhiyun #define CAPTURE_BUF_PITCH 0x0488 /* Dword offset 1_22 */ 471*4882a593Smuzhiyun 472*4882a593Smuzhiyun /* GenLocking */ 473*4882a593Smuzhiyun #define SNAPSHOT2_VH_COUNTS 0x04B0 /* Dword offset 1_2C */ 474*4882a593Smuzhiyun #define SNAPSHOT2_F_COUNT 0x04B4 /* Dword offset 1_2D */ 475*4882a593Smuzhiyun #define N_VIF2_COUNT 0x04B8 /* Dword offset 1_2E */ 476*4882a593Smuzhiyun #define SNAPSHOT2_VIF_COUNT 0x04BC /* Dword offset 1_2F */ 477*4882a593Smuzhiyun 478*4882a593Smuzhiyun #define MPP_CONFIG 0x04C0 /* Dword offset 1_30 */ 479*4882a593Smuzhiyun #define MPP_STROBE_SEQ 0x04C4 /* Dword offset 1_31 */ 480*4882a593Smuzhiyun #define MPP_ADDR 0x04C8 /* Dword offset 1_32 */ 481*4882a593Smuzhiyun #define MPP_DATA 0x04CC /* Dword offset 1_33 */ 482*4882a593Smuzhiyun #define TVO_CNTL 0x0500 /* Dword offset 1_40 */ 483*4882a593Smuzhiyun 484*4882a593Smuzhiyun /* Test and Debug */ 485*4882a593Smuzhiyun #define CRT_HORZ_VERT_LOAD 0x0544 /* Dword offset 1_51 */ 486*4882a593Smuzhiyun 487*4882a593Smuzhiyun /* AGP */ 488*4882a593Smuzhiyun #define AGP_BASE 0x0548 /* Dword offset 1_52 */ 489*4882a593Smuzhiyun #define AGP_CNTL 0x054C /* Dword offset 1_53 */ 490*4882a593Smuzhiyun 491*4882a593Smuzhiyun #define SCALER_COLOUR_CNTL 0x0550 /* Dword offset 1_54 */ 492*4882a593Smuzhiyun #define SCALER_H_COEFF0 0x0554 /* Dword offset 1_55 */ 493*4882a593Smuzhiyun #define SCALER_H_COEFF1 0x0558 /* Dword offset 1_56 */ 494*4882a593Smuzhiyun #define SCALER_H_COEFF2 0x055C /* Dword offset 1_57 */ 495*4882a593Smuzhiyun #define SCALER_H_COEFF3 0x0560 /* Dword offset 1_58 */ 496*4882a593Smuzhiyun #define SCALER_H_COEFF4 0x0564 /* Dword offset 1_59 */ 497*4882a593Smuzhiyun 498*4882a593Smuzhiyun /* Command FIFO */ 499*4882a593Smuzhiyun #define GUI_CMDFIFO_DEBUG 0x0570 /* Dword offset 1_5C */ 500*4882a593Smuzhiyun #define GUI_CMDFIFO_DATA 0x0574 /* Dword offset 1_5D */ 501*4882a593Smuzhiyun #define GUI_CNTL 0x0578 /* Dword offset 1_5E */ 502*4882a593Smuzhiyun 503*4882a593Smuzhiyun /* Bus Mastering */ 504*4882a593Smuzhiyun #define BM_FRAME_BUF_OFFSET 0x0580 /* Dword offset 1_60 */ 505*4882a593Smuzhiyun #define BM_SYSTEM_MEM_ADDR 0x0584 /* Dword offset 1_61 */ 506*4882a593Smuzhiyun #define BM_COMMAND 0x0588 /* Dword offset 1_62 */ 507*4882a593Smuzhiyun #define BM_STATUS 0x058C /* Dword offset 1_63 */ 508*4882a593Smuzhiyun #define BM_GUI_TABLE 0x05B8 /* Dword offset 1_6E */ 509*4882a593Smuzhiyun #define BM_SYSTEM_TABLE 0x05BC /* Dword offset 1_6F */ 510*4882a593Smuzhiyun 511*4882a593Smuzhiyun #define SCALER_BUF0_OFFSET_U 0x05D4 /* Dword offset 1_75 */ 512*4882a593Smuzhiyun #define SCALER_BUF0_OFFSET_V 0x05D8 /* Dword offset 1_76 */ 513*4882a593Smuzhiyun #define SCALER_BUF1_OFFSET_U 0x05DC /* Dword offset 1_77 */ 514*4882a593Smuzhiyun #define SCALER_BUF1_OFFSET_V 0x05E0 /* Dword offset 1_78 */ 515*4882a593Smuzhiyun 516*4882a593Smuzhiyun /* Setup Engine */ 517*4882a593Smuzhiyun #define VERTEX_1_S 0x0640 /* Dword offset 1_90 */ 518*4882a593Smuzhiyun #define VERTEX_1_T 0x0644 /* Dword offset 1_91 */ 519*4882a593Smuzhiyun #define VERTEX_1_W 0x0648 /* Dword offset 1_92 */ 520*4882a593Smuzhiyun #define VERTEX_1_SPEC_ARGB 0x064C /* Dword offset 1_93 */ 521*4882a593Smuzhiyun #define VERTEX_1_Z 0x0650 /* Dword offset 1_94 */ 522*4882a593Smuzhiyun #define VERTEX_1_ARGB 0x0654 /* Dword offset 1_95 */ 523*4882a593Smuzhiyun #define VERTEX_1_X_Y 0x0658 /* Dword offset 1_96 */ 524*4882a593Smuzhiyun #define ONE_OVER_AREA 0x065C /* Dword offset 1_97 */ 525*4882a593Smuzhiyun #define VERTEX_2_S 0x0660 /* Dword offset 1_98 */ 526*4882a593Smuzhiyun #define VERTEX_2_T 0x0664 /* Dword offset 1_99 */ 527*4882a593Smuzhiyun #define VERTEX_2_W 0x0668 /* Dword offset 1_9A */ 528*4882a593Smuzhiyun #define VERTEX_2_SPEC_ARGB 0x066C /* Dword offset 1_9B */ 529*4882a593Smuzhiyun #define VERTEX_2_Z 0x0670 /* Dword offset 1_9C */ 530*4882a593Smuzhiyun #define VERTEX_2_ARGB 0x0674 /* Dword offset 1_9D */ 531*4882a593Smuzhiyun #define VERTEX_2_X_Y 0x0678 /* Dword offset 1_9E */ 532*4882a593Smuzhiyun #define ONE_OVER_AREA 0x065C /* Dword offset 1_9F */ 533*4882a593Smuzhiyun #define VERTEX_3_S 0x0680 /* Dword offset 1_A0 */ 534*4882a593Smuzhiyun #define VERTEX_3_T 0x0684 /* Dword offset 1_A1 */ 535*4882a593Smuzhiyun #define VERTEX_3_W 0x0688 /* Dword offset 1_A2 */ 536*4882a593Smuzhiyun #define VERTEX_3_SPEC_ARGB 0x068C /* Dword offset 1_A3 */ 537*4882a593Smuzhiyun #define VERTEX_3_Z 0x0690 /* Dword offset 1_A4 */ 538*4882a593Smuzhiyun #define VERTEX_3_ARGB 0x0694 /* Dword offset 1_A5 */ 539*4882a593Smuzhiyun #define VERTEX_3_X_Y 0x0698 /* Dword offset 1_A6 */ 540*4882a593Smuzhiyun #define ONE_OVER_AREA 0x065C /* Dword offset 1_A7 */ 541*4882a593Smuzhiyun #define VERTEX_1_S 0x0640 /* Dword offset 1_AB */ 542*4882a593Smuzhiyun #define VERTEX_1_T 0x0644 /* Dword offset 1_AC */ 543*4882a593Smuzhiyun #define VERTEX_1_W 0x0648 /* Dword offset 1_AD */ 544*4882a593Smuzhiyun #define VERTEX_2_S 0x0660 /* Dword offset 1_AE */ 545*4882a593Smuzhiyun #define VERTEX_2_T 0x0664 /* Dword offset 1_AF */ 546*4882a593Smuzhiyun #define VERTEX_2_W 0x0668 /* Dword offset 1_B0 */ 547*4882a593Smuzhiyun #define VERTEX_3_SECONDARY_S 0x06C0 /* Dword offset 1_B0 */ 548*4882a593Smuzhiyun #define VERTEX_3_S 0x0680 /* Dword offset 1_B1 */ 549*4882a593Smuzhiyun #define VERTEX_3_SECONDARY_T 0x06C4 /* Dword offset 1_B1 */ 550*4882a593Smuzhiyun #define VERTEX_3_T 0x0684 /* Dword offset 1_B2 */ 551*4882a593Smuzhiyun #define VERTEX_3_SECONDARY_W 0x06C8 /* Dword offset 1_B2 */ 552*4882a593Smuzhiyun #define VERTEX_3_W 0x0688 /* Dword offset 1_B3 */ 553*4882a593Smuzhiyun #define VERTEX_1_SPEC_ARGB 0x064C /* Dword offset 1_B4 */ 554*4882a593Smuzhiyun #define VERTEX_2_SPEC_ARGB 0x066C /* Dword offset 1_B5 */ 555*4882a593Smuzhiyun #define VERTEX_3_SPEC_ARGB 0x068C /* Dword offset 1_B6 */ 556*4882a593Smuzhiyun #define VERTEX_1_Z 0x0650 /* Dword offset 1_B7 */ 557*4882a593Smuzhiyun #define VERTEX_2_Z 0x0670 /* Dword offset 1_B8 */ 558*4882a593Smuzhiyun #define VERTEX_3_Z 0x0690 /* Dword offset 1_B9 */ 559*4882a593Smuzhiyun #define VERTEX_1_ARGB 0x0654 /* Dword offset 1_BA */ 560*4882a593Smuzhiyun #define VERTEX_2_ARGB 0x0674 /* Dword offset 1_BB */ 561*4882a593Smuzhiyun #define VERTEX_3_ARGB 0x0694 /* Dword offset 1_BC */ 562*4882a593Smuzhiyun #define VERTEX_1_X_Y 0x0658 /* Dword offset 1_BD */ 563*4882a593Smuzhiyun #define VERTEX_2_X_Y 0x0678 /* Dword offset 1_BE */ 564*4882a593Smuzhiyun #define VERTEX_3_X_Y 0x0698 /* Dword offset 1_BF */ 565*4882a593Smuzhiyun #define ONE_OVER_AREA_UC 0x0700 /* Dword offset 1_C0 */ 566*4882a593Smuzhiyun #define SETUP_CNTL 0x0704 /* Dword offset 1_C1 */ 567*4882a593Smuzhiyun #define VERTEX_1_SECONDARY_S 0x0728 /* Dword offset 1_CA */ 568*4882a593Smuzhiyun #define VERTEX_1_SECONDARY_T 0x072C /* Dword offset 1_CB */ 569*4882a593Smuzhiyun #define VERTEX_1_SECONDARY_W 0x0730 /* Dword offset 1_CC */ 570*4882a593Smuzhiyun #define VERTEX_2_SECONDARY_S 0x0734 /* Dword offset 1_CD */ 571*4882a593Smuzhiyun #define VERTEX_2_SECONDARY_T 0x0738 /* Dword offset 1_CE */ 572*4882a593Smuzhiyun #define VERTEX_2_SECONDARY_W 0x073C /* Dword offset 1_CF */ 573*4882a593Smuzhiyun 574*4882a593Smuzhiyun 575*4882a593Smuzhiyun #define GTC_3D_RESET_DELAY 3 /* 3D engine reset delay in ms */ 576*4882a593Smuzhiyun 577*4882a593Smuzhiyun /* CRTC control values (mostly CRTC_GEN_CNTL) */ 578*4882a593Smuzhiyun 579*4882a593Smuzhiyun #define CRTC_H_SYNC_NEG 0x00200000 580*4882a593Smuzhiyun #define CRTC_V_SYNC_NEG 0x00200000 581*4882a593Smuzhiyun 582*4882a593Smuzhiyun #define CRTC_DBL_SCAN_EN 0x00000001 583*4882a593Smuzhiyun #define CRTC_INTERLACE_EN 0x00000002 584*4882a593Smuzhiyun #define CRTC_HSYNC_DIS 0x00000004 585*4882a593Smuzhiyun #define CRTC_VSYNC_DIS 0x00000008 586*4882a593Smuzhiyun #define CRTC_CSYNC_EN 0x00000010 587*4882a593Smuzhiyun #define CRTC_PIX_BY_2_EN 0x00000020 /* unused on RAGE */ 588*4882a593Smuzhiyun #define CRTC_DISPLAY_DIS 0x00000040 589*4882a593Smuzhiyun #define CRTC_VGA_XOVERSCAN 0x00000080 590*4882a593Smuzhiyun 591*4882a593Smuzhiyun #define CRTC_PIX_WIDTH_MASK 0x00000700 592*4882a593Smuzhiyun #define CRTC_PIX_WIDTH_4BPP 0x00000100 593*4882a593Smuzhiyun #define CRTC_PIX_WIDTH_8BPP 0x00000200 594*4882a593Smuzhiyun #define CRTC_PIX_WIDTH_15BPP 0x00000300 595*4882a593Smuzhiyun #define CRTC_PIX_WIDTH_16BPP 0x00000400 596*4882a593Smuzhiyun #define CRTC_PIX_WIDTH_24BPP 0x00000500 597*4882a593Smuzhiyun #define CRTC_PIX_WIDTH_32BPP 0x00000600 598*4882a593Smuzhiyun 599*4882a593Smuzhiyun #define CRTC_BYTE_PIX_ORDER 0x00000800 600*4882a593Smuzhiyun #define CRTC_PIX_ORDER_MSN_LSN 0x00000000 601*4882a593Smuzhiyun #define CRTC_PIX_ORDER_LSN_MSN 0x00000800 602*4882a593Smuzhiyun 603*4882a593Smuzhiyun #define CRTC_VSYNC_INT_EN 0x00001000ul /* XC/XL */ 604*4882a593Smuzhiyun #define CRTC_VSYNC_INT 0x00002000ul /* XC/XL */ 605*4882a593Smuzhiyun #define CRTC_FIFO_OVERFILL 0x0000c000ul /* VT/GT */ 606*4882a593Smuzhiyun #define CRTC2_VSYNC_INT_EN 0x00004000ul /* XC/XL */ 607*4882a593Smuzhiyun #define CRTC2_VSYNC_INT 0x00008000ul /* XC/XL */ 608*4882a593Smuzhiyun 609*4882a593Smuzhiyun #define CRTC_FIFO_LWM 0x000f0000 610*4882a593Smuzhiyun #define CRTC_HVSYNC_IO_DRIVE 0x00010000 /* XC/XL */ 611*4882a593Smuzhiyun #define CRTC2_PIX_WIDTH 0x000e0000 /* LTPro */ 612*4882a593Smuzhiyun 613*4882a593Smuzhiyun #define CRTC_VGA_128KAP_PAGING 0x00100000 614*4882a593Smuzhiyun #define CRTC_VFC_SYNC_TRISTATE 0x00200000 /* VTB/GTB/LT */ 615*4882a593Smuzhiyun #define CRTC2_EN 0x00200000 /* LTPro */ 616*4882a593Smuzhiyun #define CRTC_LOCK_REGS 0x00400000 617*4882a593Smuzhiyun #define CRTC_SYNC_TRISTATE 0x00800000 618*4882a593Smuzhiyun 619*4882a593Smuzhiyun #define CRTC_EXT_DISP_EN 0x01000000 620*4882a593Smuzhiyun #define CRTC_EN 0x02000000 621*4882a593Smuzhiyun #define CRTC_DISP_REQ_EN 0x04000000 622*4882a593Smuzhiyun #define CRTC_VGA_LINEAR 0x08000000 623*4882a593Smuzhiyun #define CRTC_VSYNC_FALL_EDGE 0x10000000 624*4882a593Smuzhiyun #define CRTC_VGA_TEXT_132 0x20000000 625*4882a593Smuzhiyun #define CRTC_CNT_EN 0x40000000 626*4882a593Smuzhiyun #define CRTC_CUR_B_TEST 0x80000000 627*4882a593Smuzhiyun 628*4882a593Smuzhiyun #define CRTC_CRNT_VLINE 0x07f00000 629*4882a593Smuzhiyun 630*4882a593Smuzhiyun #define CRTC_PRESERVED_MASK 0x0001f000 631*4882a593Smuzhiyun 632*4882a593Smuzhiyun #define CRTC_VBLANK 0x00000001 633*4882a593Smuzhiyun #define CRTC_VBLANK_INT_EN 0x00000002 634*4882a593Smuzhiyun #define CRTC_VBLANK_INT 0x00000004 635*4882a593Smuzhiyun #define CRTC_VBLANK_INT_AK CRTC_VBLANK_INT 636*4882a593Smuzhiyun #define CRTC_VLINE_INT_EN 0x00000008 637*4882a593Smuzhiyun #define CRTC_VLINE_INT 0x00000010 638*4882a593Smuzhiyun #define CRTC_VLINE_INT_AK CRTC_VLINE_INT 639*4882a593Smuzhiyun #define CRTC_VLINE_SYNC 0x00000020 640*4882a593Smuzhiyun #define CRTC_FRAME 0x00000040 641*4882a593Smuzhiyun #define SNAPSHOT_INT_EN 0x00000080 642*4882a593Smuzhiyun #define SNAPSHOT_INT 0x00000100 643*4882a593Smuzhiyun #define SNAPSHOT_INT_AK SNAPSHOT_INT 644*4882a593Smuzhiyun #define I2C_INT_EN 0x00000200 645*4882a593Smuzhiyun #define I2C_INT 0x00000400 646*4882a593Smuzhiyun #define I2C_INT_AK I2C_INT 647*4882a593Smuzhiyun #define CRTC2_VBLANK 0x00000800 648*4882a593Smuzhiyun #define CRTC2_VBLANK_INT_EN 0x00001000 649*4882a593Smuzhiyun #define CRTC2_VBLANK_INT 0x00002000 650*4882a593Smuzhiyun #define CRTC2_VBLANK_INT_AK CRTC2_VBLANK_INT 651*4882a593Smuzhiyun #define CRTC2_VLINE_INT_EN 0x00004000 652*4882a593Smuzhiyun #define CRTC2_VLINE_INT 0x00008000 653*4882a593Smuzhiyun #define CRTC2_VLINE_INT_AK CRTC2_VLINE_INT 654*4882a593Smuzhiyun #define CAPBUF0_INT_EN 0x00010000 655*4882a593Smuzhiyun #define CAPBUF0_INT 0x00020000 656*4882a593Smuzhiyun #define CAPBUF0_INT_AK CAPBUF0_INT 657*4882a593Smuzhiyun #define CAPBUF1_INT_EN 0x00040000 658*4882a593Smuzhiyun #define CAPBUF1_INT 0x00080000 659*4882a593Smuzhiyun #define CAPBUF1_INT_AK CAPBUF1_INT 660*4882a593Smuzhiyun #define OVERLAY_EOF_INT_EN 0x00100000 661*4882a593Smuzhiyun #define OVERLAY_EOF_INT 0x00200000 662*4882a593Smuzhiyun #define OVERLAY_EOF_INT_AK OVERLAY_EOF_INT 663*4882a593Smuzhiyun #define ONESHOT_CAP_INT_EN 0x00400000 664*4882a593Smuzhiyun #define ONESHOT_CAP_INT 0x00800000 665*4882a593Smuzhiyun #define ONESHOT_CAP_INT_AK ONESHOT_CAP_INT 666*4882a593Smuzhiyun #define BUSMASTER_EOL_INT_EN 0x01000000 667*4882a593Smuzhiyun #define BUSMASTER_EOL_INT 0x02000000 668*4882a593Smuzhiyun #define BUSMASTER_EOL_INT_AK BUSMASTER_EOL_INT 669*4882a593Smuzhiyun #define GP_INT_EN 0x04000000 670*4882a593Smuzhiyun #define GP_INT 0x08000000 671*4882a593Smuzhiyun #define GP_INT_AK GP_INT 672*4882a593Smuzhiyun #define CRTC2_VLINE_SYNC 0x10000000 673*4882a593Smuzhiyun #define SNAPSHOT2_INT_EN 0x20000000 674*4882a593Smuzhiyun #define SNAPSHOT2_INT 0x40000000 675*4882a593Smuzhiyun #define SNAPSHOT2_INT_AK SNAPSHOT2_INT 676*4882a593Smuzhiyun #define VBLANK_BIT2_INT 0x80000000 677*4882a593Smuzhiyun #define VBLANK_BIT2_INT_AK VBLANK_BIT2_INT 678*4882a593Smuzhiyun 679*4882a593Smuzhiyun #define CRTC_INT_EN_MASK (CRTC_VBLANK_INT_EN | \ 680*4882a593Smuzhiyun CRTC_VLINE_INT_EN | \ 681*4882a593Smuzhiyun SNAPSHOT_INT_EN | \ 682*4882a593Smuzhiyun I2C_INT_EN | \ 683*4882a593Smuzhiyun CRTC2_VBLANK_INT_EN | \ 684*4882a593Smuzhiyun CRTC2_VLINE_INT_EN | \ 685*4882a593Smuzhiyun CAPBUF0_INT_EN | \ 686*4882a593Smuzhiyun CAPBUF1_INT_EN | \ 687*4882a593Smuzhiyun OVERLAY_EOF_INT_EN | \ 688*4882a593Smuzhiyun ONESHOT_CAP_INT_EN | \ 689*4882a593Smuzhiyun BUSMASTER_EOL_INT_EN | \ 690*4882a593Smuzhiyun GP_INT_EN | \ 691*4882a593Smuzhiyun SNAPSHOT2_INT_EN) 692*4882a593Smuzhiyun 693*4882a593Smuzhiyun /* DAC control values */ 694*4882a593Smuzhiyun 695*4882a593Smuzhiyun #define DAC_EXT_SEL_RS2 0x01 696*4882a593Smuzhiyun #define DAC_EXT_SEL_RS3 0x02 697*4882a593Smuzhiyun #define DAC_8BIT_EN 0x00000100 698*4882a593Smuzhiyun #define DAC_PIX_DLY_MASK 0x00000600 699*4882a593Smuzhiyun #define DAC_PIX_DLY_0NS 0x00000000 700*4882a593Smuzhiyun #define DAC_PIX_DLY_2NS 0x00000200 701*4882a593Smuzhiyun #define DAC_PIX_DLY_4NS 0x00000400 702*4882a593Smuzhiyun #define DAC_BLANK_ADJ_MASK 0x00001800 703*4882a593Smuzhiyun #define DAC_BLANK_ADJ_0 0x00000000 704*4882a593Smuzhiyun #define DAC_BLANK_ADJ_1 0x00000800 705*4882a593Smuzhiyun #define DAC_BLANK_ADJ_2 0x00001000 706*4882a593Smuzhiyun 707*4882a593Smuzhiyun /* DAC control values (my source XL/XC Register reference) */ 708*4882a593Smuzhiyun #define DAC_OUTPUT_MASK 0x00000001 /* 0 - PAL, 1 - NTSC */ 709*4882a593Smuzhiyun #define DAC_MISTERY_BIT 0x00000002 /* PS2 ? RS343 ?, EXTRA_BRIGHT for GT */ 710*4882a593Smuzhiyun #define DAC_BLANKING 0x00000004 711*4882a593Smuzhiyun #define DAC_CMP_DISABLE 0x00000008 712*4882a593Smuzhiyun #define DAC1_CLK_SEL 0x00000010 713*4882a593Smuzhiyun #define PALETTE_ACCESS_CNTL 0x00000020 714*4882a593Smuzhiyun #define PALETTE2_SNOOP_EN 0x00000040 715*4882a593Smuzhiyun #define DAC_CMP_OUTPUT 0x00000080 /* read only */ 716*4882a593Smuzhiyun /* #define DAC_8BIT_EN is ok */ 717*4882a593Smuzhiyun #define CRT_SENSE 0x00000800 /* read only */ 718*4882a593Smuzhiyun #define CRT_DETECTION_ON 0x00001000 719*4882a593Smuzhiyun #define DAC_VGA_ADR_EN 0x00002000 720*4882a593Smuzhiyun #define DAC_FEA_CON_EN 0x00004000 721*4882a593Smuzhiyun #define DAC_PDWN 0x00008000 722*4882a593Smuzhiyun #define DAC_TYPE_MASK 0x00070000 /* read only */ 723*4882a593Smuzhiyun 724*4882a593Smuzhiyun 725*4882a593Smuzhiyun 726*4882a593Smuzhiyun /* Mix control values */ 727*4882a593Smuzhiyun 728*4882a593Smuzhiyun #define MIX_NOT_DST 0x0000 729*4882a593Smuzhiyun #define MIX_0 0x0001 730*4882a593Smuzhiyun #define MIX_1 0x0002 731*4882a593Smuzhiyun #define MIX_DST 0x0003 732*4882a593Smuzhiyun #define MIX_NOT_SRC 0x0004 733*4882a593Smuzhiyun #define MIX_XOR 0x0005 734*4882a593Smuzhiyun #define MIX_XNOR 0x0006 735*4882a593Smuzhiyun #define MIX_SRC 0x0007 736*4882a593Smuzhiyun #define MIX_NAND 0x0008 737*4882a593Smuzhiyun #define MIX_NOT_SRC_OR_DST 0x0009 738*4882a593Smuzhiyun #define MIX_SRC_OR_NOT_DST 0x000a 739*4882a593Smuzhiyun #define MIX_OR 0x000b 740*4882a593Smuzhiyun #define MIX_AND 0x000c 741*4882a593Smuzhiyun #define MIX_SRC_AND_NOT_DST 0x000d 742*4882a593Smuzhiyun #define MIX_NOT_SRC_AND_DST 0x000e 743*4882a593Smuzhiyun #define MIX_NOR 0x000f 744*4882a593Smuzhiyun 745*4882a593Smuzhiyun /* Maximum engine dimensions */ 746*4882a593Smuzhiyun #define ENGINE_MIN_X 0 747*4882a593Smuzhiyun #define ENGINE_MIN_Y 0 748*4882a593Smuzhiyun #define ENGINE_MAX_X 4095 749*4882a593Smuzhiyun #define ENGINE_MAX_Y 16383 750*4882a593Smuzhiyun 751*4882a593Smuzhiyun /* Mach64 engine bit constants - these are typically ORed together */ 752*4882a593Smuzhiyun 753*4882a593Smuzhiyun /* BUS_CNTL register constants */ 754*4882a593Smuzhiyun #define BUS_APER_REG_DIS 0x00000010 755*4882a593Smuzhiyun #define BUS_FIFO_ERR_ACK 0x00200000 756*4882a593Smuzhiyun #define BUS_HOST_ERR_ACK 0x00800000 757*4882a593Smuzhiyun 758*4882a593Smuzhiyun /* GEN_TEST_CNTL register constants */ 759*4882a593Smuzhiyun #define GEN_OVR_OUTPUT_EN 0x20 760*4882a593Smuzhiyun #define HWCURSOR_ENABLE 0x80 761*4882a593Smuzhiyun #define GUI_ENGINE_ENABLE 0x100 762*4882a593Smuzhiyun #define BLOCK_WRITE_ENABLE 0x200 763*4882a593Smuzhiyun 764*4882a593Smuzhiyun /* DSP_CONFIG register constants */ 765*4882a593Smuzhiyun #define DSP_XCLKS_PER_QW 0x00003fff 766*4882a593Smuzhiyun #define DSP_LOOP_LATENCY 0x000f0000 767*4882a593Smuzhiyun #define DSP_PRECISION 0x00700000 768*4882a593Smuzhiyun 769*4882a593Smuzhiyun /* DSP_ON_OFF register constants */ 770*4882a593Smuzhiyun #define DSP_OFF 0x000007ff 771*4882a593Smuzhiyun #define DSP_ON 0x07ff0000 772*4882a593Smuzhiyun #define VGA_DSP_OFF DSP_OFF 773*4882a593Smuzhiyun #define VGA_DSP_ON DSP_ON 774*4882a593Smuzhiyun #define VGA_DSP_XCLKS_PER_QW DSP_XCLKS_PER_QW 775*4882a593Smuzhiyun 776*4882a593Smuzhiyun /* PLL register indices and fields */ 777*4882a593Smuzhiyun #define MPLL_CNTL 0x00 778*4882a593Smuzhiyun #define PLL_PC_GAIN 0x07 779*4882a593Smuzhiyun #define PLL_VC_GAIN 0x18 780*4882a593Smuzhiyun #define PLL_DUTY_CYC 0xE0 781*4882a593Smuzhiyun #define VPLL_CNTL 0x01 782*4882a593Smuzhiyun #define PLL_REF_DIV 0x02 783*4882a593Smuzhiyun #define PLL_GEN_CNTL 0x03 784*4882a593Smuzhiyun #define PLL_OVERRIDE 0x01 /* PLL_SLEEP */ 785*4882a593Smuzhiyun #define PLL_MCLK_RST 0x02 /* PLL_MRESET */ 786*4882a593Smuzhiyun #define OSC_EN 0x04 787*4882a593Smuzhiyun #define EXT_CLK_EN 0x08 788*4882a593Smuzhiyun #define FORCE_DCLK_TRI_STATE 0x08 /* VT4 -> */ 789*4882a593Smuzhiyun #define MCLK_SRC_SEL 0x70 790*4882a593Smuzhiyun #define EXT_CLK_CNTL 0x80 791*4882a593Smuzhiyun #define DLL_PWDN 0x80 /* VT4 -> */ 792*4882a593Smuzhiyun #define MCLK_FB_DIV 0x04 793*4882a593Smuzhiyun #define PLL_VCLK_CNTL 0x05 794*4882a593Smuzhiyun #define PLL_VCLK_SRC_SEL 0x03 795*4882a593Smuzhiyun #define PLL_VCLK_RST 0x04 796*4882a593Smuzhiyun #define PLL_VCLK_INVERT 0x08 797*4882a593Smuzhiyun #define VCLK_POST_DIV 0x06 798*4882a593Smuzhiyun #define VCLK0_POST 0x03 799*4882a593Smuzhiyun #define VCLK1_POST 0x0C 800*4882a593Smuzhiyun #define VCLK2_POST 0x30 801*4882a593Smuzhiyun #define VCLK3_POST 0xC0 802*4882a593Smuzhiyun #define VCLK0_FB_DIV 0x07 803*4882a593Smuzhiyun #define VCLK1_FB_DIV 0x08 804*4882a593Smuzhiyun #define VCLK2_FB_DIV 0x09 805*4882a593Smuzhiyun #define VCLK3_FB_DIV 0x0A 806*4882a593Smuzhiyun #define PLL_EXT_CNTL 0x0B 807*4882a593Smuzhiyun #define PLL_XCLK_MCLK_RATIO 0x03 808*4882a593Smuzhiyun #define PLL_XCLK_SRC_SEL 0x07 809*4882a593Smuzhiyun #define PLL_MFB_TIMES_4_2B 0x08 810*4882a593Smuzhiyun #define PLL_VCLK0_XDIV 0x10 811*4882a593Smuzhiyun #define PLL_VCLK1_XDIV 0x20 812*4882a593Smuzhiyun #define PLL_VCLK2_XDIV 0x40 813*4882a593Smuzhiyun #define PLL_VCLK3_XDIV 0x80 814*4882a593Smuzhiyun #define DLL_CNTL 0x0C 815*4882a593Smuzhiyun #define DLL1_CNTL 0x0C 816*4882a593Smuzhiyun #define VFC_CNTL 0x0D 817*4882a593Smuzhiyun #define PLL_TEST_CNTL 0x0E 818*4882a593Smuzhiyun #define PLL_TEST_COUNT 0x0F 819*4882a593Smuzhiyun #define LVDS_CNTL0 0x10 820*4882a593Smuzhiyun #define LVDS_CNTL1 0x11 821*4882a593Smuzhiyun #define AGP1_CNTL 0x12 822*4882a593Smuzhiyun #define AGP2_CNTL 0x13 823*4882a593Smuzhiyun #define DLL2_CNTL 0x14 824*4882a593Smuzhiyun #define SCLK_FB_DIV 0x15 825*4882a593Smuzhiyun #define SPLL_CNTL1 0x16 826*4882a593Smuzhiyun #define SPLL_CNTL2 0x17 827*4882a593Smuzhiyun #define APLL_STRAPS 0x18 828*4882a593Smuzhiyun #define EXT_VPLL_CNTL 0x19 829*4882a593Smuzhiyun #define EXT_VPLL_EN 0x04 830*4882a593Smuzhiyun #define EXT_VPLL_VGA_EN 0x08 831*4882a593Smuzhiyun #define EXT_VPLL_INSYNC 0x10 832*4882a593Smuzhiyun #define EXT_VPLL_REF_DIV 0x1A 833*4882a593Smuzhiyun #define EXT_VPLL_FB_DIV 0x1B 834*4882a593Smuzhiyun #define EXT_VPLL_MSB 0x1C 835*4882a593Smuzhiyun #define HTOTAL_CNTL 0x1D 836*4882a593Smuzhiyun #define BYTE_CLK_CNTL 0x1E 837*4882a593Smuzhiyun #define TV_PLL_CNTL1 0x1F 838*4882a593Smuzhiyun #define TV_PLL_CNTL2 0x20 839*4882a593Smuzhiyun #define TV_PLL_CNTL 0x21 840*4882a593Smuzhiyun #define EXT_TV_PLL 0x22 841*4882a593Smuzhiyun #define V2PLL_CNTL 0x23 842*4882a593Smuzhiyun #define PLL_V2CLK_CNTL 0x24 843*4882a593Smuzhiyun #define EXT_V2PLL_REF_DIV 0x25 844*4882a593Smuzhiyun #define EXT_V2PLL_FB_DIV 0x26 845*4882a593Smuzhiyun #define EXT_V2PLL_MSB 0x27 846*4882a593Smuzhiyun #define HTOTAL2_CNTL 0x28 847*4882a593Smuzhiyun #define PLL_YCLK_CNTL 0x29 848*4882a593Smuzhiyun #define PM_DYN_CLK_CNTL 0x2A 849*4882a593Smuzhiyun 850*4882a593Smuzhiyun /* CNFG_CNTL register constants */ 851*4882a593Smuzhiyun #define APERTURE_4M_ENABLE 1 852*4882a593Smuzhiyun #define APERTURE_8M_ENABLE 2 853*4882a593Smuzhiyun #define VGA_APERTURE_ENABLE 4 854*4882a593Smuzhiyun 855*4882a593Smuzhiyun /* CNFG_STAT0 register constants (GX, CX) */ 856*4882a593Smuzhiyun #define CFG_BUS_TYPE 0x00000007 857*4882a593Smuzhiyun #define CFG_MEM_TYPE 0x00000038 858*4882a593Smuzhiyun #define CFG_INIT_DAC_TYPE 0x00000e00 859*4882a593Smuzhiyun 860*4882a593Smuzhiyun /* CNFG_STAT0 register constants (CT, ET, VT) */ 861*4882a593Smuzhiyun #define CFG_MEM_TYPE_xT 0x00000007 862*4882a593Smuzhiyun 863*4882a593Smuzhiyun #define ISA 0 864*4882a593Smuzhiyun #define EISA 1 865*4882a593Smuzhiyun #define LOCAL_BUS 6 866*4882a593Smuzhiyun #define PCI 7 867*4882a593Smuzhiyun 868*4882a593Smuzhiyun /* Memory types for GX, CX */ 869*4882a593Smuzhiyun #define DRAMx4 0 870*4882a593Smuzhiyun #define VRAMx16 1 871*4882a593Smuzhiyun #define VRAMx16ssr 2 872*4882a593Smuzhiyun #define DRAMx16 3 873*4882a593Smuzhiyun #define GraphicsDRAMx16 4 874*4882a593Smuzhiyun #define EnhancedVRAMx16 5 875*4882a593Smuzhiyun #define EnhancedVRAMx16ssr 6 876*4882a593Smuzhiyun 877*4882a593Smuzhiyun /* Memory types for CT, ET, VT, GT */ 878*4882a593Smuzhiyun #define DRAM 1 879*4882a593Smuzhiyun #define EDO 2 880*4882a593Smuzhiyun #define PSEUDO_EDO 3 881*4882a593Smuzhiyun #define SDRAM 4 882*4882a593Smuzhiyun #define SGRAM 5 883*4882a593Smuzhiyun #define WRAM 6 884*4882a593Smuzhiyun #define SDRAM32 6 885*4882a593Smuzhiyun 886*4882a593Smuzhiyun #define DAC_INTERNAL 0x00 887*4882a593Smuzhiyun #define DAC_IBMRGB514 0x01 888*4882a593Smuzhiyun #define DAC_ATI68875 0x02 889*4882a593Smuzhiyun #define DAC_TVP3026_A 0x72 890*4882a593Smuzhiyun #define DAC_BT476 0x03 891*4882a593Smuzhiyun #define DAC_BT481 0x04 892*4882a593Smuzhiyun #define DAC_ATT20C491 0x14 893*4882a593Smuzhiyun #define DAC_SC15026 0x24 894*4882a593Smuzhiyun #define DAC_MU9C1880 0x34 895*4882a593Smuzhiyun #define DAC_IMSG174 0x44 896*4882a593Smuzhiyun #define DAC_ATI68860_B 0x05 897*4882a593Smuzhiyun #define DAC_ATI68860_C 0x15 898*4882a593Smuzhiyun #define DAC_TVP3026_B 0x75 899*4882a593Smuzhiyun #define DAC_STG1700 0x06 900*4882a593Smuzhiyun #define DAC_ATT498 0x16 901*4882a593Smuzhiyun #define DAC_STG1702 0x07 902*4882a593Smuzhiyun #define DAC_SC15021 0x17 903*4882a593Smuzhiyun #define DAC_ATT21C498 0x27 904*4882a593Smuzhiyun #define DAC_STG1703 0x37 905*4882a593Smuzhiyun #define DAC_CH8398 0x47 906*4882a593Smuzhiyun #define DAC_ATT20C408 0x57 907*4882a593Smuzhiyun 908*4882a593Smuzhiyun #define CLK_ATI18818_0 0 909*4882a593Smuzhiyun #define CLK_ATI18818_1 1 910*4882a593Smuzhiyun #define CLK_STG1703 2 911*4882a593Smuzhiyun #define CLK_CH8398 3 912*4882a593Smuzhiyun #define CLK_INTERNAL 4 913*4882a593Smuzhiyun #define CLK_ATT20C408 5 914*4882a593Smuzhiyun #define CLK_IBMRGB514 6 915*4882a593Smuzhiyun 916*4882a593Smuzhiyun /* MEM_CNTL register constants */ 917*4882a593Smuzhiyun #define MEM_SIZE_ALIAS 0x00000007 918*4882a593Smuzhiyun #define MEM_SIZE_512K 0x00000000 919*4882a593Smuzhiyun #define MEM_SIZE_1M 0x00000001 920*4882a593Smuzhiyun #define MEM_SIZE_2M 0x00000002 921*4882a593Smuzhiyun #define MEM_SIZE_4M 0x00000003 922*4882a593Smuzhiyun #define MEM_SIZE_6M 0x00000004 923*4882a593Smuzhiyun #define MEM_SIZE_8M 0x00000005 924*4882a593Smuzhiyun #define MEM_SIZE_ALIAS_GTB 0x0000000F 925*4882a593Smuzhiyun #define MEM_SIZE_2M_GTB 0x00000003 926*4882a593Smuzhiyun #define MEM_SIZE_4M_GTB 0x00000007 927*4882a593Smuzhiyun #define MEM_SIZE_6M_GTB 0x00000009 928*4882a593Smuzhiyun #define MEM_SIZE_8M_GTB 0x0000000B 929*4882a593Smuzhiyun #define MEM_BNDRY 0x00030000 930*4882a593Smuzhiyun #define MEM_BNDRY_0K 0x00000000 931*4882a593Smuzhiyun #define MEM_BNDRY_256K 0x00010000 932*4882a593Smuzhiyun #define MEM_BNDRY_512K 0x00020000 933*4882a593Smuzhiyun #define MEM_BNDRY_1M 0x00030000 934*4882a593Smuzhiyun #define MEM_BNDRY_EN 0x00040000 935*4882a593Smuzhiyun 936*4882a593Smuzhiyun #define ONE_MB 0x100000 937*4882a593Smuzhiyun /* ATI PCI constants */ 938*4882a593Smuzhiyun #define PCI_ATI_VENDOR_ID 0x1002 939*4882a593Smuzhiyun 940*4882a593Smuzhiyun 941*4882a593Smuzhiyun /* CNFG_CHIP_ID register constants */ 942*4882a593Smuzhiyun #define CFG_CHIP_TYPE 0x0000FFFF 943*4882a593Smuzhiyun #define CFG_CHIP_CLASS 0x00FF0000 944*4882a593Smuzhiyun #define CFG_CHIP_REV 0xFF000000 945*4882a593Smuzhiyun #define CFG_CHIP_MAJOR 0x07000000 946*4882a593Smuzhiyun #define CFG_CHIP_FND_ID 0x38000000 947*4882a593Smuzhiyun #define CFG_CHIP_MINOR 0xC0000000 948*4882a593Smuzhiyun 949*4882a593Smuzhiyun 950*4882a593Smuzhiyun /* Chip IDs read from CNFG_CHIP_ID */ 951*4882a593Smuzhiyun 952*4882a593Smuzhiyun /* mach64GX family */ 953*4882a593Smuzhiyun #define GX_CHIP_ID 0xD7 /* mach64GX (ATI888GX00) */ 954*4882a593Smuzhiyun #define CX_CHIP_ID 0x57 /* mach64CX (ATI888CX00) */ 955*4882a593Smuzhiyun 956*4882a593Smuzhiyun #define GX_PCI_ID 0x4758 /* mach64GX (ATI888GX00) */ 957*4882a593Smuzhiyun #define CX_PCI_ID 0x4358 /* mach64CX (ATI888CX00) */ 958*4882a593Smuzhiyun 959*4882a593Smuzhiyun /* mach64CT family */ 960*4882a593Smuzhiyun #define CT_CHIP_ID 0x4354 /* mach64CT (ATI264CT) */ 961*4882a593Smuzhiyun #define ET_CHIP_ID 0x4554 /* mach64ET (ATI264ET) */ 962*4882a593Smuzhiyun 963*4882a593Smuzhiyun /* mach64CT family / mach64VT class */ 964*4882a593Smuzhiyun #define VT_CHIP_ID 0x5654 /* mach64VT (ATI264VT) */ 965*4882a593Smuzhiyun #define VU_CHIP_ID 0x5655 /* mach64VTB (ATI264VTB) */ 966*4882a593Smuzhiyun #define VV_CHIP_ID 0x5656 /* mach64VT4 (ATI264VT4) */ 967*4882a593Smuzhiyun 968*4882a593Smuzhiyun /* mach64CT family / mach64GT (3D RAGE) class */ 969*4882a593Smuzhiyun #define LB_CHIP_ID 0x4c42 /* RAGE LT PRO, AGP */ 970*4882a593Smuzhiyun #define LD_CHIP_ID 0x4c44 /* RAGE LT PRO */ 971*4882a593Smuzhiyun #define LG_CHIP_ID 0x4c47 /* RAGE LT */ 972*4882a593Smuzhiyun #define LI_CHIP_ID 0x4c49 /* RAGE LT PRO */ 973*4882a593Smuzhiyun #define LP_CHIP_ID 0x4c50 /* RAGE LT PRO */ 974*4882a593Smuzhiyun #define LT_CHIP_ID 0x4c54 /* RAGE LT */ 975*4882a593Smuzhiyun 976*4882a593Smuzhiyun /* mach64CT family / (Rage XL) class */ 977*4882a593Smuzhiyun #define GR_CHIP_ID 0x4752 /* RAGE XL, BGA, PCI33 */ 978*4882a593Smuzhiyun #define GS_CHIP_ID 0x4753 /* RAGE XL, PQFP, PCI33 */ 979*4882a593Smuzhiyun #define GM_CHIP_ID 0x474d /* RAGE XL, BGA, AGP 1x,2x */ 980*4882a593Smuzhiyun #define GN_CHIP_ID 0x474e /* RAGE XL, PQFP,AGP 1x,2x */ 981*4882a593Smuzhiyun #define GO_CHIP_ID 0x474f /* RAGE XL, BGA, PCI66 */ 982*4882a593Smuzhiyun #define GL_CHIP_ID 0x474c /* RAGE XL, PQFP, PCI66 */ 983*4882a593Smuzhiyun 984*4882a593Smuzhiyun #define IS_XL(id) ((id)==GR_CHIP_ID || (id)==GS_CHIP_ID || \ 985*4882a593Smuzhiyun (id)==GM_CHIP_ID || (id)==GN_CHIP_ID || \ 986*4882a593Smuzhiyun (id)==GO_CHIP_ID || (id)==GL_CHIP_ID) 987*4882a593Smuzhiyun 988*4882a593Smuzhiyun #define GT_CHIP_ID 0x4754 /* RAGE (GT) */ 989*4882a593Smuzhiyun #define GU_CHIP_ID 0x4755 /* RAGE II/II+ (GTB) */ 990*4882a593Smuzhiyun #define GV_CHIP_ID 0x4756 /* RAGE IIC, PCI */ 991*4882a593Smuzhiyun #define GW_CHIP_ID 0x4757 /* RAGE IIC, AGP */ 992*4882a593Smuzhiyun #define GZ_CHIP_ID 0x475a /* RAGE IIC, AGP */ 993*4882a593Smuzhiyun #define GB_CHIP_ID 0x4742 /* RAGE PRO, BGA, AGP 1x and 2x */ 994*4882a593Smuzhiyun #define GD_CHIP_ID 0x4744 /* RAGE PRO, BGA, AGP 1x only */ 995*4882a593Smuzhiyun #define GI_CHIP_ID 0x4749 /* RAGE PRO, BGA, PCI33 only */ 996*4882a593Smuzhiyun #define GP_CHIP_ID 0x4750 /* RAGE PRO, PQFP, PCI33, full 3D */ 997*4882a593Smuzhiyun #define GQ_CHIP_ID 0x4751 /* RAGE PRO, PQFP, PCI33, limited 3D */ 998*4882a593Smuzhiyun 999*4882a593Smuzhiyun #define LM_CHIP_ID 0x4c4d /* RAGE Mobility AGP, full function */ 1000*4882a593Smuzhiyun #define LN_CHIP_ID 0x4c4e /* RAGE Mobility AGP */ 1001*4882a593Smuzhiyun #define LR_CHIP_ID 0x4c52 /* RAGE Mobility PCI, full function */ 1002*4882a593Smuzhiyun #define LS_CHIP_ID 0x4c53 /* RAGE Mobility PCI */ 1003*4882a593Smuzhiyun 1004*4882a593Smuzhiyun #define IS_MOBILITY(id) ((id)==LM_CHIP_ID || (id)==LN_CHIP_ID || \ 1005*4882a593Smuzhiyun (id)==LR_CHIP_ID || (id)==LS_CHIP_ID) 1006*4882a593Smuzhiyun /* Mach64 major ASIC revisions */ 1007*4882a593Smuzhiyun #define MACH64_ASIC_NEC_VT_A3 0x08 1008*4882a593Smuzhiyun #define MACH64_ASIC_NEC_VT_A4 0x48 1009*4882a593Smuzhiyun #define MACH64_ASIC_SGS_VT_A4 0x40 1010*4882a593Smuzhiyun #define MACH64_ASIC_SGS_VT_B1S1 0x01 1011*4882a593Smuzhiyun #define MACH64_ASIC_SGS_GT_B1S1 0x01 1012*4882a593Smuzhiyun #define MACH64_ASIC_SGS_GT_B1S2 0x41 1013*4882a593Smuzhiyun #define MACH64_ASIC_UMC_GT_B2U1 0x1a 1014*4882a593Smuzhiyun #define MACH64_ASIC_UMC_GT_B2U2 0x5a 1015*4882a593Smuzhiyun #define MACH64_ASIC_UMC_VT_B2U3 0x9a 1016*4882a593Smuzhiyun #define MACH64_ASIC_UMC_GT_B2U3 0x9a 1017*4882a593Smuzhiyun #define MACH64_ASIC_UMC_R3B_D_P_A1 0x1b 1018*4882a593Smuzhiyun #define MACH64_ASIC_UMC_R3B_D_P_A2 0x5b 1019*4882a593Smuzhiyun #define MACH64_ASIC_UMC_R3B_D_P_A3 0x1c 1020*4882a593Smuzhiyun #define MACH64_ASIC_UMC_R3B_D_P_A4 0x5c 1021*4882a593Smuzhiyun 1022*4882a593Smuzhiyun /* Mach64 foundries */ 1023*4882a593Smuzhiyun #define MACH64_FND_SGS 0 1024*4882a593Smuzhiyun #define MACH64_FND_NEC 1 1025*4882a593Smuzhiyun #define MACH64_FND_UMC 3 1026*4882a593Smuzhiyun 1027*4882a593Smuzhiyun /* Mach64 chip types */ 1028*4882a593Smuzhiyun #define MACH64_UNKNOWN 0 1029*4882a593Smuzhiyun #define MACH64_GX 1 1030*4882a593Smuzhiyun #define MACH64_CX 2 1031*4882a593Smuzhiyun #define MACH64_CT 3Restore 1032*4882a593Smuzhiyun #define MACH64_ET 4 1033*4882a593Smuzhiyun #define MACH64_VT 5 1034*4882a593Smuzhiyun #define MACH64_GT 6 1035*4882a593Smuzhiyun 1036*4882a593Smuzhiyun /* DST_CNTL register constants */ 1037*4882a593Smuzhiyun #define DST_X_RIGHT_TO_LEFT 0 1038*4882a593Smuzhiyun #define DST_X_LEFT_TO_RIGHT 1 1039*4882a593Smuzhiyun #define DST_Y_BOTTOM_TO_TOP 0 1040*4882a593Smuzhiyun #define DST_Y_TOP_TO_BOTTOM 2 1041*4882a593Smuzhiyun #define DST_X_MAJOR 0 1042*4882a593Smuzhiyun #define DST_Y_MAJOR 4 1043*4882a593Smuzhiyun #define DST_X_TILE 8 1044*4882a593Smuzhiyun #define DST_Y_TILE 0x10 1045*4882a593Smuzhiyun #define DST_LAST_PEL 0x20 1046*4882a593Smuzhiyun #define DST_POLYGON_ENABLE 0x40 1047*4882a593Smuzhiyun #define DST_24_ROTATION_ENABLE 0x80 1048*4882a593Smuzhiyun 1049*4882a593Smuzhiyun /* SRC_CNTL register constants */ 1050*4882a593Smuzhiyun #define SRC_PATTERN_ENABLE 1 1051*4882a593Smuzhiyun #define SRC_ROTATION_ENABLE 2 1052*4882a593Smuzhiyun #define SRC_LINEAR_ENABLE 4 1053*4882a593Smuzhiyun #define SRC_BYTE_ALIGN 8 1054*4882a593Smuzhiyun #define SRC_LINE_X_RIGHT_TO_LEFT 0 1055*4882a593Smuzhiyun #define SRC_LINE_X_LEFT_TO_RIGHT 0x10 1056*4882a593Smuzhiyun 1057*4882a593Smuzhiyun /* HOST_CNTL register constants */ 1058*4882a593Smuzhiyun #define HOST_BYTE_ALIGN 1 1059*4882a593Smuzhiyun 1060*4882a593Smuzhiyun /* GUI_TRAJ_CNTL register constants */ 1061*4882a593Smuzhiyun #define PAT_MONO_8x8_ENABLE 0x01000000 1062*4882a593Smuzhiyun #define PAT_CLR_4x2_ENABLE 0x02000000 1063*4882a593Smuzhiyun #define PAT_CLR_8x1_ENABLE 0x04000000 1064*4882a593Smuzhiyun 1065*4882a593Smuzhiyun /* DP_CHAIN_MASK register constants */ 1066*4882a593Smuzhiyun #define DP_CHAIN_4BPP 0x8888 1067*4882a593Smuzhiyun #define DP_CHAIN_7BPP 0xD2D2 1068*4882a593Smuzhiyun #define DP_CHAIN_8BPP 0x8080 1069*4882a593Smuzhiyun #define DP_CHAIN_8BPP_RGB 0x9292 1070*4882a593Smuzhiyun #define DP_CHAIN_15BPP 0x4210 1071*4882a593Smuzhiyun #define DP_CHAIN_16BPP 0x8410 1072*4882a593Smuzhiyun #define DP_CHAIN_24BPP 0x8080 1073*4882a593Smuzhiyun #define DP_CHAIN_32BPP 0x8080 1074*4882a593Smuzhiyun 1075*4882a593Smuzhiyun /* DP_PIX_WIDTH register constants */ 1076*4882a593Smuzhiyun #define DST_1BPP 0x0 1077*4882a593Smuzhiyun #define DST_4BPP 0x1 1078*4882a593Smuzhiyun #define DST_8BPP 0x2 1079*4882a593Smuzhiyun #define DST_15BPP 0x3 1080*4882a593Smuzhiyun #define DST_16BPP 0x4 1081*4882a593Smuzhiyun #define DST_24BPP 0x5 1082*4882a593Smuzhiyun #define DST_32BPP 0x6 1083*4882a593Smuzhiyun #define DST_MASK 0xF 1084*4882a593Smuzhiyun #define SRC_1BPP 0x000 1085*4882a593Smuzhiyun #define SRC_4BPP 0x100 1086*4882a593Smuzhiyun #define SRC_8BPP 0x200 1087*4882a593Smuzhiyun #define SRC_15BPP 0x300 1088*4882a593Smuzhiyun #define SRC_16BPP 0x400 1089*4882a593Smuzhiyun #define SRC_24BPP 0x500 1090*4882a593Smuzhiyun #define SRC_32BPP 0x600 1091*4882a593Smuzhiyun #define SRC_MASK 0xF00 1092*4882a593Smuzhiyun #define DP_HOST_TRIPLE_EN 0x2000 1093*4882a593Smuzhiyun #define HOST_1BPP 0x00000 1094*4882a593Smuzhiyun #define HOST_4BPP 0x10000 1095*4882a593Smuzhiyun #define HOST_8BPP 0x20000 1096*4882a593Smuzhiyun #define HOST_15BPP 0x30000 1097*4882a593Smuzhiyun #define HOST_16BPP 0x40000 1098*4882a593Smuzhiyun #define HOST_24BPP 0x50000 1099*4882a593Smuzhiyun #define HOST_32BPP 0x60000 1100*4882a593Smuzhiyun #define HOST_MASK 0xF0000 1101*4882a593Smuzhiyun #define BYTE_ORDER_MSB_TO_LSB 0 1102*4882a593Smuzhiyun #define BYTE_ORDER_LSB_TO_MSB 0x1000000 1103*4882a593Smuzhiyun #define BYTE_ORDER_MASK 0x1000000 1104*4882a593Smuzhiyun 1105*4882a593Smuzhiyun /* DP_MIX register constants */ 1106*4882a593Smuzhiyun #define BKGD_MIX_NOT_D 0 1107*4882a593Smuzhiyun #define BKGD_MIX_ZERO 1 1108*4882a593Smuzhiyun #define BKGD_MIX_ONE 2 1109*4882a593Smuzhiyun #define BKGD_MIX_D 3 1110*4882a593Smuzhiyun #define BKGD_MIX_NOT_S 4 1111*4882a593Smuzhiyun #define BKGD_MIX_D_XOR_S 5 1112*4882a593Smuzhiyun #define BKGD_MIX_NOT_D_XOR_S 6 1113*4882a593Smuzhiyun #define BKGD_MIX_S 7 1114*4882a593Smuzhiyun #define BKGD_MIX_NOT_D_OR_NOT_S 8 1115*4882a593Smuzhiyun #define BKGD_MIX_D_OR_NOT_S 9 1116*4882a593Smuzhiyun #define BKGD_MIX_NOT_D_OR_S 10 1117*4882a593Smuzhiyun #define BKGD_MIX_D_OR_S 11 1118*4882a593Smuzhiyun #define BKGD_MIX_D_AND_S 12 1119*4882a593Smuzhiyun #define BKGD_MIX_NOT_D_AND_S 13 1120*4882a593Smuzhiyun #define BKGD_MIX_D_AND_NOT_S 14 1121*4882a593Smuzhiyun #define BKGD_MIX_NOT_D_AND_NOT_S 15 1122*4882a593Smuzhiyun #define BKGD_MIX_D_PLUS_S_DIV2 0x17 1123*4882a593Smuzhiyun #define FRGD_MIX_NOT_D 0 1124*4882a593Smuzhiyun #define FRGD_MIX_ZERO 0x10000 1125*4882a593Smuzhiyun #define FRGD_MIX_ONE 0x20000 1126*4882a593Smuzhiyun #define FRGD_MIX_D 0x30000 1127*4882a593Smuzhiyun #define FRGD_MIX_NOT_S 0x40000 1128*4882a593Smuzhiyun #define FRGD_MIX_D_XOR_S 0x50000 1129*4882a593Smuzhiyun #define FRGD_MIX_NOT_D_XOR_S 0x60000 1130*4882a593Smuzhiyun #define FRGD_MIX_S 0x70000 1131*4882a593Smuzhiyun #define FRGD_MIX_NOT_D_OR_NOT_S 0x80000 1132*4882a593Smuzhiyun #define FRGD_MIX_D_OR_NOT_S 0x90000 1133*4882a593Smuzhiyun #define FRGD_MIX_NOT_D_OR_S 0xa0000 1134*4882a593Smuzhiyun #define FRGD_MIX_D_OR_S 0xb0000 1135*4882a593Smuzhiyun #define FRGD_MIX_D_AND_S 0xc0000 1136*4882a593Smuzhiyun #define FRGD_MIX_NOT_D_AND_S 0xd0000 1137*4882a593Smuzhiyun #define FRGD_MIX_D_AND_NOT_S 0xe0000 1138*4882a593Smuzhiyun #define FRGD_MIX_NOT_D_AND_NOT_S 0xf0000 1139*4882a593Smuzhiyun #define FRGD_MIX_D_PLUS_S_DIV2 0x170000 1140*4882a593Smuzhiyun 1141*4882a593Smuzhiyun /* DP_SRC register constants */ 1142*4882a593Smuzhiyun #define BKGD_SRC_BKGD_CLR 0 1143*4882a593Smuzhiyun #define BKGD_SRC_FRGD_CLR 1 1144*4882a593Smuzhiyun #define BKGD_SRC_HOST 2 1145*4882a593Smuzhiyun #define BKGD_SRC_BLIT 3 1146*4882a593Smuzhiyun #define BKGD_SRC_PATTERN 4 1147*4882a593Smuzhiyun #define FRGD_SRC_BKGD_CLR 0 1148*4882a593Smuzhiyun #define FRGD_SRC_FRGD_CLR 0x100 1149*4882a593Smuzhiyun #define FRGD_SRC_HOST 0x200 1150*4882a593Smuzhiyun #define FRGD_SRC_BLIT 0x300 1151*4882a593Smuzhiyun #define FRGD_SRC_PATTERN 0x400 1152*4882a593Smuzhiyun #define MONO_SRC_ONE 0 1153*4882a593Smuzhiyun #define MONO_SRC_PATTERN 0x10000 1154*4882a593Smuzhiyun #define MONO_SRC_HOST 0x20000 1155*4882a593Smuzhiyun #define MONO_SRC_BLIT 0x30000 1156*4882a593Smuzhiyun 1157*4882a593Smuzhiyun /* CLR_CMP_CNTL register constants */ 1158*4882a593Smuzhiyun #define COMPARE_FALSE 0 1159*4882a593Smuzhiyun #define COMPARE_TRUE 1 1160*4882a593Smuzhiyun #define COMPARE_NOT_EQUAL 4 1161*4882a593Smuzhiyun #define COMPARE_EQUAL 5 1162*4882a593Smuzhiyun #define COMPARE_DESTINATION 0 1163*4882a593Smuzhiyun #define COMPARE_SOURCE 0x1000000 1164*4882a593Smuzhiyun 1165*4882a593Smuzhiyun /* FIFO_STAT register constants */ 1166*4882a593Smuzhiyun #define FIFO_ERR 0x80000000 1167*4882a593Smuzhiyun 1168*4882a593Smuzhiyun /* CONTEXT_LOAD_CNTL constants */ 1169*4882a593Smuzhiyun #define CONTEXT_NO_LOAD 0 1170*4882a593Smuzhiyun #define CONTEXT_LOAD 0x10000 1171*4882a593Smuzhiyun #define CONTEXT_LOAD_AND_DO_FILL 0x20000 1172*4882a593Smuzhiyun #define CONTEXT_LOAD_AND_DO_LINE 0x30000 1173*4882a593Smuzhiyun #define CONTEXT_EXECUTE 0 1174*4882a593Smuzhiyun #define CONTEXT_CMD_DISABLE 0x80000000 1175*4882a593Smuzhiyun 1176*4882a593Smuzhiyun /* GUI_STAT register constants */ 1177*4882a593Smuzhiyun #define ENGINE_IDLE 0 1178*4882a593Smuzhiyun #define ENGINE_BUSY 1 1179*4882a593Smuzhiyun #define SCISSOR_LEFT_FLAG 0x10 1180*4882a593Smuzhiyun #define SCISSOR_RIGHT_FLAG 0x20 1181*4882a593Smuzhiyun #define SCISSOR_TOP_FLAG 0x40 1182*4882a593Smuzhiyun #define SCISSOR_BOTTOM_FLAG 0x80 1183*4882a593Smuzhiyun 1184*4882a593Smuzhiyun /* ATI VGA Extended Regsiters */ 1185*4882a593Smuzhiyun #define sioATIEXT 0x1ce 1186*4882a593Smuzhiyun #define bioATIEXT 0x3ce 1187*4882a593Smuzhiyun 1188*4882a593Smuzhiyun #define ATI2E 0xae 1189*4882a593Smuzhiyun #define ATI32 0xb2 1190*4882a593Smuzhiyun #define ATI36 0xb6 1191*4882a593Smuzhiyun 1192*4882a593Smuzhiyun /* VGA Graphics Controller Registers */ 1193*4882a593Smuzhiyun #define R_GENMO 0x3cc 1194*4882a593Smuzhiyun #define VGAGRA 0x3ce 1195*4882a593Smuzhiyun #define GRA06 0x06 1196*4882a593Smuzhiyun 1197*4882a593Smuzhiyun /* VGA Seququencer Registers */ 1198*4882a593Smuzhiyun #define VGASEQ 0x3c4 1199*4882a593Smuzhiyun #define SEQ02 0x02 1200*4882a593Smuzhiyun #define SEQ04 0x04 1201*4882a593Smuzhiyun 1202*4882a593Smuzhiyun #define MACH64_MAX_X ENGINE_MAX_X 1203*4882a593Smuzhiyun #define MACH64_MAX_Y ENGINE_MAX_Y 1204*4882a593Smuzhiyun 1205*4882a593Smuzhiyun #define INC_X 0x0020 1206*4882a593Smuzhiyun #define INC_Y 0x0080 1207*4882a593Smuzhiyun 1208*4882a593Smuzhiyun #define RGB16_555 0x0000 1209*4882a593Smuzhiyun #define RGB16_565 0x0040 1210*4882a593Smuzhiyun #define RGB16_655 0x0080 1211*4882a593Smuzhiyun #define RGB16_664 0x00c0 1212*4882a593Smuzhiyun 1213*4882a593Smuzhiyun #define POLY_TEXT_TYPE 0x0001 1214*4882a593Smuzhiyun #define IMAGE_TEXT_TYPE 0x0002 1215*4882a593Smuzhiyun #define TEXT_TYPE_8_BIT 0x0004 1216*4882a593Smuzhiyun #define TEXT_TYPE_16_BIT 0x0008 1217*4882a593Smuzhiyun #define POLY_TEXT_TYPE_8 (POLY_TEXT_TYPE | TEXT_TYPE_8_BIT) 1218*4882a593Smuzhiyun #define IMAGE_TEXT_TYPE_8 (IMAGE_TEXT_TYPE | TEXT_TYPE_8_BIT) 1219*4882a593Smuzhiyun #define POLY_TEXT_TYPE_16 (POLY_TEXT_TYPE | TEXT_TYPE_16_BIT) 1220*4882a593Smuzhiyun #define IMAGE_TEXT_TYPE_16 (IMAGE_TEXT_TYPE | TEXT_TYPE_16_BIT) 1221*4882a593Smuzhiyun 1222*4882a593Smuzhiyun #define MACH64_NUM_CLOCKS 16 1223*4882a593Smuzhiyun #define MACH64_NUM_FREQS 50 1224*4882a593Smuzhiyun 1225*4882a593Smuzhiyun /* Power Management register constants (LT & LT Pro) */ 1226*4882a593Smuzhiyun #define PWR_MGT_ON 0x00000001 1227*4882a593Smuzhiyun #define PWR_MGT_MODE_MASK 0x00000006 1228*4882a593Smuzhiyun #define AUTO_PWR_UP 0x00000008 1229*4882a593Smuzhiyun #define USE_F32KHZ 0x00000400 1230*4882a593Smuzhiyun #define TRISTATE_MEM_EN 0x00000800 1231*4882a593Smuzhiyun #define SELF_REFRESH 0x00000080 1232*4882a593Smuzhiyun #define PWR_BLON 0x02000000 1233*4882a593Smuzhiyun #define STANDBY_NOW 0x10000000 1234*4882a593Smuzhiyun #define SUSPEND_NOW 0x20000000 1235*4882a593Smuzhiyun #define PWR_MGT_STATUS_MASK 0xC0000000 1236*4882a593Smuzhiyun #define PWR_MGT_STATUS_SUSPEND 0x80000000 1237*4882a593Smuzhiyun 1238*4882a593Smuzhiyun /* PM Mode constants */ 1239*4882a593Smuzhiyun #define PWR_MGT_MODE_PIN 0x00000000 1240*4882a593Smuzhiyun #define PWR_MGT_MODE_REG 0x00000002 1241*4882a593Smuzhiyun #define PWR_MGT_MODE_TIMER 0x00000004 1242*4882a593Smuzhiyun #define PWR_MGT_MODE_PCI 0x00000006 1243*4882a593Smuzhiyun 1244*4882a593Smuzhiyun /* LCD registers (LT Pro) */ 1245*4882a593Smuzhiyun 1246*4882a593Smuzhiyun /* LCD Index register */ 1247*4882a593Smuzhiyun #define LCD_INDEX_MASK 0x0000003F 1248*4882a593Smuzhiyun #define LCD_DISPLAY_DIS 0x00000100 1249*4882a593Smuzhiyun #define LCD_SRC_SEL 0x00000200 1250*4882a593Smuzhiyun #define CRTC2_DISPLAY_DIS 0x00000400 1251*4882a593Smuzhiyun 1252*4882a593Smuzhiyun /* LCD register indices */ 1253*4882a593Smuzhiyun #define CNFG_PANEL 0x00 1254*4882a593Smuzhiyun #define LCD_GEN_CNTL 0x01 1255*4882a593Smuzhiyun #define DSTN_CONTROL 0x02 1256*4882a593Smuzhiyun #define HFB_PITCH_ADDR 0x03 1257*4882a593Smuzhiyun #define HORZ_STRETCHING 0x04 1258*4882a593Smuzhiyun #define VERT_STRETCHING 0x05 1259*4882a593Smuzhiyun #define EXT_VERT_STRETCH 0x06 1260*4882a593Smuzhiyun #define LT_GIO 0x07 1261*4882a593Smuzhiyun #define POWER_MANAGEMENT 0x08 1262*4882a593Smuzhiyun #define ZVGPIO 0x09 1263*4882a593Smuzhiyun #define ICON_CLR0 0x0A 1264*4882a593Smuzhiyun #define ICON_CLR1 0x0B 1265*4882a593Smuzhiyun #define ICON_OFFSET 0x0C 1266*4882a593Smuzhiyun #define ICON_HORZ_VERT_POSN 0x0D 1267*4882a593Smuzhiyun #define ICON_HORZ_VERT_OFF 0x0E 1268*4882a593Smuzhiyun #define ICON2_CLR0 0x0F 1269*4882a593Smuzhiyun #define ICON2_CLR1 0x10 1270*4882a593Smuzhiyun #define ICON2_OFFSET 0x11 1271*4882a593Smuzhiyun #define ICON2_HORZ_VERT_POSN 0x12 1272*4882a593Smuzhiyun #define ICON2_HORZ_VERT_OFF 0x13 1273*4882a593Smuzhiyun #define LCD_MISC_CNTL 0x14 1274*4882a593Smuzhiyun #define APC_CNTL 0x1C 1275*4882a593Smuzhiyun #define POWER_MANAGEMENT_2 0x1D 1276*4882a593Smuzhiyun #define ALPHA_BLENDING 0x25 1277*4882a593Smuzhiyun #define PORTRAIT_GEN_CNTL 0x26 1278*4882a593Smuzhiyun #define APC_CTRL_IO 0x27 1279*4882a593Smuzhiyun #define TEST_IO 0x28 1280*4882a593Smuzhiyun #define TEST_OUTPUTS 0x29 1281*4882a593Smuzhiyun #define DP1_MEM_ACCESS 0x2A 1282*4882a593Smuzhiyun #define DP0_MEM_ACCESS 0x2B 1283*4882a593Smuzhiyun #define DP0_DEBUG_A 0x2C 1284*4882a593Smuzhiyun #define DP0_DEBUG_B 0x2D 1285*4882a593Smuzhiyun #define DP1_DEBUG_A 0x2E 1286*4882a593Smuzhiyun #define DP1_DEBUG_B 0x2F 1287*4882a593Smuzhiyun #define DPCTRL_DEBUG_A 0x30 1288*4882a593Smuzhiyun #define DPCTRL_DEBUG_B 0x31 1289*4882a593Smuzhiyun #define MEMBLK_DEBUG 0x32 1290*4882a593Smuzhiyun #define APC_LUT_AB 0x33 1291*4882a593Smuzhiyun #define APC_LUT_CD 0x34 1292*4882a593Smuzhiyun #define APC_LUT_EF 0x35 1293*4882a593Smuzhiyun #define APC_LUT_GH 0x36 1294*4882a593Smuzhiyun #define APC_LUT_IJ 0x37 1295*4882a593Smuzhiyun #define APC_LUT_KL 0x38 1296*4882a593Smuzhiyun #define APC_LUT_MN 0x39 1297*4882a593Smuzhiyun #define APC_LUT_OP 0x3A 1298*4882a593Smuzhiyun 1299*4882a593Smuzhiyun /* Values in LCD_GEN_CTRL */ 1300*4882a593Smuzhiyun #define CRT_ON 0x00000001ul 1301*4882a593Smuzhiyun #define LCD_ON 0x00000002ul 1302*4882a593Smuzhiyun #define HORZ_DIVBY2_EN 0x00000004ul 1303*4882a593Smuzhiyun #define DONT_DS_ICON 0x00000008ul 1304*4882a593Smuzhiyun #define LOCK_8DOT 0x00000010ul 1305*4882a593Smuzhiyun #define ICON_ENABLE 0x00000020ul 1306*4882a593Smuzhiyun #define DONT_SHADOW_VPAR 0x00000040ul 1307*4882a593Smuzhiyun #define V2CLK_PM_EN 0x00000080ul 1308*4882a593Smuzhiyun #define RST_FM 0x00000100ul 1309*4882a593Smuzhiyun #define DISABLE_PCLK_RESET 0x00000200ul /* XC/XL */ 1310*4882a593Smuzhiyun #define DIS_HOR_CRT_DIVBY2 0x00000400ul 1311*4882a593Smuzhiyun #define SCLK_SEL 0x00000800ul 1312*4882a593Smuzhiyun #define SCLK_DELAY 0x0000f000ul 1313*4882a593Smuzhiyun #define TVCLK_PM_EN 0x00010000ul 1314*4882a593Smuzhiyun #define VCLK_DAC_PM_EN 0x00020000ul 1315*4882a593Smuzhiyun #define VCLK_LCD_OFF 0x00040000ul 1316*4882a593Smuzhiyun #define SELECT_WAIT_4MS 0x00080000ul 1317*4882a593Smuzhiyun #define XTALIN_PM_EN 0x00080000ul /* XC/XL */ 1318*4882a593Smuzhiyun #define V2CLK_DAC_PM_EN 0x00100000ul 1319*4882a593Smuzhiyun #define LVDS_EN 0x00200000ul 1320*4882a593Smuzhiyun #define LVDS_PLL_EN 0x00400000ul 1321*4882a593Smuzhiyun #define LVDS_PLL_RESET 0x00800000ul 1322*4882a593Smuzhiyun #define LVDS_RESERVED_BITS 0x07000000ul 1323*4882a593Smuzhiyun #define CRTC_RW_SELECT 0x08000000ul /* LTPro */ 1324*4882a593Smuzhiyun #define USE_SHADOWED_VEND 0x10000000ul 1325*4882a593Smuzhiyun #define USE_SHADOWED_ROWCUR 0x20000000ul 1326*4882a593Smuzhiyun #define SHADOW_EN 0x40000000ul 1327*4882a593Smuzhiyun #define SHADOW_RW_EN 0x80000000ul 1328*4882a593Smuzhiyun 1329*4882a593Smuzhiyun #define LCD_SET_PRIMARY_MASK 0x07FFFBFBul 1330*4882a593Smuzhiyun 1331*4882a593Smuzhiyun /* Values in HORZ_STRETCHING */ 1332*4882a593Smuzhiyun #define HORZ_STRETCH_BLEND 0x00000ffful 1333*4882a593Smuzhiyun #define HORZ_STRETCH_RATIO 0x0000fffful 1334*4882a593Smuzhiyun #define HORZ_STRETCH_LOOP 0x00070000ul 1335*4882a593Smuzhiyun #define HORZ_STRETCH_LOOP09 0x00000000ul 1336*4882a593Smuzhiyun #define HORZ_STRETCH_LOOP11 0x00010000ul 1337*4882a593Smuzhiyun #define HORZ_STRETCH_LOOP12 0x00020000ul 1338*4882a593Smuzhiyun #define HORZ_STRETCH_LOOP14 0x00030000ul 1339*4882a593Smuzhiyun #define HORZ_STRETCH_LOOP15 0x00040000ul 1340*4882a593Smuzhiyun /* ? 0x00050000ul */ 1341*4882a593Smuzhiyun /* ? 0x00060000ul */ 1342*4882a593Smuzhiyun /* ? 0x00070000ul */ 1343*4882a593Smuzhiyun /* ? 0x00080000ul */ 1344*4882a593Smuzhiyun #define HORZ_PANEL_SIZE 0x0ff00000ul /* XC/XL */ 1345*4882a593Smuzhiyun /* ? 0x10000000ul */ 1346*4882a593Smuzhiyun #define AUTO_HORZ_RATIO 0x20000000ul /* XC/XL */ 1347*4882a593Smuzhiyun #define HORZ_STRETCH_MODE 0x40000000ul 1348*4882a593Smuzhiyun #define HORZ_STRETCH_EN 0x80000000ul 1349*4882a593Smuzhiyun 1350*4882a593Smuzhiyun /* Values in VERT_STRETCHING */ 1351*4882a593Smuzhiyun #define VERT_STRETCH_RATIO0 0x000003fful 1352*4882a593Smuzhiyun #define VERT_STRETCH_RATIO1 0x000ffc00ul 1353*4882a593Smuzhiyun #define VERT_STRETCH_RATIO2 0x3ff00000ul 1354*4882a593Smuzhiyun #define VERT_STRETCH_USE0 0x40000000ul 1355*4882a593Smuzhiyun #define VERT_STRETCH_EN 0x80000000ul 1356*4882a593Smuzhiyun 1357*4882a593Smuzhiyun /* Values in EXT_VERT_STRETCH */ 1358*4882a593Smuzhiyun #define VERT_STRETCH_RATIO3 0x000003fful 1359*4882a593Smuzhiyun #define FORCE_DAC_DATA 0x000000fful 1360*4882a593Smuzhiyun #define FORCE_DAC_DATA_SEL 0x00000300ul 1361*4882a593Smuzhiyun #define VERT_STRETCH_MODE 0x00000400ul 1362*4882a593Smuzhiyun #define VERT_PANEL_SIZE 0x003ff800ul 1363*4882a593Smuzhiyun #define AUTO_VERT_RATIO 0x00400000ul 1364*4882a593Smuzhiyun #define USE_AUTO_FP_POS 0x00800000ul 1365*4882a593Smuzhiyun #define USE_AUTO_LCD_VSYNC 0x01000000ul 1366*4882a593Smuzhiyun /* ? 0xfe000000ul */ 1367*4882a593Smuzhiyun 1368*4882a593Smuzhiyun /* Values in LCD_MISC_CNTL */ 1369*4882a593Smuzhiyun #define BIAS_MOD_LEVEL_MASK 0x0000ff00 1370*4882a593Smuzhiyun #define BIAS_MOD_LEVEL_SHIFT 8 1371*4882a593Smuzhiyun #define BLMOD_EN 0x00010000 1372*4882a593Smuzhiyun #define BIASMOD_EN 0x00020000 1373*4882a593Smuzhiyun 1374*4882a593Smuzhiyun #endif /* REGMACH64_H */ 1375