1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-only */
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * Copyright 2012 Steffen Trumtrar <s.trumtrar@pengutronix.de>
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * description of display timings
6*4882a593Smuzhiyun */
7*4882a593Smuzhiyun
8*4882a593Smuzhiyun #ifndef __LINUX_DISPLAY_TIMING_H
9*4882a593Smuzhiyun #define __LINUX_DISPLAY_TIMING_H
10*4882a593Smuzhiyun
11*4882a593Smuzhiyun #include <linux/bitops.h>
12*4882a593Smuzhiyun #include <linux/types.h>
13*4882a593Smuzhiyun
14*4882a593Smuzhiyun enum display_flags {
15*4882a593Smuzhiyun DISPLAY_FLAGS_HSYNC_LOW = BIT(0),
16*4882a593Smuzhiyun DISPLAY_FLAGS_HSYNC_HIGH = BIT(1),
17*4882a593Smuzhiyun DISPLAY_FLAGS_VSYNC_LOW = BIT(2),
18*4882a593Smuzhiyun DISPLAY_FLAGS_VSYNC_HIGH = BIT(3),
19*4882a593Smuzhiyun
20*4882a593Smuzhiyun /* data enable flag */
21*4882a593Smuzhiyun DISPLAY_FLAGS_DE_LOW = BIT(4),
22*4882a593Smuzhiyun DISPLAY_FLAGS_DE_HIGH = BIT(5),
23*4882a593Smuzhiyun /* drive data on pos. edge */
24*4882a593Smuzhiyun DISPLAY_FLAGS_PIXDATA_POSEDGE = BIT(6),
25*4882a593Smuzhiyun /* drive data on neg. edge */
26*4882a593Smuzhiyun DISPLAY_FLAGS_PIXDATA_NEGEDGE = BIT(7),
27*4882a593Smuzhiyun DISPLAY_FLAGS_INTERLACED = BIT(8),
28*4882a593Smuzhiyun DISPLAY_FLAGS_DOUBLESCAN = BIT(9),
29*4882a593Smuzhiyun DISPLAY_FLAGS_DOUBLECLK = BIT(10),
30*4882a593Smuzhiyun /* drive sync on pos. edge */
31*4882a593Smuzhiyun DISPLAY_FLAGS_SYNC_POSEDGE = BIT(11),
32*4882a593Smuzhiyun /* drive sync on neg. edge */
33*4882a593Smuzhiyun DISPLAY_FLAGS_SYNC_NEGEDGE = BIT(12),
34*4882a593Smuzhiyun };
35*4882a593Smuzhiyun
36*4882a593Smuzhiyun /*
37*4882a593Smuzhiyun * A single signal can be specified via a range of minimal and maximal values
38*4882a593Smuzhiyun * with a typical value, that lies somewhere inbetween.
39*4882a593Smuzhiyun */
40*4882a593Smuzhiyun struct timing_entry {
41*4882a593Smuzhiyun u32 min;
42*4882a593Smuzhiyun u32 typ;
43*4882a593Smuzhiyun u32 max;
44*4882a593Smuzhiyun };
45*4882a593Smuzhiyun
46*4882a593Smuzhiyun /*
47*4882a593Smuzhiyun * Single "mode" entry. This describes one set of signal timings a display can
48*4882a593Smuzhiyun * have in one setting. This struct can later be converted to struct videomode
49*4882a593Smuzhiyun * (see include/video/videomode.h). As each timing_entry can be defined as a
50*4882a593Smuzhiyun * range, one struct display_timing may become multiple struct videomodes.
51*4882a593Smuzhiyun *
52*4882a593Smuzhiyun * Example: hsync active high, vsync active low
53*4882a593Smuzhiyun *
54*4882a593Smuzhiyun * Active Video
55*4882a593Smuzhiyun * Video ______________________XXXXXXXXXXXXXXXXXXXXXX_____________________
56*4882a593Smuzhiyun * |<- sync ->|<- back ->|<----- active ----->|<- front ->|<- sync..
57*4882a593Smuzhiyun * | | porch | | porch |
58*4882a593Smuzhiyun *
59*4882a593Smuzhiyun * HSync _|¯¯¯¯¯¯¯¯¯¯|___________________________________________|¯¯¯¯¯¯¯¯¯
60*4882a593Smuzhiyun *
61*4882a593Smuzhiyun * VSync ¯|__________|¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯|_________
62*4882a593Smuzhiyun */
63*4882a593Smuzhiyun struct display_timing {
64*4882a593Smuzhiyun struct timing_entry pixelclock;
65*4882a593Smuzhiyun
66*4882a593Smuzhiyun struct timing_entry hactive; /* hor. active video */
67*4882a593Smuzhiyun struct timing_entry hfront_porch; /* hor. front porch */
68*4882a593Smuzhiyun struct timing_entry hback_porch; /* hor. back porch */
69*4882a593Smuzhiyun struct timing_entry hsync_len; /* hor. sync len */
70*4882a593Smuzhiyun
71*4882a593Smuzhiyun struct timing_entry vactive; /* ver. active video */
72*4882a593Smuzhiyun struct timing_entry vfront_porch; /* ver. front porch */
73*4882a593Smuzhiyun struct timing_entry vback_porch; /* ver. back porch */
74*4882a593Smuzhiyun struct timing_entry vsync_len; /* ver. sync len */
75*4882a593Smuzhiyun
76*4882a593Smuzhiyun enum display_flags flags; /* display flags */
77*4882a593Smuzhiyun };
78*4882a593Smuzhiyun
79*4882a593Smuzhiyun /*
80*4882a593Smuzhiyun * This describes all timing settings a display provides.
81*4882a593Smuzhiyun * The native_mode is the default setting for this display.
82*4882a593Smuzhiyun * Drivers that can handle multiple videomodes should work with this struct and
83*4882a593Smuzhiyun * convert each entry to the desired end result.
84*4882a593Smuzhiyun */
85*4882a593Smuzhiyun struct display_timings {
86*4882a593Smuzhiyun unsigned int num_timings;
87*4882a593Smuzhiyun unsigned int native_mode;
88*4882a593Smuzhiyun
89*4882a593Smuzhiyun struct display_timing **timings;
90*4882a593Smuzhiyun };
91*4882a593Smuzhiyun
92*4882a593Smuzhiyun /* get one entry from struct display_timings */
display_timings_get(const struct display_timings * disp,unsigned int index)93*4882a593Smuzhiyun static inline struct display_timing *display_timings_get(const struct
94*4882a593Smuzhiyun display_timings *disp,
95*4882a593Smuzhiyun unsigned int index)
96*4882a593Smuzhiyun {
97*4882a593Smuzhiyun if (disp->num_timings > index)
98*4882a593Smuzhiyun return disp->timings[index];
99*4882a593Smuzhiyun else
100*4882a593Smuzhiyun return NULL;
101*4882a593Smuzhiyun }
102*4882a593Smuzhiyun
103*4882a593Smuzhiyun void display_timings_release(struct display_timings *disp);
104*4882a593Smuzhiyun
105*4882a593Smuzhiyun #endif
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