1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * Phase5 CybervisionPPC (TVP4020) definitions for the Permedia2 framebuffer 3*4882a593Smuzhiyun * driver. 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Copyright (c) 1998-1999 Ilario Nardinocchi (nardinoc@CS.UniBO.IT) 6*4882a593Smuzhiyun * -------------------------------------------------------------------------- 7*4882a593Smuzhiyun * $Id: cvisionppc.h,v 1.8 1999/01/28 13:18:07 illo Exp $ 8*4882a593Smuzhiyun * -------------------------------------------------------------------------- 9*4882a593Smuzhiyun * This file is subject to the terms and conditions of the GNU General Public 10*4882a593Smuzhiyun * License. See the file COPYING in the main directory of this archive 11*4882a593Smuzhiyun * for more details. 12*4882a593Smuzhiyun */ 13*4882a593Smuzhiyun 14*4882a593Smuzhiyun #ifndef CVISIONPPC_H 15*4882a593Smuzhiyun #define CVISIONPPC_H 16*4882a593Smuzhiyun 17*4882a593Smuzhiyun #ifndef PM2FB_H 18*4882a593Smuzhiyun #include "pm2fb.h" 19*4882a593Smuzhiyun #endif 20*4882a593Smuzhiyun 21*4882a593Smuzhiyun struct cvppc_par { 22*4882a593Smuzhiyun unsigned char* pci_config; 23*4882a593Smuzhiyun unsigned char* pci_bridge; 24*4882a593Smuzhiyun u32 user_flags; 25*4882a593Smuzhiyun }; 26*4882a593Smuzhiyun 27*4882a593Smuzhiyun #define CSPPC_PCI_BRIDGE 0xfffe0000 28*4882a593Smuzhiyun #define CSPPC_BRIDGE_ENDIAN 0x0000 29*4882a593Smuzhiyun #define CSPPC_BRIDGE_INT 0x0010 30*4882a593Smuzhiyun 31*4882a593Smuzhiyun #define CVPPC_PCI_CONFIG 0xfffc0000 32*4882a593Smuzhiyun #define CVPPC_ROM_ADDRESS 0xe2000001 33*4882a593Smuzhiyun #define CVPPC_REGS_REGION 0xef000000 34*4882a593Smuzhiyun #define CVPPC_FB_APERTURE_ONE 0xe0000000 35*4882a593Smuzhiyun #define CVPPC_FB_APERTURE_TWO 0xe1000000 36*4882a593Smuzhiyun #define CVPPC_FB_SIZE 0x00800000 37*4882a593Smuzhiyun #define CVPPC_MEM_CONFIG_OLD 0xed61fcaa /* FIXME Fujitsu?? */ 38*4882a593Smuzhiyun #define CVPPC_MEM_CONFIG_NEW 0xed41c532 /* FIXME USA?? */ 39*4882a593Smuzhiyun #define CVPPC_MEMCLOCK 83000 /* in KHz */ 40*4882a593Smuzhiyun 41*4882a593Smuzhiyun /* CVPPC_BRIDGE_ENDIAN */ 42*4882a593Smuzhiyun #define CSPPCF_BRIDGE_BIG_ENDIAN 0x02 43*4882a593Smuzhiyun 44*4882a593Smuzhiyun /* CVPPC_BRIDGE_INT */ 45*4882a593Smuzhiyun #define CSPPCF_BRIDGE_ACTIVE_INT2 0x01 46*4882a593Smuzhiyun 47*4882a593Smuzhiyun #endif /* CVISIONPPC_H */ 48*4882a593Smuzhiyun 49*4882a593Smuzhiyun /***************************************************************************** 50*4882a593Smuzhiyun * That's all folks! 51*4882a593Smuzhiyun *****************************************************************************/ 52