1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-or-later */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Header file for AT91/AT32 LCD Controller 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Data structure and register user interface 6*4882a593Smuzhiyun * 7*4882a593Smuzhiyun * Copyright (C) 2007 Atmel Corporation 8*4882a593Smuzhiyun */ 9*4882a593Smuzhiyun #ifndef __ATMEL_LCDC_H__ 10*4882a593Smuzhiyun #define __ATMEL_LCDC_H__ 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun #include <linux/workqueue.h> 13*4882a593Smuzhiyun 14*4882a593Smuzhiyun /* Way LCD wires are connected to the chip: 15*4882a593Smuzhiyun * Some Atmel chips use BGR color mode (instead of standard RGB) 16*4882a593Smuzhiyun * A swapped wiring onboard can bring to RGB mode. 17*4882a593Smuzhiyun */ 18*4882a593Smuzhiyun #define ATMEL_LCDC_WIRING_BGR 0 19*4882a593Smuzhiyun #define ATMEL_LCDC_WIRING_RGB 1 20*4882a593Smuzhiyun 21*4882a593Smuzhiyun 22*4882a593Smuzhiyun /* LCD Controller info data structure, stored in device platform_data */ 23*4882a593Smuzhiyun struct atmel_lcdfb_pdata { 24*4882a593Smuzhiyun unsigned int guard_time; 25*4882a593Smuzhiyun bool lcdcon_is_backlight; 26*4882a593Smuzhiyun bool lcdcon_pol_negative; 27*4882a593Smuzhiyun u8 default_bpp; 28*4882a593Smuzhiyun u8 lcd_wiring_mode; 29*4882a593Smuzhiyun unsigned int default_lcdcon2; 30*4882a593Smuzhiyun unsigned int default_dmacon; 31*4882a593Smuzhiyun void (*atmel_lcdfb_power_control)(struct atmel_lcdfb_pdata *pdata, int on); 32*4882a593Smuzhiyun struct fb_monspecs *default_monspecs; 33*4882a593Smuzhiyun 34*4882a593Smuzhiyun struct list_head pwr_gpios; 35*4882a593Smuzhiyun }; 36*4882a593Smuzhiyun 37*4882a593Smuzhiyun #define ATMEL_LCDC_DMABADDR1 0x00 38*4882a593Smuzhiyun #define ATMEL_LCDC_DMABADDR2 0x04 39*4882a593Smuzhiyun #define ATMEL_LCDC_DMAFRMPT1 0x08 40*4882a593Smuzhiyun #define ATMEL_LCDC_DMAFRMPT2 0x0c 41*4882a593Smuzhiyun #define ATMEL_LCDC_DMAFRMADD1 0x10 42*4882a593Smuzhiyun #define ATMEL_LCDC_DMAFRMADD2 0x14 43*4882a593Smuzhiyun 44*4882a593Smuzhiyun #define ATMEL_LCDC_DMAFRMCFG 0x18 45*4882a593Smuzhiyun #define ATMEL_LCDC_FRSIZE (0x7fffff << 0) 46*4882a593Smuzhiyun #define ATMEL_LCDC_BLENGTH_OFFSET 24 47*4882a593Smuzhiyun #define ATMEL_LCDC_BLENGTH (0x7f << ATMEL_LCDC_BLENGTH_OFFSET) 48*4882a593Smuzhiyun 49*4882a593Smuzhiyun #define ATMEL_LCDC_DMACON 0x1c 50*4882a593Smuzhiyun #define ATMEL_LCDC_DMAEN (0x1 << 0) 51*4882a593Smuzhiyun #define ATMEL_LCDC_DMARST (0x1 << 1) 52*4882a593Smuzhiyun #define ATMEL_LCDC_DMABUSY (0x1 << 2) 53*4882a593Smuzhiyun #define ATMEL_LCDC_DMAUPDT (0x1 << 3) 54*4882a593Smuzhiyun #define ATMEL_LCDC_DMA2DEN (0x1 << 4) 55*4882a593Smuzhiyun 56*4882a593Smuzhiyun #define ATMEL_LCDC_DMA2DCFG 0x20 57*4882a593Smuzhiyun #define ATMEL_LCDC_ADDRINC_OFFSET 0 58*4882a593Smuzhiyun #define ATMEL_LCDC_ADDRINC (0xffff) 59*4882a593Smuzhiyun #define ATMEL_LCDC_PIXELOFF_OFFSET 24 60*4882a593Smuzhiyun #define ATMEL_LCDC_PIXELOFF (0x1f << 24) 61*4882a593Smuzhiyun 62*4882a593Smuzhiyun #define ATMEL_LCDC_LCDCON1 0x0800 63*4882a593Smuzhiyun #define ATMEL_LCDC_BYPASS (1 << 0) 64*4882a593Smuzhiyun #define ATMEL_LCDC_CLKVAL_OFFSET 12 65*4882a593Smuzhiyun #define ATMEL_LCDC_CLKVAL (0x1ff << ATMEL_LCDC_CLKVAL_OFFSET) 66*4882a593Smuzhiyun #define ATMEL_LCDC_LINCNT (0x7ff << 21) 67*4882a593Smuzhiyun 68*4882a593Smuzhiyun #define ATMEL_LCDC_LCDCON2 0x0804 69*4882a593Smuzhiyun #define ATMEL_LCDC_DISTYPE (3 << 0) 70*4882a593Smuzhiyun #define ATMEL_LCDC_DISTYPE_STNMONO (0 << 0) 71*4882a593Smuzhiyun #define ATMEL_LCDC_DISTYPE_STNCOLOR (1 << 0) 72*4882a593Smuzhiyun #define ATMEL_LCDC_DISTYPE_TFT (2 << 0) 73*4882a593Smuzhiyun #define ATMEL_LCDC_SCANMOD (1 << 2) 74*4882a593Smuzhiyun #define ATMEL_LCDC_SCANMOD_SINGLE (0 << 2) 75*4882a593Smuzhiyun #define ATMEL_LCDC_SCANMOD_DUAL (1 << 2) 76*4882a593Smuzhiyun #define ATMEL_LCDC_IFWIDTH (3 << 3) 77*4882a593Smuzhiyun #define ATMEL_LCDC_IFWIDTH_4 (0 << 3) 78*4882a593Smuzhiyun #define ATMEL_LCDC_IFWIDTH_8 (1 << 3) 79*4882a593Smuzhiyun #define ATMEL_LCDC_IFWIDTH_16 (2 << 3) 80*4882a593Smuzhiyun #define ATMEL_LCDC_PIXELSIZE (7 << 5) 81*4882a593Smuzhiyun #define ATMEL_LCDC_PIXELSIZE_1 (0 << 5) 82*4882a593Smuzhiyun #define ATMEL_LCDC_PIXELSIZE_2 (1 << 5) 83*4882a593Smuzhiyun #define ATMEL_LCDC_PIXELSIZE_4 (2 << 5) 84*4882a593Smuzhiyun #define ATMEL_LCDC_PIXELSIZE_8 (3 << 5) 85*4882a593Smuzhiyun #define ATMEL_LCDC_PIXELSIZE_16 (4 << 5) 86*4882a593Smuzhiyun #define ATMEL_LCDC_PIXELSIZE_24 (5 << 5) 87*4882a593Smuzhiyun #define ATMEL_LCDC_PIXELSIZE_32 (6 << 5) 88*4882a593Smuzhiyun #define ATMEL_LCDC_INVVD (1 << 8) 89*4882a593Smuzhiyun #define ATMEL_LCDC_INVVD_NORMAL (0 << 8) 90*4882a593Smuzhiyun #define ATMEL_LCDC_INVVD_INVERTED (1 << 8) 91*4882a593Smuzhiyun #define ATMEL_LCDC_INVFRAME (1 << 9 ) 92*4882a593Smuzhiyun #define ATMEL_LCDC_INVFRAME_NORMAL (0 << 9) 93*4882a593Smuzhiyun #define ATMEL_LCDC_INVFRAME_INVERTED (1 << 9) 94*4882a593Smuzhiyun #define ATMEL_LCDC_INVLINE (1 << 10) 95*4882a593Smuzhiyun #define ATMEL_LCDC_INVLINE_NORMAL (0 << 10) 96*4882a593Smuzhiyun #define ATMEL_LCDC_INVLINE_INVERTED (1 << 10) 97*4882a593Smuzhiyun #define ATMEL_LCDC_INVCLK (1 << 11) 98*4882a593Smuzhiyun #define ATMEL_LCDC_INVCLK_NORMAL (0 << 11) 99*4882a593Smuzhiyun #define ATMEL_LCDC_INVCLK_INVERTED (1 << 11) 100*4882a593Smuzhiyun #define ATMEL_LCDC_INVDVAL (1 << 12) 101*4882a593Smuzhiyun #define ATMEL_LCDC_INVDVAL_NORMAL (0 << 12) 102*4882a593Smuzhiyun #define ATMEL_LCDC_INVDVAL_INVERTED (1 << 12) 103*4882a593Smuzhiyun #define ATMEL_LCDC_CLKMOD (1 << 15) 104*4882a593Smuzhiyun #define ATMEL_LCDC_CLKMOD_ACTIVEDISPLAY (0 << 15) 105*4882a593Smuzhiyun #define ATMEL_LCDC_CLKMOD_ALWAYSACTIVE (1 << 15) 106*4882a593Smuzhiyun #define ATMEL_LCDC_MEMOR (1 << 31) 107*4882a593Smuzhiyun #define ATMEL_LCDC_MEMOR_BIG (0 << 31) 108*4882a593Smuzhiyun #define ATMEL_LCDC_MEMOR_LITTLE (1 << 31) 109*4882a593Smuzhiyun 110*4882a593Smuzhiyun #define ATMEL_LCDC_TIM1 0x0808 111*4882a593Smuzhiyun #define ATMEL_LCDC_VFP (0xffU << 0) 112*4882a593Smuzhiyun #define ATMEL_LCDC_VBP_OFFSET 8 113*4882a593Smuzhiyun #define ATMEL_LCDC_VBP (0xffU << ATMEL_LCDC_VBP_OFFSET) 114*4882a593Smuzhiyun #define ATMEL_LCDC_VPW_OFFSET 16 115*4882a593Smuzhiyun #define ATMEL_LCDC_VPW (0x3fU << ATMEL_LCDC_VPW_OFFSET) 116*4882a593Smuzhiyun #define ATMEL_LCDC_VHDLY_OFFSET 24 117*4882a593Smuzhiyun #define ATMEL_LCDC_VHDLY (0xfU << ATMEL_LCDC_VHDLY_OFFSET) 118*4882a593Smuzhiyun 119*4882a593Smuzhiyun #define ATMEL_LCDC_TIM2 0x080c 120*4882a593Smuzhiyun #define ATMEL_LCDC_HBP (0xffU << 0) 121*4882a593Smuzhiyun #define ATMEL_LCDC_HPW_OFFSET 8 122*4882a593Smuzhiyun #define ATMEL_LCDC_HPW (0x3fU << ATMEL_LCDC_HPW_OFFSET) 123*4882a593Smuzhiyun #define ATMEL_LCDC_HFP_OFFSET 21 124*4882a593Smuzhiyun #define ATMEL_LCDC_HFP (0x7ffU << ATMEL_LCDC_HFP_OFFSET) 125*4882a593Smuzhiyun 126*4882a593Smuzhiyun #define ATMEL_LCDC_LCDFRMCFG 0x0810 127*4882a593Smuzhiyun #define ATMEL_LCDC_LINEVAL (0x7ff << 0) 128*4882a593Smuzhiyun #define ATMEL_LCDC_HOZVAL_OFFSET 21 129*4882a593Smuzhiyun #define ATMEL_LCDC_HOZVAL (0x7ff << ATMEL_LCDC_HOZVAL_OFFSET) 130*4882a593Smuzhiyun 131*4882a593Smuzhiyun #define ATMEL_LCDC_FIFO 0x0814 132*4882a593Smuzhiyun #define ATMEL_LCDC_FIFOTH (0xffff) 133*4882a593Smuzhiyun 134*4882a593Smuzhiyun #define ATMEL_LCDC_MVAL 0x0818 135*4882a593Smuzhiyun 136*4882a593Smuzhiyun #define ATMEL_LCDC_DP1_2 0x081c 137*4882a593Smuzhiyun #define ATMEL_LCDC_DP4_7 0x0820 138*4882a593Smuzhiyun #define ATMEL_LCDC_DP3_5 0x0824 139*4882a593Smuzhiyun #define ATMEL_LCDC_DP2_3 0x0828 140*4882a593Smuzhiyun #define ATMEL_LCDC_DP5_7 0x082c 141*4882a593Smuzhiyun #define ATMEL_LCDC_DP3_4 0x0830 142*4882a593Smuzhiyun #define ATMEL_LCDC_DP4_5 0x0834 143*4882a593Smuzhiyun #define ATMEL_LCDC_DP6_7 0x0838 144*4882a593Smuzhiyun #define ATMEL_LCDC_DP1_2_VAL (0xff) 145*4882a593Smuzhiyun #define ATMEL_LCDC_DP4_7_VAL (0xfffffff) 146*4882a593Smuzhiyun #define ATMEL_LCDC_DP3_5_VAL (0xfffff) 147*4882a593Smuzhiyun #define ATMEL_LCDC_DP2_3_VAL (0xfff) 148*4882a593Smuzhiyun #define ATMEL_LCDC_DP5_7_VAL (0xfffffff) 149*4882a593Smuzhiyun #define ATMEL_LCDC_DP3_4_VAL (0xffff) 150*4882a593Smuzhiyun #define ATMEL_LCDC_DP4_5_VAL (0xfffff) 151*4882a593Smuzhiyun #define ATMEL_LCDC_DP6_7_VAL (0xfffffff) 152*4882a593Smuzhiyun 153*4882a593Smuzhiyun #define ATMEL_LCDC_PWRCON 0x083c 154*4882a593Smuzhiyun #define ATMEL_LCDC_PWR (1 << 0) 155*4882a593Smuzhiyun #define ATMEL_LCDC_GUARDT_OFFSET 1 156*4882a593Smuzhiyun #define ATMEL_LCDC_GUARDT (0x7f << ATMEL_LCDC_GUARDT_OFFSET) 157*4882a593Smuzhiyun #define ATMEL_LCDC_BUSY (1 << 31) 158*4882a593Smuzhiyun 159*4882a593Smuzhiyun #define ATMEL_LCDC_CONTRAST_CTR 0x0840 160*4882a593Smuzhiyun #define ATMEL_LCDC_PS (3 << 0) 161*4882a593Smuzhiyun #define ATMEL_LCDC_PS_DIV1 (0 << 0) 162*4882a593Smuzhiyun #define ATMEL_LCDC_PS_DIV2 (1 << 0) 163*4882a593Smuzhiyun #define ATMEL_LCDC_PS_DIV4 (2 << 0) 164*4882a593Smuzhiyun #define ATMEL_LCDC_PS_DIV8 (3 << 0) 165*4882a593Smuzhiyun #define ATMEL_LCDC_POL (1 << 2) 166*4882a593Smuzhiyun #define ATMEL_LCDC_POL_NEGATIVE (0 << 2) 167*4882a593Smuzhiyun #define ATMEL_LCDC_POL_POSITIVE (1 << 2) 168*4882a593Smuzhiyun #define ATMEL_LCDC_ENA (1 << 3) 169*4882a593Smuzhiyun #define ATMEL_LCDC_ENA_PWMDISABLE (0 << 3) 170*4882a593Smuzhiyun #define ATMEL_LCDC_ENA_PWMENABLE (1 << 3) 171*4882a593Smuzhiyun 172*4882a593Smuzhiyun #define ATMEL_LCDC_CONTRAST_VAL 0x0844 173*4882a593Smuzhiyun #define ATMEL_LCDC_CVAL (0xff) 174*4882a593Smuzhiyun 175*4882a593Smuzhiyun #define ATMEL_LCDC_IER 0x0848 176*4882a593Smuzhiyun #define ATMEL_LCDC_IDR 0x084c 177*4882a593Smuzhiyun #define ATMEL_LCDC_IMR 0x0850 178*4882a593Smuzhiyun #define ATMEL_LCDC_ISR 0x0854 179*4882a593Smuzhiyun #define ATMEL_LCDC_ICR 0x0858 180*4882a593Smuzhiyun #define ATMEL_LCDC_LNI (1 << 0) 181*4882a593Smuzhiyun #define ATMEL_LCDC_LSTLNI (1 << 1) 182*4882a593Smuzhiyun #define ATMEL_LCDC_EOFI (1 << 2) 183*4882a593Smuzhiyun #define ATMEL_LCDC_UFLWI (1 << 4) 184*4882a593Smuzhiyun #define ATMEL_LCDC_OWRI (1 << 5) 185*4882a593Smuzhiyun #define ATMEL_LCDC_MERI (1 << 6) 186*4882a593Smuzhiyun 187*4882a593Smuzhiyun #define ATMEL_LCDC_LUT(n) (0x0c00 + ((n)*4)) 188*4882a593Smuzhiyun 189*4882a593Smuzhiyun #endif /* __ATMEL_LCDC_H__ */ 190