1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * snd_sst_tokens.h - Intel SST tokens definition 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Copyright (C) 2016 Intel Corp 6*4882a593Smuzhiyun * Author: Shreyas NC <shreyas.nc@intel.com> 7*4882a593Smuzhiyun * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 8*4882a593Smuzhiyun * 9*4882a593Smuzhiyun * This program is free software; you can redistribute it and/or modify 10*4882a593Smuzhiyun * it under the terms of the GNU General Public License as version 2, as 11*4882a593Smuzhiyun * published by the Free Software Foundation. 12*4882a593Smuzhiyun * 13*4882a593Smuzhiyun * This program is distributed in the hope that it will be useful, but 14*4882a593Smuzhiyun * WITHOUT ANY WARRANTY; without even the implied warranty of 15*4882a593Smuzhiyun * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 16*4882a593Smuzhiyun * General Public License for more details. 17*4882a593Smuzhiyun */ 18*4882a593Smuzhiyun #ifndef __SND_SST_TOKENS_H__ 19*4882a593Smuzhiyun #define __SND_SST_TOKENS_H__ 20*4882a593Smuzhiyun 21*4882a593Smuzhiyun /** 22*4882a593Smuzhiyun * %SKL_TKN_UUID: Module UUID 23*4882a593Smuzhiyun * 24*4882a593Smuzhiyun * %SKL_TKN_U8_BLOCK_TYPE: Type of the private data block.Can be: 25*4882a593Smuzhiyun * tuples, bytes, short and words 26*4882a593Smuzhiyun * 27*4882a593Smuzhiyun * %SKL_TKN_U8_IN_PIN_TYPE: Input pin type, 28*4882a593Smuzhiyun * homogenous=0, heterogenous=1 29*4882a593Smuzhiyun * 30*4882a593Smuzhiyun * %SKL_TKN_U8_OUT_PIN_TYPE: Output pin type, 31*4882a593Smuzhiyun * homogenous=0, heterogenous=1 32*4882a593Smuzhiyun * %SKL_TKN_U8_DYN_IN_PIN: Configure Input pin dynamically 33*4882a593Smuzhiyun * if true 34*4882a593Smuzhiyun * 35*4882a593Smuzhiyun * %SKL_TKN_U8_DYN_OUT_PIN: Configure Output pin dynamically 36*4882a593Smuzhiyun * if true 37*4882a593Smuzhiyun * 38*4882a593Smuzhiyun * %SKL_TKN_U8_IN_QUEUE_COUNT: Store the number of Input pins 39*4882a593Smuzhiyun * 40*4882a593Smuzhiyun * %SKL_TKN_U8_OUT_QUEUE_COUNT: Store the number of Output pins 41*4882a593Smuzhiyun * 42*4882a593Smuzhiyun * %SKL_TKN_U8_TIME_SLOT: TDM slot number 43*4882a593Smuzhiyun * 44*4882a593Smuzhiyun * %SKL_TKN_U8_CORE_ID: Stores module affinity value.Can take 45*4882a593Smuzhiyun * the values: 46*4882a593Smuzhiyun * SKL_AFFINITY_CORE_0 = 0, 47*4882a593Smuzhiyun * SKL_AFFINITY_CORE_1, 48*4882a593Smuzhiyun * SKL_AFFINITY_CORE_MAX 49*4882a593Smuzhiyun * 50*4882a593Smuzhiyun * %SKL_TKN_U8_MOD_TYPE: Module type value. 51*4882a593Smuzhiyun * 52*4882a593Smuzhiyun * %SKL_TKN_U8_CONN_TYPE: Module connection type can be a FE, 53*4882a593Smuzhiyun * BE or NONE as defined : 54*4882a593Smuzhiyun * SKL_PIPE_CONN_TYPE_NONE = 0, 55*4882a593Smuzhiyun * SKL_PIPE_CONN_TYPE_FE = 1 (HOST_DMA) 56*4882a593Smuzhiyun * SKL_PIPE_CONN_TYPE_BE = 2 (LINK_DMA) 57*4882a593Smuzhiyun * 58*4882a593Smuzhiyun * %SKL_TKN_U8_DEV_TYPE: Type of device to which the module is 59*4882a593Smuzhiyun * connected 60*4882a593Smuzhiyun * Can take the values: 61*4882a593Smuzhiyun * SKL_DEVICE_BT = 0x0, 62*4882a593Smuzhiyun * SKL_DEVICE_DMIC = 0x1, 63*4882a593Smuzhiyun * SKL_DEVICE_I2S = 0x2, 64*4882a593Smuzhiyun * SKL_DEVICE_SLIMBUS = 0x3, 65*4882a593Smuzhiyun * SKL_DEVICE_HDALINK = 0x4, 66*4882a593Smuzhiyun * SKL_DEVICE_HDAHOST = 0x5, 67*4882a593Smuzhiyun * SKL_DEVICE_NONE 68*4882a593Smuzhiyun * 69*4882a593Smuzhiyun * %SKL_TKN_U8_HW_CONN_TYPE: Connection type of the HW to which the 70*4882a593Smuzhiyun * module is connected 71*4882a593Smuzhiyun * SKL_CONN_NONE = 0, 72*4882a593Smuzhiyun * SKL_CONN_SOURCE = 1, 73*4882a593Smuzhiyun * SKL_CONN_SINK = 2 74*4882a593Smuzhiyun * 75*4882a593Smuzhiyun * %SKL_TKN_U16_PIN_INST_ID: Stores the pin instance id 76*4882a593Smuzhiyun * 77*4882a593Smuzhiyun * %SKL_TKN_U16_MOD_INST_ID: Stores the mdule instance id 78*4882a593Smuzhiyun * 79*4882a593Smuzhiyun * %SKL_TKN_U32_MAX_MCPS: Module max mcps value 80*4882a593Smuzhiyun * 81*4882a593Smuzhiyun * %SKL_TKN_U32_MEM_PAGES: Module resource pages 82*4882a593Smuzhiyun * 83*4882a593Smuzhiyun * %SKL_TKN_U32_OBS: Stores Output Buffer size 84*4882a593Smuzhiyun * 85*4882a593Smuzhiyun * %SKL_TKN_U32_IBS: Stores input buffer size 86*4882a593Smuzhiyun * 87*4882a593Smuzhiyun * %SKL_TKN_U32_VBUS_ID: Module VBUS_ID. PDM=0, SSP0=0, 88*4882a593Smuzhiyun * SSP1=1,SSP2=2, 89*4882a593Smuzhiyun * SSP3=3, SSP4=4, 90*4882a593Smuzhiyun * SSP5=5, SSP6=6,INVALID 91*4882a593Smuzhiyun * 92*4882a593Smuzhiyun * %SKL_TKN_U32_PARAMS_FIXUP: Module Params fixup mask 93*4882a593Smuzhiyun * %SKL_TKN_U32_CONVERTER: Module params converter mask 94*4882a593Smuzhiyun * %SKL_TKN_U32_PIPE_ID: Stores the pipe id 95*4882a593Smuzhiyun * 96*4882a593Smuzhiyun * %SKL_TKN_U32_PIPE_CONN_TYPE: Type of the token to which the pipe is 97*4882a593Smuzhiyun * connected to. It can be 98*4882a593Smuzhiyun * SKL_PIPE_CONN_TYPE_NONE = 0, 99*4882a593Smuzhiyun * SKL_PIPE_CONN_TYPE_FE = 1 (HOST_DMA), 100*4882a593Smuzhiyun * SKL_PIPE_CONN_TYPE_BE = 2 (LINK_DMA), 101*4882a593Smuzhiyun * 102*4882a593Smuzhiyun * %SKL_TKN_U32_PIPE_PRIORITY: Pipe priority value 103*4882a593Smuzhiyun * %SKL_TKN_U32_PIPE_MEM_PGS: Pipe resource pages 104*4882a593Smuzhiyun * 105*4882a593Smuzhiyun * %SKL_TKN_U32_DIR_PIN_COUNT: Value for the direction to set input/output 106*4882a593Smuzhiyun * formats and the pin count. 107*4882a593Smuzhiyun * The first 4 bits have the direction 108*4882a593Smuzhiyun * value and the next 4 have 109*4882a593Smuzhiyun * the pin count value. 110*4882a593Smuzhiyun * SKL_DIR_IN = 0, SKL_DIR_OUT = 1. 111*4882a593Smuzhiyun * The input and output formats 112*4882a593Smuzhiyun * share the same set of tokens 113*4882a593Smuzhiyun * with the distinction between input 114*4882a593Smuzhiyun * and output made by reading direction 115*4882a593Smuzhiyun * token. 116*4882a593Smuzhiyun * 117*4882a593Smuzhiyun * %SKL_TKN_U32_FMT_CH: Supported channel count 118*4882a593Smuzhiyun * 119*4882a593Smuzhiyun * %SKL_TKN_U32_FMT_FREQ: Supported frequency/sample rate 120*4882a593Smuzhiyun * 121*4882a593Smuzhiyun * %SKL_TKN_U32_FMT_BIT_DEPTH: Supported container size 122*4882a593Smuzhiyun * 123*4882a593Smuzhiyun * %SKL_TKN_U32_FMT_SAMPLE_SIZE:Number of samples in the container 124*4882a593Smuzhiyun * 125*4882a593Smuzhiyun * %SKL_TKN_U32_FMT_CH_CONFIG: Supported channel configurations for the 126*4882a593Smuzhiyun * input/output. 127*4882a593Smuzhiyun * 128*4882a593Smuzhiyun * %SKL_TKN_U32_FMT_INTERLEAVE: Interleaving style which can be per 129*4882a593Smuzhiyun * channel or per sample. The values can be : 130*4882a593Smuzhiyun * SKL_INTERLEAVING_PER_CHANNEL = 0, 131*4882a593Smuzhiyun * SKL_INTERLEAVING_PER_SAMPLE = 1, 132*4882a593Smuzhiyun * 133*4882a593Smuzhiyun * %SKL_TKN_U32_FMT_SAMPLE_TYPE: 134*4882a593Smuzhiyun * Specifies the sample type. Can take the 135*4882a593Smuzhiyun * values: SKL_SAMPLE_TYPE_INT_MSB = 0, 136*4882a593Smuzhiyun * SKL_SAMPLE_TYPE_INT_LSB = 1, 137*4882a593Smuzhiyun * SKL_SAMPLE_TYPE_INT_SIGNED = 2, 138*4882a593Smuzhiyun * SKL_SAMPLE_TYPE_INT_UNSIGNED = 3, 139*4882a593Smuzhiyun * SKL_SAMPLE_TYPE_FLOAT = 4 140*4882a593Smuzhiyun * 141*4882a593Smuzhiyun * %SKL_TKN_U32_CH_MAP: Channel map values 142*4882a593Smuzhiyun * %SKL_TKN_U32_MOD_SET_PARAMS: It can take these values: 143*4882a593Smuzhiyun * SKL_PARAM_DEFAULT, SKL_PARAM_INIT, 144*4882a593Smuzhiyun * SKL_PARAM_SET, SKL_PARAM_BIND 145*4882a593Smuzhiyun * 146*4882a593Smuzhiyun * %SKL_TKN_U32_MOD_PARAM_ID: ID of the module params 147*4882a593Smuzhiyun * 148*4882a593Smuzhiyun * %SKL_TKN_U32_CAPS_SET_PARAMS: 149*4882a593Smuzhiyun * Set params value 150*4882a593Smuzhiyun * 151*4882a593Smuzhiyun * %SKL_TKN_U32_CAPS_PARAMS_ID: Params ID 152*4882a593Smuzhiyun * 153*4882a593Smuzhiyun * %SKL_TKN_U32_CAPS_SIZE: Caps size 154*4882a593Smuzhiyun * 155*4882a593Smuzhiyun * %SKL_TKN_U32_PROC_DOMAIN: Specify processing domain 156*4882a593Smuzhiyun * 157*4882a593Smuzhiyun * %SKL_TKN_U32_LIB_COUNT: Specifies the number of libraries 158*4882a593Smuzhiyun * 159*4882a593Smuzhiyun * %SKL_TKN_STR_LIB_NAME: Specifies the library name 160*4882a593Smuzhiyun * 161*4882a593Smuzhiyun * %SKL_TKN_U32_PMODE: Specifies the power mode for pipe 162*4882a593Smuzhiyun * 163*4882a593Smuzhiyun * %SKL_TKL_U32_D0I3_CAPS: Specifies the D0i3 capability for module 164*4882a593Smuzhiyun * 165*4882a593Smuzhiyun * %SKL_TKN_U32_DMA_BUF_SIZE: DMA buffer size in millisec 166*4882a593Smuzhiyun * 167*4882a593Smuzhiyun * %SKL_TKN_U32_PIPE_DIR: Specifies pipe direction. Can be 168*4882a593Smuzhiyun * playback/capture. 169*4882a593Smuzhiyun * 170*4882a593Smuzhiyun * %SKL_TKN_U32_NUM_CONFIGS: Number of pipe configs 171*4882a593Smuzhiyun * 172*4882a593Smuzhiyun * %SKL_TKN_U32_PATH_MEM_PGS: Size of memory (in pages) required for pipeline 173*4882a593Smuzhiyun * and its data 174*4882a593Smuzhiyun * 175*4882a593Smuzhiyun * %SKL_TKN_U32_PIPE_CONFIG_ID: Config id for the modules in the pipe 176*4882a593Smuzhiyun * and PCM params supported by that pipe 177*4882a593Smuzhiyun * config. This is used as index to fill 178*4882a593Smuzhiyun * up the pipe config and module config 179*4882a593Smuzhiyun * structure. 180*4882a593Smuzhiyun * 181*4882a593Smuzhiyun * %SKL_TKN_U32_CFG_FREQ: 182*4882a593Smuzhiyun * %SKL_TKN_U8_CFG_CHAN: 183*4882a593Smuzhiyun * %SKL_TKN_U8_CFG_BPS: PCM params (freq, channels, bits per sample) 184*4882a593Smuzhiyun * supported for each of the pipe configs. 185*4882a593Smuzhiyun * 186*4882a593Smuzhiyun * %SKL_TKN_CFG_MOD_RES_ID: Module's resource index for each of the 187*4882a593Smuzhiyun * pipe config 188*4882a593Smuzhiyun * 189*4882a593Smuzhiyun * %SKL_TKN_CFG_MOD_FMT_ID: Module's interface index for each of the 190*4882a593Smuzhiyun * pipe config 191*4882a593Smuzhiyun * 192*4882a593Smuzhiyun * %SKL_TKN_U8_NUM_MOD: Number of modules in the manifest 193*4882a593Smuzhiyun * 194*4882a593Smuzhiyun * %SKL_TKN_MM_U8_MOD_IDX: Current index of the module in the manifest 195*4882a593Smuzhiyun * 196*4882a593Smuzhiyun * %SKL_TKN_MM_U8_NUM_RES: Number of resources for the module 197*4882a593Smuzhiyun * 198*4882a593Smuzhiyun * %SKL_TKN_MM_U8_NUM_INTF: Number of interfaces for the module 199*4882a593Smuzhiyun * 200*4882a593Smuzhiyun * %SKL_TKN_MM_U32_RES_ID: Resource index for the resource info to 201*4882a593Smuzhiyun * be filled into. 202*4882a593Smuzhiyun * A module can support multiple resource 203*4882a593Smuzhiyun * configuration and is represnted as a 204*4882a593Smuzhiyun * resource table. This index is used to 205*4882a593Smuzhiyun * fill information into appropriate index. 206*4882a593Smuzhiyun * 207*4882a593Smuzhiyun * %SKL_TKN_MM_U32_CPS: DSP cycles per second 208*4882a593Smuzhiyun * 209*4882a593Smuzhiyun * %SKL_TKN_MM_U32_DMA_SIZE: Allocated buffer size for gateway DMA 210*4882a593Smuzhiyun * 211*4882a593Smuzhiyun * %SKL_TKN_MM_U32_CPC: DSP cycles allocated per frame 212*4882a593Smuzhiyun * 213*4882a593Smuzhiyun * %SKL_TKN_MM_U32_RES_PIN_ID: Resource pin index in the module 214*4882a593Smuzhiyun * 215*4882a593Smuzhiyun * %SKL_TKN_MM_U32_INTF_PIN_ID: Interface index in the module 216*4882a593Smuzhiyun * 217*4882a593Smuzhiyun * %SKL_TKN_MM_U32_PIN_BUF: Buffer size of the module pin 218*4882a593Smuzhiyun * 219*4882a593Smuzhiyun * %SKL_TKN_MM_U32_FMT_ID: Format index for each of the interface/ 220*4882a593Smuzhiyun * format information to be filled into. 221*4882a593Smuzhiyun * 222*4882a593Smuzhiyun * %SKL_TKN_MM_U32_NUM_IN_FMT: Number of input formats 223*4882a593Smuzhiyun * %SKL_TKN_MM_U32_NUM_OUT_FMT: Number of output formats 224*4882a593Smuzhiyun * 225*4882a593Smuzhiyun * %SKL_TKN_U32_ASTATE_IDX: Table Index for the A-State entry to be filled 226*4882a593Smuzhiyun * with kcps and clock source 227*4882a593Smuzhiyun * 228*4882a593Smuzhiyun * %SKL_TKN_U32_ASTATE_COUNT: Number of valid entries in A-State table 229*4882a593Smuzhiyun * 230*4882a593Smuzhiyun * %SKL_TKN_U32_ASTATE_KCPS: Specifies the core load threshold (in kilo 231*4882a593Smuzhiyun * cycles per second) below which DSP is clocked 232*4882a593Smuzhiyun * from source specified by clock source. 233*4882a593Smuzhiyun * 234*4882a593Smuzhiyun * %SKL_TKN_U32_ASTATE_CLK_SRC: Clock source for A-State entry 235*4882a593Smuzhiyun * 236*4882a593Smuzhiyun * module_id and loadable flags dont have tokens as these values will be 237*4882a593Smuzhiyun * read from the DSP FW manifest 238*4882a593Smuzhiyun * 239*4882a593Smuzhiyun * Tokens defined can be used either in the manifest or widget private data. 240*4882a593Smuzhiyun * 241*4882a593Smuzhiyun * SKL_TKN_MM is used as a suffix for all tokens that represent 242*4882a593Smuzhiyun * module data in the manifest. 243*4882a593Smuzhiyun */ 244*4882a593Smuzhiyun enum SKL_TKNS { 245*4882a593Smuzhiyun SKL_TKN_UUID = 1, 246*4882a593Smuzhiyun SKL_TKN_U8_NUM_BLOCKS, 247*4882a593Smuzhiyun SKL_TKN_U8_BLOCK_TYPE, 248*4882a593Smuzhiyun SKL_TKN_U8_IN_PIN_TYPE, 249*4882a593Smuzhiyun SKL_TKN_U8_OUT_PIN_TYPE, 250*4882a593Smuzhiyun SKL_TKN_U8_DYN_IN_PIN, 251*4882a593Smuzhiyun SKL_TKN_U8_DYN_OUT_PIN, 252*4882a593Smuzhiyun SKL_TKN_U8_IN_QUEUE_COUNT, 253*4882a593Smuzhiyun SKL_TKN_U8_OUT_QUEUE_COUNT, 254*4882a593Smuzhiyun SKL_TKN_U8_TIME_SLOT, 255*4882a593Smuzhiyun SKL_TKN_U8_CORE_ID, 256*4882a593Smuzhiyun SKL_TKN_U8_MOD_TYPE, 257*4882a593Smuzhiyun SKL_TKN_U8_CONN_TYPE, 258*4882a593Smuzhiyun SKL_TKN_U8_DEV_TYPE, 259*4882a593Smuzhiyun SKL_TKN_U8_HW_CONN_TYPE, 260*4882a593Smuzhiyun SKL_TKN_U16_MOD_INST_ID, 261*4882a593Smuzhiyun SKL_TKN_U16_BLOCK_SIZE, 262*4882a593Smuzhiyun SKL_TKN_U32_MAX_MCPS, 263*4882a593Smuzhiyun SKL_TKN_U32_MEM_PAGES, 264*4882a593Smuzhiyun SKL_TKN_U32_OBS, 265*4882a593Smuzhiyun SKL_TKN_U32_IBS, 266*4882a593Smuzhiyun SKL_TKN_U32_VBUS_ID, 267*4882a593Smuzhiyun SKL_TKN_U32_PARAMS_FIXUP, 268*4882a593Smuzhiyun SKL_TKN_U32_CONVERTER, 269*4882a593Smuzhiyun SKL_TKN_U32_PIPE_ID, 270*4882a593Smuzhiyun SKL_TKN_U32_PIPE_CONN_TYPE, 271*4882a593Smuzhiyun SKL_TKN_U32_PIPE_PRIORITY, 272*4882a593Smuzhiyun SKL_TKN_U32_PIPE_MEM_PGS, 273*4882a593Smuzhiyun SKL_TKN_U32_DIR_PIN_COUNT, 274*4882a593Smuzhiyun SKL_TKN_U32_FMT_CH, 275*4882a593Smuzhiyun SKL_TKN_U32_FMT_FREQ, 276*4882a593Smuzhiyun SKL_TKN_U32_FMT_BIT_DEPTH, 277*4882a593Smuzhiyun SKL_TKN_U32_FMT_SAMPLE_SIZE, 278*4882a593Smuzhiyun SKL_TKN_U32_FMT_CH_CONFIG, 279*4882a593Smuzhiyun SKL_TKN_U32_FMT_INTERLEAVE, 280*4882a593Smuzhiyun SKL_TKN_U32_FMT_SAMPLE_TYPE, 281*4882a593Smuzhiyun SKL_TKN_U32_FMT_CH_MAP, 282*4882a593Smuzhiyun SKL_TKN_U32_PIN_MOD_ID, 283*4882a593Smuzhiyun SKL_TKN_U32_PIN_INST_ID, 284*4882a593Smuzhiyun SKL_TKN_U32_MOD_SET_PARAMS, 285*4882a593Smuzhiyun SKL_TKN_U32_MOD_PARAM_ID, 286*4882a593Smuzhiyun SKL_TKN_U32_CAPS_SET_PARAMS, 287*4882a593Smuzhiyun SKL_TKN_U32_CAPS_PARAMS_ID, 288*4882a593Smuzhiyun SKL_TKN_U32_CAPS_SIZE, 289*4882a593Smuzhiyun SKL_TKN_U32_PROC_DOMAIN, 290*4882a593Smuzhiyun SKL_TKN_U32_LIB_COUNT, 291*4882a593Smuzhiyun SKL_TKN_STR_LIB_NAME, 292*4882a593Smuzhiyun SKL_TKN_U32_PMODE, 293*4882a593Smuzhiyun SKL_TKL_U32_D0I3_CAPS, /* Typo added at v4.10 */ 294*4882a593Smuzhiyun SKL_TKN_U32_D0I3_CAPS = SKL_TKL_U32_D0I3_CAPS, 295*4882a593Smuzhiyun SKL_TKN_U32_DMA_BUF_SIZE, 296*4882a593Smuzhiyun 297*4882a593Smuzhiyun SKL_TKN_U32_PIPE_DIRECTION, 298*4882a593Smuzhiyun SKL_TKN_U32_PIPE_CONFIG_ID, 299*4882a593Smuzhiyun SKL_TKN_U32_NUM_CONFIGS, 300*4882a593Smuzhiyun SKL_TKN_U32_PATH_MEM_PGS, 301*4882a593Smuzhiyun 302*4882a593Smuzhiyun SKL_TKN_U32_CFG_FREQ, 303*4882a593Smuzhiyun SKL_TKN_U8_CFG_CHAN, 304*4882a593Smuzhiyun SKL_TKN_U8_CFG_BPS, 305*4882a593Smuzhiyun SKL_TKN_CFG_MOD_RES_ID, 306*4882a593Smuzhiyun SKL_TKN_CFG_MOD_FMT_ID, 307*4882a593Smuzhiyun SKL_TKN_U8_NUM_MOD, 308*4882a593Smuzhiyun 309*4882a593Smuzhiyun SKL_TKN_MM_U8_MOD_IDX, 310*4882a593Smuzhiyun SKL_TKN_MM_U8_NUM_RES, 311*4882a593Smuzhiyun SKL_TKN_MM_U8_NUM_INTF, 312*4882a593Smuzhiyun SKL_TKN_MM_U32_RES_ID, 313*4882a593Smuzhiyun SKL_TKN_MM_U32_CPS, 314*4882a593Smuzhiyun SKL_TKN_MM_U32_DMA_SIZE, 315*4882a593Smuzhiyun SKL_TKN_MM_U32_CPC, 316*4882a593Smuzhiyun SKL_TKN_MM_U32_RES_PIN_ID, 317*4882a593Smuzhiyun SKL_TKN_MM_U32_INTF_PIN_ID, 318*4882a593Smuzhiyun SKL_TKN_MM_U32_PIN_BUF, 319*4882a593Smuzhiyun SKL_TKN_MM_U32_FMT_ID, 320*4882a593Smuzhiyun SKL_TKN_MM_U32_NUM_IN_FMT, 321*4882a593Smuzhiyun SKL_TKN_MM_U32_NUM_OUT_FMT, 322*4882a593Smuzhiyun 323*4882a593Smuzhiyun SKL_TKN_U32_ASTATE_IDX, 324*4882a593Smuzhiyun SKL_TKN_U32_ASTATE_COUNT, 325*4882a593Smuzhiyun SKL_TKN_U32_ASTATE_KCPS, 326*4882a593Smuzhiyun SKL_TKN_U32_ASTATE_CLK_SRC, 327*4882a593Smuzhiyun SKL_TKN_MAX = SKL_TKN_U32_ASTATE_CLK_SRC, 328*4882a593Smuzhiyun }; 329*4882a593Smuzhiyun 330*4882a593Smuzhiyun #endif 331