1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0+ WITH Linux-syscall-note */ 2*4882a593Smuzhiyun #ifndef __SOUND_HDSPM_H 3*4882a593Smuzhiyun #define __SOUND_HDSPM_H 4*4882a593Smuzhiyun /* 5*4882a593Smuzhiyun * Copyright (C) 2003 Winfried Ritsch (IEM) 6*4882a593Smuzhiyun * based on hdsp.h from Thomas Charbonnel (thomas@undata.org) 7*4882a593Smuzhiyun * 8*4882a593Smuzhiyun * 9*4882a593Smuzhiyun * This program is free software; you can redistribute it and/or modify 10*4882a593Smuzhiyun * it under the terms of the GNU General Public License as published by 11*4882a593Smuzhiyun * the Free Software Foundation; either version 2 of the License, or 12*4882a593Smuzhiyun * (at your option) any later version. 13*4882a593Smuzhiyun * 14*4882a593Smuzhiyun * This program is distributed in the hope that it will be useful, 15*4882a593Smuzhiyun * but WITHOUT ANY WARRANTY; without even the implied warranty of 16*4882a593Smuzhiyun * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17*4882a593Smuzhiyun * GNU General Public License for more details. 18*4882a593Smuzhiyun * 19*4882a593Smuzhiyun * You should have received a copy of the GNU General Public License 20*4882a593Smuzhiyun * along with this program; if not, write to the Free Software 21*4882a593Smuzhiyun * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. 22*4882a593Smuzhiyun */ 23*4882a593Smuzhiyun 24*4882a593Smuzhiyun #ifdef __linux__ 25*4882a593Smuzhiyun #include <linux/types.h> 26*4882a593Smuzhiyun #endif 27*4882a593Smuzhiyun 28*4882a593Smuzhiyun /* Maximum channels is 64 even on 56Mode you have 64playbacks to matrix */ 29*4882a593Smuzhiyun #define HDSPM_MAX_CHANNELS 64 30*4882a593Smuzhiyun 31*4882a593Smuzhiyun enum hdspm_io_type { 32*4882a593Smuzhiyun MADI, 33*4882a593Smuzhiyun MADIface, 34*4882a593Smuzhiyun AIO, 35*4882a593Smuzhiyun AES32, 36*4882a593Smuzhiyun RayDAT 37*4882a593Smuzhiyun }; 38*4882a593Smuzhiyun 39*4882a593Smuzhiyun enum hdspm_speed { 40*4882a593Smuzhiyun ss, 41*4882a593Smuzhiyun ds, 42*4882a593Smuzhiyun qs 43*4882a593Smuzhiyun }; 44*4882a593Smuzhiyun 45*4882a593Smuzhiyun /* -------------------- IOCTL Peak/RMS Meters -------------------- */ 46*4882a593Smuzhiyun 47*4882a593Smuzhiyun struct hdspm_peak_rms { 48*4882a593Smuzhiyun __u32 input_peaks[64]; 49*4882a593Smuzhiyun __u32 playback_peaks[64]; 50*4882a593Smuzhiyun __u32 output_peaks[64]; 51*4882a593Smuzhiyun 52*4882a593Smuzhiyun __u64 input_rms[64]; 53*4882a593Smuzhiyun __u64 playback_rms[64]; 54*4882a593Smuzhiyun __u64 output_rms[64]; 55*4882a593Smuzhiyun 56*4882a593Smuzhiyun __u8 speed; /* enum {ss, ds, qs} */ 57*4882a593Smuzhiyun int status2; 58*4882a593Smuzhiyun }; 59*4882a593Smuzhiyun 60*4882a593Smuzhiyun #define SNDRV_HDSPM_IOCTL_GET_PEAK_RMS \ 61*4882a593Smuzhiyun _IOR('H', 0x42, struct hdspm_peak_rms) 62*4882a593Smuzhiyun 63*4882a593Smuzhiyun /* ------------ CONFIG block IOCTL ---------------------- */ 64*4882a593Smuzhiyun 65*4882a593Smuzhiyun struct hdspm_config { 66*4882a593Smuzhiyun unsigned char pref_sync_ref; 67*4882a593Smuzhiyun unsigned char wordclock_sync_check; 68*4882a593Smuzhiyun unsigned char madi_sync_check; 69*4882a593Smuzhiyun unsigned int system_sample_rate; 70*4882a593Smuzhiyun unsigned int autosync_sample_rate; 71*4882a593Smuzhiyun unsigned char system_clock_mode; 72*4882a593Smuzhiyun unsigned char clock_source; 73*4882a593Smuzhiyun unsigned char autosync_ref; 74*4882a593Smuzhiyun unsigned char line_out; 75*4882a593Smuzhiyun unsigned int passthru; 76*4882a593Smuzhiyun unsigned int analog_out; 77*4882a593Smuzhiyun }; 78*4882a593Smuzhiyun 79*4882a593Smuzhiyun #define SNDRV_HDSPM_IOCTL_GET_CONFIG \ 80*4882a593Smuzhiyun _IOR('H', 0x41, struct hdspm_config) 81*4882a593Smuzhiyun 82*4882a593Smuzhiyun /* 83*4882a593Smuzhiyun * If there's a TCO (TimeCode Option) board installed, 84*4882a593Smuzhiyun * there are further options and status data available. 85*4882a593Smuzhiyun * The hdspm_ltc structure contains the current SMPTE 86*4882a593Smuzhiyun * timecode and some status information and can be 87*4882a593Smuzhiyun * obtained via SNDRV_HDSPM_IOCTL_GET_LTC or in the 88*4882a593Smuzhiyun * hdspm_status struct. 89*4882a593Smuzhiyun */ 90*4882a593Smuzhiyun 91*4882a593Smuzhiyun enum hdspm_ltc_format { 92*4882a593Smuzhiyun format_invalid, 93*4882a593Smuzhiyun fps_24, 94*4882a593Smuzhiyun fps_25, 95*4882a593Smuzhiyun fps_2997, 96*4882a593Smuzhiyun fps_30 97*4882a593Smuzhiyun }; 98*4882a593Smuzhiyun 99*4882a593Smuzhiyun enum hdspm_ltc_frame { 100*4882a593Smuzhiyun frame_invalid, 101*4882a593Smuzhiyun drop_frame, 102*4882a593Smuzhiyun full_frame 103*4882a593Smuzhiyun }; 104*4882a593Smuzhiyun 105*4882a593Smuzhiyun enum hdspm_ltc_input_format { 106*4882a593Smuzhiyun ntsc, 107*4882a593Smuzhiyun pal, 108*4882a593Smuzhiyun no_video 109*4882a593Smuzhiyun }; 110*4882a593Smuzhiyun 111*4882a593Smuzhiyun struct hdspm_ltc { 112*4882a593Smuzhiyun unsigned int ltc; 113*4882a593Smuzhiyun 114*4882a593Smuzhiyun enum hdspm_ltc_format format; 115*4882a593Smuzhiyun enum hdspm_ltc_frame frame; 116*4882a593Smuzhiyun enum hdspm_ltc_input_format input_format; 117*4882a593Smuzhiyun }; 118*4882a593Smuzhiyun 119*4882a593Smuzhiyun #define SNDRV_HDSPM_IOCTL_GET_LTC _IOR('H', 0x46, struct hdspm_ltc) 120*4882a593Smuzhiyun 121*4882a593Smuzhiyun /* 122*4882a593Smuzhiyun * The status data reflects the device's current state 123*4882a593Smuzhiyun * as determined by the card's configuration and 124*4882a593Smuzhiyun * connection status. 125*4882a593Smuzhiyun */ 126*4882a593Smuzhiyun 127*4882a593Smuzhiyun enum hdspm_sync { 128*4882a593Smuzhiyun hdspm_sync_no_lock = 0, 129*4882a593Smuzhiyun hdspm_sync_lock = 1, 130*4882a593Smuzhiyun hdspm_sync_sync = 2 131*4882a593Smuzhiyun }; 132*4882a593Smuzhiyun 133*4882a593Smuzhiyun enum hdspm_madi_input { 134*4882a593Smuzhiyun hdspm_input_optical = 0, 135*4882a593Smuzhiyun hdspm_input_coax = 1 136*4882a593Smuzhiyun }; 137*4882a593Smuzhiyun 138*4882a593Smuzhiyun enum hdspm_madi_channel_format { 139*4882a593Smuzhiyun hdspm_format_ch_64 = 0, 140*4882a593Smuzhiyun hdspm_format_ch_56 = 1 141*4882a593Smuzhiyun }; 142*4882a593Smuzhiyun 143*4882a593Smuzhiyun enum hdspm_madi_frame_format { 144*4882a593Smuzhiyun hdspm_frame_48 = 0, 145*4882a593Smuzhiyun hdspm_frame_96 = 1 146*4882a593Smuzhiyun }; 147*4882a593Smuzhiyun 148*4882a593Smuzhiyun enum hdspm_syncsource { 149*4882a593Smuzhiyun syncsource_wc = 0, 150*4882a593Smuzhiyun syncsource_madi = 1, 151*4882a593Smuzhiyun syncsource_tco = 2, 152*4882a593Smuzhiyun syncsource_sync = 3, 153*4882a593Smuzhiyun syncsource_none = 4 154*4882a593Smuzhiyun }; 155*4882a593Smuzhiyun 156*4882a593Smuzhiyun struct hdspm_status { 157*4882a593Smuzhiyun __u8 card_type; /* enum hdspm_io_type */ 158*4882a593Smuzhiyun enum hdspm_syncsource autosync_source; 159*4882a593Smuzhiyun 160*4882a593Smuzhiyun __u64 card_clock; 161*4882a593Smuzhiyun __u32 master_period; 162*4882a593Smuzhiyun 163*4882a593Smuzhiyun union { 164*4882a593Smuzhiyun struct { 165*4882a593Smuzhiyun __u8 sync_wc; /* enum hdspm_sync */ 166*4882a593Smuzhiyun __u8 sync_madi; /* enum hdspm_sync */ 167*4882a593Smuzhiyun __u8 sync_tco; /* enum hdspm_sync */ 168*4882a593Smuzhiyun __u8 sync_in; /* enum hdspm_sync */ 169*4882a593Smuzhiyun __u8 madi_input; /* enum hdspm_madi_input */ 170*4882a593Smuzhiyun __u8 channel_format; /* enum hdspm_madi_channel_format */ 171*4882a593Smuzhiyun __u8 frame_format; /* enum hdspm_madi_frame_format */ 172*4882a593Smuzhiyun } madi; 173*4882a593Smuzhiyun } card_specific; 174*4882a593Smuzhiyun }; 175*4882a593Smuzhiyun 176*4882a593Smuzhiyun #define SNDRV_HDSPM_IOCTL_GET_STATUS \ 177*4882a593Smuzhiyun _IOR('H', 0x47, struct hdspm_status) 178*4882a593Smuzhiyun 179*4882a593Smuzhiyun /* 180*4882a593Smuzhiyun * Get information about the card and its add-ons. 181*4882a593Smuzhiyun */ 182*4882a593Smuzhiyun 183*4882a593Smuzhiyun #define HDSPM_ADDON_TCO 1 184*4882a593Smuzhiyun 185*4882a593Smuzhiyun struct hdspm_version { 186*4882a593Smuzhiyun __u8 card_type; /* enum hdspm_io_type */ 187*4882a593Smuzhiyun char cardname[20]; 188*4882a593Smuzhiyun unsigned int serial; 189*4882a593Smuzhiyun unsigned short firmware_rev; 190*4882a593Smuzhiyun int addons; 191*4882a593Smuzhiyun }; 192*4882a593Smuzhiyun 193*4882a593Smuzhiyun #define SNDRV_HDSPM_IOCTL_GET_VERSION _IOR('H', 0x48, struct hdspm_version) 194*4882a593Smuzhiyun 195*4882a593Smuzhiyun /* ------------- get Matrix Mixer IOCTL --------------- */ 196*4882a593Smuzhiyun 197*4882a593Smuzhiyun /* MADI mixer: 64inputs+64playback in 64outputs = 8192 => *4Byte = 198*4882a593Smuzhiyun * 32768 Bytes 199*4882a593Smuzhiyun */ 200*4882a593Smuzhiyun 201*4882a593Smuzhiyun /* organisation is 64 channelfader in a continuous memory block */ 202*4882a593Smuzhiyun /* equivalent to hardware definition, maybe for future feature of mmap of 203*4882a593Smuzhiyun * them 204*4882a593Smuzhiyun */ 205*4882a593Smuzhiyun /* each of 64 outputs has 64 infader and 64 outfader: 206*4882a593Smuzhiyun Ins to Outs mixer[out].in[in], Outstreams to Outs mixer[out].pb[pb] */ 207*4882a593Smuzhiyun 208*4882a593Smuzhiyun #define HDSPM_MIXER_CHANNELS HDSPM_MAX_CHANNELS 209*4882a593Smuzhiyun 210*4882a593Smuzhiyun struct hdspm_channelfader { 211*4882a593Smuzhiyun unsigned int in[HDSPM_MIXER_CHANNELS]; 212*4882a593Smuzhiyun unsigned int pb[HDSPM_MIXER_CHANNELS]; 213*4882a593Smuzhiyun }; 214*4882a593Smuzhiyun 215*4882a593Smuzhiyun struct hdspm_mixer { 216*4882a593Smuzhiyun struct hdspm_channelfader ch[HDSPM_MIXER_CHANNELS]; 217*4882a593Smuzhiyun }; 218*4882a593Smuzhiyun 219*4882a593Smuzhiyun struct hdspm_mixer_ioctl { 220*4882a593Smuzhiyun struct hdspm_mixer *mixer; 221*4882a593Smuzhiyun }; 222*4882a593Smuzhiyun 223*4882a593Smuzhiyun /* use indirect access due to the limit of ioctl bit size */ 224*4882a593Smuzhiyun #define SNDRV_HDSPM_IOCTL_GET_MIXER _IOR('H', 0x44, struct hdspm_mixer_ioctl) 225*4882a593Smuzhiyun 226*4882a593Smuzhiyun #endif 227