xref: /OK3568_Linux_fs/kernel/include/uapi/rdma/vmw_pvrdma-abi.h (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun /* SPDX-License-Identifier: ((GPL-2.0 WITH Linux-syscall-note) OR BSD-2-Clause) */
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun  * Copyright (c) 2012-2016 VMware, Inc.  All rights reserved.
4*4882a593Smuzhiyun  *
5*4882a593Smuzhiyun  * This program is free software; you can redistribute it and/or
6*4882a593Smuzhiyun  * modify it under the terms of EITHER the GNU General Public License
7*4882a593Smuzhiyun  * version 2 as published by the Free Software Foundation or the BSD
8*4882a593Smuzhiyun  * 2-Clause License. This program is distributed in the hope that it
9*4882a593Smuzhiyun  * will be useful, but WITHOUT ANY WARRANTY; WITHOUT EVEN THE IMPLIED
10*4882a593Smuzhiyun  * WARRANTY OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE.
11*4882a593Smuzhiyun  * See the GNU General Public License version 2 for more details at
12*4882a593Smuzhiyun  * http://www.gnu.org/licenses/old-licenses/gpl-2.0.en.html.
13*4882a593Smuzhiyun  *
14*4882a593Smuzhiyun  * You should have received a copy of the GNU General Public License
15*4882a593Smuzhiyun  * along with this program available in the file COPYING in the main
16*4882a593Smuzhiyun  * directory of this source tree.
17*4882a593Smuzhiyun  *
18*4882a593Smuzhiyun  * The BSD 2-Clause License
19*4882a593Smuzhiyun  *
20*4882a593Smuzhiyun  *     Redistribution and use in source and binary forms, with or
21*4882a593Smuzhiyun  *     without modification, are permitted provided that the following
22*4882a593Smuzhiyun  *     conditions are met:
23*4882a593Smuzhiyun  *
24*4882a593Smuzhiyun  *      - Redistributions of source code must retain the above
25*4882a593Smuzhiyun  *        copyright notice, this list of conditions and the following
26*4882a593Smuzhiyun  *        disclaimer.
27*4882a593Smuzhiyun  *
28*4882a593Smuzhiyun  *      - Redistributions in binary form must reproduce the above
29*4882a593Smuzhiyun  *        copyright notice, this list of conditions and the following
30*4882a593Smuzhiyun  *        disclaimer in the documentation and/or other materials
31*4882a593Smuzhiyun  *        provided with the distribution.
32*4882a593Smuzhiyun  *
33*4882a593Smuzhiyun  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
34*4882a593Smuzhiyun  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
35*4882a593Smuzhiyun  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
36*4882a593Smuzhiyun  * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
37*4882a593Smuzhiyun  * COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
38*4882a593Smuzhiyun  * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
39*4882a593Smuzhiyun  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
40*4882a593Smuzhiyun  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
41*4882a593Smuzhiyun  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
42*4882a593Smuzhiyun  * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
43*4882a593Smuzhiyun  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
44*4882a593Smuzhiyun  * OF THE POSSIBILITY OF SUCH DAMAGE.
45*4882a593Smuzhiyun  */
46*4882a593Smuzhiyun 
47*4882a593Smuzhiyun #ifndef __VMW_PVRDMA_ABI_H__
48*4882a593Smuzhiyun #define __VMW_PVRDMA_ABI_H__
49*4882a593Smuzhiyun 
50*4882a593Smuzhiyun #include <linux/types.h>
51*4882a593Smuzhiyun 
52*4882a593Smuzhiyun #define PVRDMA_UVERBS_ABI_VERSION	3		/* ABI Version. */
53*4882a593Smuzhiyun #define PVRDMA_UAR_HANDLE_MASK		0x00FFFFFF	/* Bottom 24 bits. */
54*4882a593Smuzhiyun #define PVRDMA_UAR_QP_OFFSET		0		/* QP doorbell. */
55*4882a593Smuzhiyun #define PVRDMA_UAR_QP_SEND		(1 << 30)	/* Send bit. */
56*4882a593Smuzhiyun #define PVRDMA_UAR_QP_RECV		(1 << 31)	/* Recv bit. */
57*4882a593Smuzhiyun #define PVRDMA_UAR_CQ_OFFSET		4		/* CQ doorbell. */
58*4882a593Smuzhiyun #define PVRDMA_UAR_CQ_ARM_SOL		(1 << 29)	/* Arm solicited bit. */
59*4882a593Smuzhiyun #define PVRDMA_UAR_CQ_ARM		(1 << 30)	/* Arm bit. */
60*4882a593Smuzhiyun #define PVRDMA_UAR_CQ_POLL		(1 << 31)	/* Poll bit. */
61*4882a593Smuzhiyun #define PVRDMA_UAR_SRQ_OFFSET		8		/* SRQ doorbell. */
62*4882a593Smuzhiyun #define PVRDMA_UAR_SRQ_RECV		(1 << 30)	/* Recv bit. */
63*4882a593Smuzhiyun 
64*4882a593Smuzhiyun enum pvrdma_wr_opcode {
65*4882a593Smuzhiyun 	PVRDMA_WR_RDMA_WRITE,
66*4882a593Smuzhiyun 	PVRDMA_WR_RDMA_WRITE_WITH_IMM,
67*4882a593Smuzhiyun 	PVRDMA_WR_SEND,
68*4882a593Smuzhiyun 	PVRDMA_WR_SEND_WITH_IMM,
69*4882a593Smuzhiyun 	PVRDMA_WR_RDMA_READ,
70*4882a593Smuzhiyun 	PVRDMA_WR_ATOMIC_CMP_AND_SWP,
71*4882a593Smuzhiyun 	PVRDMA_WR_ATOMIC_FETCH_AND_ADD,
72*4882a593Smuzhiyun 	PVRDMA_WR_LSO,
73*4882a593Smuzhiyun 	PVRDMA_WR_SEND_WITH_INV,
74*4882a593Smuzhiyun 	PVRDMA_WR_RDMA_READ_WITH_INV,
75*4882a593Smuzhiyun 	PVRDMA_WR_LOCAL_INV,
76*4882a593Smuzhiyun 	PVRDMA_WR_FAST_REG_MR,
77*4882a593Smuzhiyun 	PVRDMA_WR_MASKED_ATOMIC_CMP_AND_SWP,
78*4882a593Smuzhiyun 	PVRDMA_WR_MASKED_ATOMIC_FETCH_AND_ADD,
79*4882a593Smuzhiyun 	PVRDMA_WR_BIND_MW,
80*4882a593Smuzhiyun 	PVRDMA_WR_REG_SIG_MR,
81*4882a593Smuzhiyun 	PVRDMA_WR_ERROR,
82*4882a593Smuzhiyun };
83*4882a593Smuzhiyun 
84*4882a593Smuzhiyun enum pvrdma_wc_status {
85*4882a593Smuzhiyun 	PVRDMA_WC_SUCCESS,
86*4882a593Smuzhiyun 	PVRDMA_WC_LOC_LEN_ERR,
87*4882a593Smuzhiyun 	PVRDMA_WC_LOC_QP_OP_ERR,
88*4882a593Smuzhiyun 	PVRDMA_WC_LOC_EEC_OP_ERR,
89*4882a593Smuzhiyun 	PVRDMA_WC_LOC_PROT_ERR,
90*4882a593Smuzhiyun 	PVRDMA_WC_WR_FLUSH_ERR,
91*4882a593Smuzhiyun 	PVRDMA_WC_MW_BIND_ERR,
92*4882a593Smuzhiyun 	PVRDMA_WC_BAD_RESP_ERR,
93*4882a593Smuzhiyun 	PVRDMA_WC_LOC_ACCESS_ERR,
94*4882a593Smuzhiyun 	PVRDMA_WC_REM_INV_REQ_ERR,
95*4882a593Smuzhiyun 	PVRDMA_WC_REM_ACCESS_ERR,
96*4882a593Smuzhiyun 	PVRDMA_WC_REM_OP_ERR,
97*4882a593Smuzhiyun 	PVRDMA_WC_RETRY_EXC_ERR,
98*4882a593Smuzhiyun 	PVRDMA_WC_RNR_RETRY_EXC_ERR,
99*4882a593Smuzhiyun 	PVRDMA_WC_LOC_RDD_VIOL_ERR,
100*4882a593Smuzhiyun 	PVRDMA_WC_REM_INV_RD_REQ_ERR,
101*4882a593Smuzhiyun 	PVRDMA_WC_REM_ABORT_ERR,
102*4882a593Smuzhiyun 	PVRDMA_WC_INV_EECN_ERR,
103*4882a593Smuzhiyun 	PVRDMA_WC_INV_EEC_STATE_ERR,
104*4882a593Smuzhiyun 	PVRDMA_WC_FATAL_ERR,
105*4882a593Smuzhiyun 	PVRDMA_WC_RESP_TIMEOUT_ERR,
106*4882a593Smuzhiyun 	PVRDMA_WC_GENERAL_ERR,
107*4882a593Smuzhiyun };
108*4882a593Smuzhiyun 
109*4882a593Smuzhiyun enum pvrdma_wc_opcode {
110*4882a593Smuzhiyun 	PVRDMA_WC_SEND,
111*4882a593Smuzhiyun 	PVRDMA_WC_RDMA_WRITE,
112*4882a593Smuzhiyun 	PVRDMA_WC_RDMA_READ,
113*4882a593Smuzhiyun 	PVRDMA_WC_COMP_SWAP,
114*4882a593Smuzhiyun 	PVRDMA_WC_FETCH_ADD,
115*4882a593Smuzhiyun 	PVRDMA_WC_BIND_MW,
116*4882a593Smuzhiyun 	PVRDMA_WC_LSO,
117*4882a593Smuzhiyun 	PVRDMA_WC_LOCAL_INV,
118*4882a593Smuzhiyun 	PVRDMA_WC_FAST_REG_MR,
119*4882a593Smuzhiyun 	PVRDMA_WC_MASKED_COMP_SWAP,
120*4882a593Smuzhiyun 	PVRDMA_WC_MASKED_FETCH_ADD,
121*4882a593Smuzhiyun 	PVRDMA_WC_RECV = 1 << 7,
122*4882a593Smuzhiyun 	PVRDMA_WC_RECV_RDMA_WITH_IMM,
123*4882a593Smuzhiyun };
124*4882a593Smuzhiyun 
125*4882a593Smuzhiyun enum pvrdma_wc_flags {
126*4882a593Smuzhiyun 	PVRDMA_WC_GRH			= 1 << 0,
127*4882a593Smuzhiyun 	PVRDMA_WC_WITH_IMM		= 1 << 1,
128*4882a593Smuzhiyun 	PVRDMA_WC_WITH_INVALIDATE	= 1 << 2,
129*4882a593Smuzhiyun 	PVRDMA_WC_IP_CSUM_OK		= 1 << 3,
130*4882a593Smuzhiyun 	PVRDMA_WC_WITH_SMAC		= 1 << 4,
131*4882a593Smuzhiyun 	PVRDMA_WC_WITH_VLAN		= 1 << 5,
132*4882a593Smuzhiyun 	PVRDMA_WC_WITH_NETWORK_HDR_TYPE	= 1 << 6,
133*4882a593Smuzhiyun 	PVRDMA_WC_FLAGS_MAX		= PVRDMA_WC_WITH_NETWORK_HDR_TYPE,
134*4882a593Smuzhiyun };
135*4882a593Smuzhiyun 
136*4882a593Smuzhiyun enum pvrdma_network_type {
137*4882a593Smuzhiyun 	PVRDMA_NETWORK_IB,
138*4882a593Smuzhiyun 	PVRDMA_NETWORK_ROCE_V1 = PVRDMA_NETWORK_IB,
139*4882a593Smuzhiyun 	PVRDMA_NETWORK_IPV4,
140*4882a593Smuzhiyun 	PVRDMA_NETWORK_IPV6
141*4882a593Smuzhiyun };
142*4882a593Smuzhiyun 
143*4882a593Smuzhiyun struct pvrdma_alloc_ucontext_resp {
144*4882a593Smuzhiyun 	__u32 qp_tab_size;
145*4882a593Smuzhiyun 	__u32 reserved;
146*4882a593Smuzhiyun };
147*4882a593Smuzhiyun 
148*4882a593Smuzhiyun struct pvrdma_alloc_pd_resp {
149*4882a593Smuzhiyun 	__u32 pdn;
150*4882a593Smuzhiyun 	__u32 reserved;
151*4882a593Smuzhiyun };
152*4882a593Smuzhiyun 
153*4882a593Smuzhiyun struct pvrdma_create_cq {
154*4882a593Smuzhiyun 	__aligned_u64 buf_addr;
155*4882a593Smuzhiyun 	__u32 buf_size;
156*4882a593Smuzhiyun 	__u32 reserved;
157*4882a593Smuzhiyun };
158*4882a593Smuzhiyun 
159*4882a593Smuzhiyun struct pvrdma_create_cq_resp {
160*4882a593Smuzhiyun 	__u32 cqn;
161*4882a593Smuzhiyun 	__u32 reserved;
162*4882a593Smuzhiyun };
163*4882a593Smuzhiyun 
164*4882a593Smuzhiyun struct pvrdma_resize_cq {
165*4882a593Smuzhiyun 	__aligned_u64 buf_addr;
166*4882a593Smuzhiyun 	__u32 buf_size;
167*4882a593Smuzhiyun 	__u32 reserved;
168*4882a593Smuzhiyun };
169*4882a593Smuzhiyun 
170*4882a593Smuzhiyun struct pvrdma_create_srq {
171*4882a593Smuzhiyun 	__aligned_u64 buf_addr;
172*4882a593Smuzhiyun 	__u32 buf_size;
173*4882a593Smuzhiyun 	__u32 reserved;
174*4882a593Smuzhiyun };
175*4882a593Smuzhiyun 
176*4882a593Smuzhiyun struct pvrdma_create_srq_resp {
177*4882a593Smuzhiyun 	__u32 srqn;
178*4882a593Smuzhiyun 	__u32 reserved;
179*4882a593Smuzhiyun };
180*4882a593Smuzhiyun 
181*4882a593Smuzhiyun struct pvrdma_create_qp {
182*4882a593Smuzhiyun 	__aligned_u64 rbuf_addr;
183*4882a593Smuzhiyun 	__aligned_u64 sbuf_addr;
184*4882a593Smuzhiyun 	__u32 rbuf_size;
185*4882a593Smuzhiyun 	__u32 sbuf_size;
186*4882a593Smuzhiyun 	__aligned_u64 qp_addr;
187*4882a593Smuzhiyun };
188*4882a593Smuzhiyun 
189*4882a593Smuzhiyun struct pvrdma_create_qp_resp {
190*4882a593Smuzhiyun 	__u32 qpn;
191*4882a593Smuzhiyun 	__u32 qp_handle;
192*4882a593Smuzhiyun };
193*4882a593Smuzhiyun 
194*4882a593Smuzhiyun /* PVRDMA masked atomic compare and swap */
195*4882a593Smuzhiyun struct pvrdma_ex_cmp_swap {
196*4882a593Smuzhiyun 	__aligned_u64 swap_val;
197*4882a593Smuzhiyun 	__aligned_u64 compare_val;
198*4882a593Smuzhiyun 	__aligned_u64 swap_mask;
199*4882a593Smuzhiyun 	__aligned_u64 compare_mask;
200*4882a593Smuzhiyun };
201*4882a593Smuzhiyun 
202*4882a593Smuzhiyun /* PVRDMA masked atomic fetch and add */
203*4882a593Smuzhiyun struct pvrdma_ex_fetch_add {
204*4882a593Smuzhiyun 	__aligned_u64 add_val;
205*4882a593Smuzhiyun 	__aligned_u64 field_boundary;
206*4882a593Smuzhiyun };
207*4882a593Smuzhiyun 
208*4882a593Smuzhiyun /* PVRDMA address vector. */
209*4882a593Smuzhiyun struct pvrdma_av {
210*4882a593Smuzhiyun 	__u32 port_pd;
211*4882a593Smuzhiyun 	__u32 sl_tclass_flowlabel;
212*4882a593Smuzhiyun 	__u8 dgid[16];
213*4882a593Smuzhiyun 	__u8 src_path_bits;
214*4882a593Smuzhiyun 	__u8 gid_index;
215*4882a593Smuzhiyun 	__u8 stat_rate;
216*4882a593Smuzhiyun 	__u8 hop_limit;
217*4882a593Smuzhiyun 	__u8 dmac[6];
218*4882a593Smuzhiyun 	__u8 reserved[6];
219*4882a593Smuzhiyun };
220*4882a593Smuzhiyun 
221*4882a593Smuzhiyun /* PVRDMA scatter/gather entry */
222*4882a593Smuzhiyun struct pvrdma_sge {
223*4882a593Smuzhiyun 	__aligned_u64 addr;
224*4882a593Smuzhiyun 	__u32   length;
225*4882a593Smuzhiyun 	__u32   lkey;
226*4882a593Smuzhiyun };
227*4882a593Smuzhiyun 
228*4882a593Smuzhiyun /* PVRDMA receive queue work request */
229*4882a593Smuzhiyun struct pvrdma_rq_wqe_hdr {
230*4882a593Smuzhiyun 	__aligned_u64 wr_id;		/* wr id */
231*4882a593Smuzhiyun 	__u32 num_sge;		/* size of s/g array */
232*4882a593Smuzhiyun 	__u32 total_len;	/* reserved */
233*4882a593Smuzhiyun };
234*4882a593Smuzhiyun /* Use pvrdma_sge (ib_sge) for receive queue s/g array elements. */
235*4882a593Smuzhiyun 
236*4882a593Smuzhiyun /* PVRDMA send queue work request */
237*4882a593Smuzhiyun struct pvrdma_sq_wqe_hdr {
238*4882a593Smuzhiyun 	__aligned_u64 wr_id;		/* wr id */
239*4882a593Smuzhiyun 	__u32 num_sge;		/* size of s/g array */
240*4882a593Smuzhiyun 	__u32 total_len;	/* reserved */
241*4882a593Smuzhiyun 	__u32 opcode;		/* operation type */
242*4882a593Smuzhiyun 	__u32 send_flags;	/* wr flags */
243*4882a593Smuzhiyun 	union {
244*4882a593Smuzhiyun 		__be32 imm_data;
245*4882a593Smuzhiyun 		__u32 invalidate_rkey;
246*4882a593Smuzhiyun 	} ex;
247*4882a593Smuzhiyun 	__u32 reserved;
248*4882a593Smuzhiyun 	union {
249*4882a593Smuzhiyun 		struct {
250*4882a593Smuzhiyun 			__aligned_u64 remote_addr;
251*4882a593Smuzhiyun 			__u32 rkey;
252*4882a593Smuzhiyun 			__u8 reserved[4];
253*4882a593Smuzhiyun 		} rdma;
254*4882a593Smuzhiyun 		struct {
255*4882a593Smuzhiyun 			__aligned_u64 remote_addr;
256*4882a593Smuzhiyun 			__aligned_u64 compare_add;
257*4882a593Smuzhiyun 			__aligned_u64 swap;
258*4882a593Smuzhiyun 			__u32 rkey;
259*4882a593Smuzhiyun 			__u32 reserved;
260*4882a593Smuzhiyun 		} atomic;
261*4882a593Smuzhiyun 		struct {
262*4882a593Smuzhiyun 			__aligned_u64 remote_addr;
263*4882a593Smuzhiyun 			__u32 log_arg_sz;
264*4882a593Smuzhiyun 			__u32 rkey;
265*4882a593Smuzhiyun 			union {
266*4882a593Smuzhiyun 				struct pvrdma_ex_cmp_swap  cmp_swap;
267*4882a593Smuzhiyun 				struct pvrdma_ex_fetch_add fetch_add;
268*4882a593Smuzhiyun 			} wr_data;
269*4882a593Smuzhiyun 		} masked_atomics;
270*4882a593Smuzhiyun 		struct {
271*4882a593Smuzhiyun 			__aligned_u64 iova_start;
272*4882a593Smuzhiyun 			__aligned_u64 pl_pdir_dma;
273*4882a593Smuzhiyun 			__u32 page_shift;
274*4882a593Smuzhiyun 			__u32 page_list_len;
275*4882a593Smuzhiyun 			__u32 length;
276*4882a593Smuzhiyun 			__u32 access_flags;
277*4882a593Smuzhiyun 			__u32 rkey;
278*4882a593Smuzhiyun 			__u32 reserved;
279*4882a593Smuzhiyun 		} fast_reg;
280*4882a593Smuzhiyun 		struct {
281*4882a593Smuzhiyun 			__u32 remote_qpn;
282*4882a593Smuzhiyun 			__u32 remote_qkey;
283*4882a593Smuzhiyun 			struct pvrdma_av av;
284*4882a593Smuzhiyun 		} ud;
285*4882a593Smuzhiyun 	} wr;
286*4882a593Smuzhiyun };
287*4882a593Smuzhiyun /* Use pvrdma_sge (ib_sge) for send queue s/g array elements. */
288*4882a593Smuzhiyun 
289*4882a593Smuzhiyun /* Completion queue element. */
290*4882a593Smuzhiyun struct pvrdma_cqe {
291*4882a593Smuzhiyun 	__aligned_u64 wr_id;
292*4882a593Smuzhiyun 	__aligned_u64 qp;
293*4882a593Smuzhiyun 	__u32 opcode;
294*4882a593Smuzhiyun 	__u32 status;
295*4882a593Smuzhiyun 	__u32 byte_len;
296*4882a593Smuzhiyun 	__be32 imm_data;
297*4882a593Smuzhiyun 	__u32 src_qp;
298*4882a593Smuzhiyun 	__u32 wc_flags;
299*4882a593Smuzhiyun 	__u32 vendor_err;
300*4882a593Smuzhiyun 	__u16 pkey_index;
301*4882a593Smuzhiyun 	__u16 slid;
302*4882a593Smuzhiyun 	__u8 sl;
303*4882a593Smuzhiyun 	__u8 dlid_path_bits;
304*4882a593Smuzhiyun 	__u8 port_num;
305*4882a593Smuzhiyun 	__u8 smac[6];
306*4882a593Smuzhiyun 	__u8 network_hdr_type;
307*4882a593Smuzhiyun 	__u8 reserved2[6]; /* Pad to next power of 2 (64). */
308*4882a593Smuzhiyun };
309*4882a593Smuzhiyun 
310*4882a593Smuzhiyun #endif /* __VMW_PVRDMA_ABI_H__ */
311