1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * Copyright (c) 2006 - 2016 Intel Corporation. All rights reserved. 3*4882a593Smuzhiyun * Copyright (c) 2005 Topspin Communications. All rights reserved. 4*4882a593Smuzhiyun * Copyright (c) 2005 Cisco Systems. All rights reserved. 5*4882a593Smuzhiyun * Copyright (c) 2005 Open Grid Computing, Inc. All rights reserved. 6*4882a593Smuzhiyun * 7*4882a593Smuzhiyun * This software is available to you under a choice of one of two 8*4882a593Smuzhiyun * licenses. You may choose to be licensed under the terms of the GNU 9*4882a593Smuzhiyun * General Public License (GPL) Version 2, available from the file 10*4882a593Smuzhiyun * COPYING in the main directory of this source tree, or the 11*4882a593Smuzhiyun * OpenIB.org BSD license below: 12*4882a593Smuzhiyun * 13*4882a593Smuzhiyun * Redistribution and use in source and binary forms, with or 14*4882a593Smuzhiyun * without modification, are permitted provided that the following 15*4882a593Smuzhiyun * conditions are met: 16*4882a593Smuzhiyun * 17*4882a593Smuzhiyun * - Redistributions of source code must retain the above 18*4882a593Smuzhiyun * copyright notice, this list of conditions and the following 19*4882a593Smuzhiyun * disclaimer. 20*4882a593Smuzhiyun * 21*4882a593Smuzhiyun * - Redistributions in binary form must reproduce the above 22*4882a593Smuzhiyun * copyright notice, this list of conditions and the following 23*4882a593Smuzhiyun * disclaimer in the documentation and/or other materials 24*4882a593Smuzhiyun * provided with the distribution. 25*4882a593Smuzhiyun * 26*4882a593Smuzhiyun * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 27*4882a593Smuzhiyun * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 28*4882a593Smuzhiyun * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 29*4882a593Smuzhiyun * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 30*4882a593Smuzhiyun * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 31*4882a593Smuzhiyun * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 32*4882a593Smuzhiyun * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 33*4882a593Smuzhiyun * SOFTWARE. 34*4882a593Smuzhiyun * 35*4882a593Smuzhiyun */ 36*4882a593Smuzhiyun 37*4882a593Smuzhiyun #ifndef I40IW_ABI_H 38*4882a593Smuzhiyun #define I40IW_ABI_H 39*4882a593Smuzhiyun 40*4882a593Smuzhiyun #include <linux/types.h> 41*4882a593Smuzhiyun 42*4882a593Smuzhiyun #define I40IW_ABI_VER 5 43*4882a593Smuzhiyun 44*4882a593Smuzhiyun struct i40iw_alloc_ucontext_req { 45*4882a593Smuzhiyun __u32 reserved32; 46*4882a593Smuzhiyun __u8 userspace_ver; 47*4882a593Smuzhiyun __u8 reserved8[3]; 48*4882a593Smuzhiyun }; 49*4882a593Smuzhiyun 50*4882a593Smuzhiyun struct i40iw_alloc_ucontext_resp { 51*4882a593Smuzhiyun __u32 max_pds; /* maximum pds allowed for this user process */ 52*4882a593Smuzhiyun __u32 max_qps; /* maximum qps allowed for this user process */ 53*4882a593Smuzhiyun __u32 wq_size; /* size of the WQs (sq+rq) allocated to the mmaped area */ 54*4882a593Smuzhiyun __u8 kernel_ver; 55*4882a593Smuzhiyun __u8 reserved[3]; 56*4882a593Smuzhiyun }; 57*4882a593Smuzhiyun 58*4882a593Smuzhiyun struct i40iw_alloc_pd_resp { 59*4882a593Smuzhiyun __u32 pd_id; 60*4882a593Smuzhiyun __u8 reserved[4]; 61*4882a593Smuzhiyun }; 62*4882a593Smuzhiyun 63*4882a593Smuzhiyun struct i40iw_create_cq_req { 64*4882a593Smuzhiyun __aligned_u64 user_cq_buffer; 65*4882a593Smuzhiyun __aligned_u64 user_shadow_area; 66*4882a593Smuzhiyun }; 67*4882a593Smuzhiyun 68*4882a593Smuzhiyun struct i40iw_create_qp_req { 69*4882a593Smuzhiyun __aligned_u64 user_wqe_buffers; 70*4882a593Smuzhiyun __aligned_u64 user_compl_ctx; 71*4882a593Smuzhiyun 72*4882a593Smuzhiyun /* UDA QP PHB */ 73*4882a593Smuzhiyun __aligned_u64 user_sq_phb; /* place for VA of the sq phb buff */ 74*4882a593Smuzhiyun __aligned_u64 user_rq_phb; /* place for VA of the rq phb buff */ 75*4882a593Smuzhiyun }; 76*4882a593Smuzhiyun 77*4882a593Smuzhiyun enum i40iw_memreg_type { 78*4882a593Smuzhiyun IW_MEMREG_TYPE_MEM = 0x0000, 79*4882a593Smuzhiyun IW_MEMREG_TYPE_QP = 0x0001, 80*4882a593Smuzhiyun IW_MEMREG_TYPE_CQ = 0x0002, 81*4882a593Smuzhiyun }; 82*4882a593Smuzhiyun 83*4882a593Smuzhiyun struct i40iw_mem_reg_req { 84*4882a593Smuzhiyun __u16 reg_type; /* Memory, QP or CQ */ 85*4882a593Smuzhiyun __u16 cq_pages; 86*4882a593Smuzhiyun __u16 rq_pages; 87*4882a593Smuzhiyun __u16 sq_pages; 88*4882a593Smuzhiyun }; 89*4882a593Smuzhiyun 90*4882a593Smuzhiyun struct i40iw_create_cq_resp { 91*4882a593Smuzhiyun __u32 cq_id; 92*4882a593Smuzhiyun __u32 cq_size; 93*4882a593Smuzhiyun __u32 mmap_db_index; 94*4882a593Smuzhiyun __u32 reserved; 95*4882a593Smuzhiyun }; 96*4882a593Smuzhiyun 97*4882a593Smuzhiyun struct i40iw_create_qp_resp { 98*4882a593Smuzhiyun __u32 qp_id; 99*4882a593Smuzhiyun __u32 actual_sq_size; 100*4882a593Smuzhiyun __u32 actual_rq_size; 101*4882a593Smuzhiyun __u32 i40iw_drv_opt; 102*4882a593Smuzhiyun __u16 push_idx; 103*4882a593Smuzhiyun __u8 lsmm; 104*4882a593Smuzhiyun __u8 rsvd2; 105*4882a593Smuzhiyun }; 106*4882a593Smuzhiyun 107*4882a593Smuzhiyun #endif 108