1*4882a593Smuzhiyun /* SPDX-License-Identifier: ((GPL-2.0 WITH Linux-syscall-note) OR BSD-3-Clause) */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * This file is provided under a dual BSD/GPLv2 license. When using or 5*4882a593Smuzhiyun * redistributing this file, you may do so under either license. 6*4882a593Smuzhiyun * 7*4882a593Smuzhiyun * GPL LICENSE SUMMARY 8*4882a593Smuzhiyun * 9*4882a593Smuzhiyun * Copyright(c) 2015 - 2020 Intel Corporation. 10*4882a593Smuzhiyun * 11*4882a593Smuzhiyun * This program is free software; you can redistribute it and/or modify 12*4882a593Smuzhiyun * it under the terms of version 2 of the GNU General Public License as 13*4882a593Smuzhiyun * published by the Free Software Foundation. 14*4882a593Smuzhiyun * 15*4882a593Smuzhiyun * This program is distributed in the hope that it will be useful, but 16*4882a593Smuzhiyun * WITHOUT ANY WARRANTY; without even the implied warranty of 17*4882a593Smuzhiyun * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 18*4882a593Smuzhiyun * General Public License for more details. 19*4882a593Smuzhiyun * 20*4882a593Smuzhiyun * BSD LICENSE 21*4882a593Smuzhiyun * 22*4882a593Smuzhiyun * Copyright(c) 2015 Intel Corporation. 23*4882a593Smuzhiyun * 24*4882a593Smuzhiyun * Redistribution and use in source and binary forms, with or without 25*4882a593Smuzhiyun * modification, are permitted provided that the following conditions 26*4882a593Smuzhiyun * are met: 27*4882a593Smuzhiyun * 28*4882a593Smuzhiyun * - Redistributions of source code must retain the above copyright 29*4882a593Smuzhiyun * notice, this list of conditions and the following disclaimer. 30*4882a593Smuzhiyun * - Redistributions in binary form must reproduce the above copyright 31*4882a593Smuzhiyun * notice, this list of conditions and the following disclaimer in 32*4882a593Smuzhiyun * the documentation and/or other materials provided with the 33*4882a593Smuzhiyun * distribution. 34*4882a593Smuzhiyun * - Neither the name of Intel Corporation nor the names of its 35*4882a593Smuzhiyun * contributors may be used to endorse or promote products derived 36*4882a593Smuzhiyun * from this software without specific prior written permission. 37*4882a593Smuzhiyun * 38*4882a593Smuzhiyun * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 39*4882a593Smuzhiyun * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 40*4882a593Smuzhiyun * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 41*4882a593Smuzhiyun * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 42*4882a593Smuzhiyun * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 43*4882a593Smuzhiyun * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 44*4882a593Smuzhiyun * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 45*4882a593Smuzhiyun * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 46*4882a593Smuzhiyun * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 47*4882a593Smuzhiyun * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 48*4882a593Smuzhiyun * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 49*4882a593Smuzhiyun * 50*4882a593Smuzhiyun */ 51*4882a593Smuzhiyun 52*4882a593Smuzhiyun /* 53*4882a593Smuzhiyun * This file contains defines, structures, etc. that are used 54*4882a593Smuzhiyun * to communicate between kernel and user code. 55*4882a593Smuzhiyun */ 56*4882a593Smuzhiyun 57*4882a593Smuzhiyun #ifndef _LINUX__HFI1_USER_H 58*4882a593Smuzhiyun #define _LINUX__HFI1_USER_H 59*4882a593Smuzhiyun 60*4882a593Smuzhiyun #include <linux/types.h> 61*4882a593Smuzhiyun #include <rdma/rdma_user_ioctl.h> 62*4882a593Smuzhiyun 63*4882a593Smuzhiyun /* 64*4882a593Smuzhiyun * This version number is given to the driver by the user code during 65*4882a593Smuzhiyun * initialization in the spu_userversion field of hfi1_user_info, so 66*4882a593Smuzhiyun * the driver can check for compatibility with user code. 67*4882a593Smuzhiyun * 68*4882a593Smuzhiyun * The major version changes when data structures change in an incompatible 69*4882a593Smuzhiyun * way. The driver must be the same for initialization to succeed. 70*4882a593Smuzhiyun */ 71*4882a593Smuzhiyun #define HFI1_USER_SWMAJOR 6 72*4882a593Smuzhiyun 73*4882a593Smuzhiyun /* 74*4882a593Smuzhiyun * Minor version differences are always compatible 75*4882a593Smuzhiyun * a within a major version, however if user software is larger 76*4882a593Smuzhiyun * than driver software, some new features and/or structure fields 77*4882a593Smuzhiyun * may not be implemented; the user code must deal with this if it 78*4882a593Smuzhiyun * cares, or it must abort after initialization reports the difference. 79*4882a593Smuzhiyun */ 80*4882a593Smuzhiyun #define HFI1_USER_SWMINOR 3 81*4882a593Smuzhiyun 82*4882a593Smuzhiyun /* 83*4882a593Smuzhiyun * We will encode the major/minor inside a single 32bit version number. 84*4882a593Smuzhiyun */ 85*4882a593Smuzhiyun #define HFI1_SWMAJOR_SHIFT 16 86*4882a593Smuzhiyun 87*4882a593Smuzhiyun /* 88*4882a593Smuzhiyun * Set of HW and driver capability/feature bits. 89*4882a593Smuzhiyun * These bit values are used to configure enabled/disabled HW and 90*4882a593Smuzhiyun * driver features. The same set of bits are communicated to user 91*4882a593Smuzhiyun * space. 92*4882a593Smuzhiyun */ 93*4882a593Smuzhiyun #define HFI1_CAP_DMA_RTAIL (1UL << 0) /* Use DMA'ed RTail value */ 94*4882a593Smuzhiyun #define HFI1_CAP_SDMA (1UL << 1) /* Enable SDMA support */ 95*4882a593Smuzhiyun #define HFI1_CAP_SDMA_AHG (1UL << 2) /* Enable SDMA AHG support */ 96*4882a593Smuzhiyun #define HFI1_CAP_EXTENDED_PSN (1UL << 3) /* Enable Extended PSN support */ 97*4882a593Smuzhiyun #define HFI1_CAP_HDRSUPP (1UL << 4) /* Enable Header Suppression */ 98*4882a593Smuzhiyun #define HFI1_CAP_TID_RDMA (1UL << 5) /* Enable TID RDMA operations */ 99*4882a593Smuzhiyun #define HFI1_CAP_USE_SDMA_HEAD (1UL << 6) /* DMA Hdr Q tail vs. use CSR */ 100*4882a593Smuzhiyun #define HFI1_CAP_MULTI_PKT_EGR (1UL << 7) /* Enable multi-packet Egr buffs*/ 101*4882a593Smuzhiyun #define HFI1_CAP_NODROP_RHQ_FULL (1UL << 8) /* Don't drop on Hdr Q full */ 102*4882a593Smuzhiyun #define HFI1_CAP_NODROP_EGR_FULL (1UL << 9) /* Don't drop on EGR buffs full */ 103*4882a593Smuzhiyun #define HFI1_CAP_TID_UNMAP (1UL << 10) /* Disable Expected TID caching */ 104*4882a593Smuzhiyun #define HFI1_CAP_PRINT_UNIMPL (1UL << 11) /* Show for unimplemented feats */ 105*4882a593Smuzhiyun #define HFI1_CAP_ALLOW_PERM_JKEY (1UL << 12) /* Allow use of permissive JKEY */ 106*4882a593Smuzhiyun #define HFI1_CAP_NO_INTEGRITY (1UL << 13) /* Enable ctxt integrity checks */ 107*4882a593Smuzhiyun #define HFI1_CAP_PKEY_CHECK (1UL << 14) /* Enable ctxt PKey checking */ 108*4882a593Smuzhiyun #define HFI1_CAP_STATIC_RATE_CTRL (1UL << 15) /* Allow PBC.StaticRateControl */ 109*4882a593Smuzhiyun #define HFI1_CAP_OPFN (1UL << 16) /* Enable the OPFN protocol */ 110*4882a593Smuzhiyun #define HFI1_CAP_SDMA_HEAD_CHECK (1UL << 17) /* SDMA head checking */ 111*4882a593Smuzhiyun #define HFI1_CAP_EARLY_CREDIT_RETURN (1UL << 18) /* early credit return */ 112*4882a593Smuzhiyun #define HFI1_CAP_AIP (1UL << 19) /* Enable accelerated IP */ 113*4882a593Smuzhiyun 114*4882a593Smuzhiyun #define HFI1_RCVHDR_ENTSIZE_2 (1UL << 0) 115*4882a593Smuzhiyun #define HFI1_RCVHDR_ENTSIZE_16 (1UL << 1) 116*4882a593Smuzhiyun #define HFI1_RCVDHR_ENTSIZE_32 (1UL << 2) 117*4882a593Smuzhiyun 118*4882a593Smuzhiyun #define _HFI1_EVENT_FROZEN_BIT 0 119*4882a593Smuzhiyun #define _HFI1_EVENT_LINKDOWN_BIT 1 120*4882a593Smuzhiyun #define _HFI1_EVENT_LID_CHANGE_BIT 2 121*4882a593Smuzhiyun #define _HFI1_EVENT_LMC_CHANGE_BIT 3 122*4882a593Smuzhiyun #define _HFI1_EVENT_SL2VL_CHANGE_BIT 4 123*4882a593Smuzhiyun #define _HFI1_EVENT_TID_MMU_NOTIFY_BIT 5 124*4882a593Smuzhiyun #define _HFI1_MAX_EVENT_BIT _HFI1_EVENT_TID_MMU_NOTIFY_BIT 125*4882a593Smuzhiyun 126*4882a593Smuzhiyun #define HFI1_EVENT_FROZEN (1UL << _HFI1_EVENT_FROZEN_BIT) 127*4882a593Smuzhiyun #define HFI1_EVENT_LINKDOWN (1UL << _HFI1_EVENT_LINKDOWN_BIT) 128*4882a593Smuzhiyun #define HFI1_EVENT_LID_CHANGE (1UL << _HFI1_EVENT_LID_CHANGE_BIT) 129*4882a593Smuzhiyun #define HFI1_EVENT_LMC_CHANGE (1UL << _HFI1_EVENT_LMC_CHANGE_BIT) 130*4882a593Smuzhiyun #define HFI1_EVENT_SL2VL_CHANGE (1UL << _HFI1_EVENT_SL2VL_CHANGE_BIT) 131*4882a593Smuzhiyun #define HFI1_EVENT_TID_MMU_NOTIFY (1UL << _HFI1_EVENT_TID_MMU_NOTIFY_BIT) 132*4882a593Smuzhiyun 133*4882a593Smuzhiyun /* 134*4882a593Smuzhiyun * These are the status bits readable (in ASCII form, 64bit value) 135*4882a593Smuzhiyun * from the "status" sysfs file. For binary compatibility, values 136*4882a593Smuzhiyun * must remain as is; removed states can be reused for different 137*4882a593Smuzhiyun * purposes. 138*4882a593Smuzhiyun */ 139*4882a593Smuzhiyun #define HFI1_STATUS_INITTED 0x1 /* basic initialization done */ 140*4882a593Smuzhiyun /* Chip has been found and initialized */ 141*4882a593Smuzhiyun #define HFI1_STATUS_CHIP_PRESENT 0x20 142*4882a593Smuzhiyun /* IB link is at ACTIVE, usable for data traffic */ 143*4882a593Smuzhiyun #define HFI1_STATUS_IB_READY 0x40 144*4882a593Smuzhiyun /* link is configured, LID, MTU, etc. have been set */ 145*4882a593Smuzhiyun #define HFI1_STATUS_IB_CONF 0x80 146*4882a593Smuzhiyun /* A Fatal hardware error has occurred. */ 147*4882a593Smuzhiyun #define HFI1_STATUS_HWERROR 0x200 148*4882a593Smuzhiyun 149*4882a593Smuzhiyun /* 150*4882a593Smuzhiyun * Number of supported shared contexts. 151*4882a593Smuzhiyun * This is the maximum number of software contexts that can share 152*4882a593Smuzhiyun * a hardware send/receive context. 153*4882a593Smuzhiyun */ 154*4882a593Smuzhiyun #define HFI1_MAX_SHARED_CTXTS 8 155*4882a593Smuzhiyun 156*4882a593Smuzhiyun /* 157*4882a593Smuzhiyun * Poll types 158*4882a593Smuzhiyun */ 159*4882a593Smuzhiyun #define HFI1_POLL_TYPE_ANYRCV 0x0 160*4882a593Smuzhiyun #define HFI1_POLL_TYPE_URGENT 0x1 161*4882a593Smuzhiyun 162*4882a593Smuzhiyun enum hfi1_sdma_comp_state { 163*4882a593Smuzhiyun FREE = 0, 164*4882a593Smuzhiyun QUEUED, 165*4882a593Smuzhiyun COMPLETE, 166*4882a593Smuzhiyun ERROR 167*4882a593Smuzhiyun }; 168*4882a593Smuzhiyun 169*4882a593Smuzhiyun /* 170*4882a593Smuzhiyun * SDMA completion ring entry 171*4882a593Smuzhiyun */ 172*4882a593Smuzhiyun struct hfi1_sdma_comp_entry { 173*4882a593Smuzhiyun __u32 status; 174*4882a593Smuzhiyun __u32 errcode; 175*4882a593Smuzhiyun }; 176*4882a593Smuzhiyun 177*4882a593Smuzhiyun /* 178*4882a593Smuzhiyun * Device status and notifications from driver to user-space. 179*4882a593Smuzhiyun */ 180*4882a593Smuzhiyun struct hfi1_status { 181*4882a593Smuzhiyun __aligned_u64 dev; /* device/hw status bits */ 182*4882a593Smuzhiyun __aligned_u64 port; /* port state and status bits */ 183*4882a593Smuzhiyun char freezemsg[0]; 184*4882a593Smuzhiyun }; 185*4882a593Smuzhiyun 186*4882a593Smuzhiyun enum sdma_req_opcode { 187*4882a593Smuzhiyun EXPECTED = 0, 188*4882a593Smuzhiyun EAGER 189*4882a593Smuzhiyun }; 190*4882a593Smuzhiyun 191*4882a593Smuzhiyun #define HFI1_SDMA_REQ_VERSION_MASK 0xF 192*4882a593Smuzhiyun #define HFI1_SDMA_REQ_VERSION_SHIFT 0x0 193*4882a593Smuzhiyun #define HFI1_SDMA_REQ_OPCODE_MASK 0xF 194*4882a593Smuzhiyun #define HFI1_SDMA_REQ_OPCODE_SHIFT 0x4 195*4882a593Smuzhiyun #define HFI1_SDMA_REQ_IOVCNT_MASK 0xFF 196*4882a593Smuzhiyun #define HFI1_SDMA_REQ_IOVCNT_SHIFT 0x8 197*4882a593Smuzhiyun 198*4882a593Smuzhiyun struct sdma_req_info { 199*4882a593Smuzhiyun /* 200*4882a593Smuzhiyun * bits 0-3 - version (currently unused) 201*4882a593Smuzhiyun * bits 4-7 - opcode (enum sdma_req_opcode) 202*4882a593Smuzhiyun * bits 8-15 - io vector count 203*4882a593Smuzhiyun */ 204*4882a593Smuzhiyun __u16 ctrl; 205*4882a593Smuzhiyun /* 206*4882a593Smuzhiyun * Number of fragments contained in this request. 207*4882a593Smuzhiyun * User-space has already computed how many 208*4882a593Smuzhiyun * fragment-sized packet the user buffer will be 209*4882a593Smuzhiyun * split into. 210*4882a593Smuzhiyun */ 211*4882a593Smuzhiyun __u16 npkts; 212*4882a593Smuzhiyun /* 213*4882a593Smuzhiyun * Size of each fragment the user buffer will be 214*4882a593Smuzhiyun * split into. 215*4882a593Smuzhiyun */ 216*4882a593Smuzhiyun __u16 fragsize; 217*4882a593Smuzhiyun /* 218*4882a593Smuzhiyun * Index of the slot in the SDMA completion ring 219*4882a593Smuzhiyun * this request should be using. User-space is 220*4882a593Smuzhiyun * in charge of managing its own ring. 221*4882a593Smuzhiyun */ 222*4882a593Smuzhiyun __u16 comp_idx; 223*4882a593Smuzhiyun } __attribute__((__packed__)); 224*4882a593Smuzhiyun 225*4882a593Smuzhiyun /* 226*4882a593Smuzhiyun * SW KDETH header. 227*4882a593Smuzhiyun * swdata is SW defined portion. 228*4882a593Smuzhiyun */ 229*4882a593Smuzhiyun struct hfi1_kdeth_header { 230*4882a593Smuzhiyun __le32 ver_tid_offset; 231*4882a593Smuzhiyun __le16 jkey; 232*4882a593Smuzhiyun __le16 hcrc; 233*4882a593Smuzhiyun __le32 swdata[7]; 234*4882a593Smuzhiyun } __attribute__((__packed__)); 235*4882a593Smuzhiyun 236*4882a593Smuzhiyun /* 237*4882a593Smuzhiyun * Structure describing the headers that User space uses. The 238*4882a593Smuzhiyun * structure above is a subset of this one. 239*4882a593Smuzhiyun */ 240*4882a593Smuzhiyun struct hfi1_pkt_header { 241*4882a593Smuzhiyun __le16 pbc[4]; 242*4882a593Smuzhiyun __be16 lrh[4]; 243*4882a593Smuzhiyun __be32 bth[3]; 244*4882a593Smuzhiyun struct hfi1_kdeth_header kdeth; 245*4882a593Smuzhiyun } __attribute__((__packed__)); 246*4882a593Smuzhiyun 247*4882a593Smuzhiyun 248*4882a593Smuzhiyun /* 249*4882a593Smuzhiyun * The list of usermode accessible registers. 250*4882a593Smuzhiyun */ 251*4882a593Smuzhiyun enum hfi1_ureg { 252*4882a593Smuzhiyun /* (RO) DMA RcvHdr to be used next. */ 253*4882a593Smuzhiyun ur_rcvhdrtail = 0, 254*4882a593Smuzhiyun /* (RW) RcvHdr entry to be processed next by host. */ 255*4882a593Smuzhiyun ur_rcvhdrhead = 1, 256*4882a593Smuzhiyun /* (RO) Index of next Eager index to use. */ 257*4882a593Smuzhiyun ur_rcvegrindextail = 2, 258*4882a593Smuzhiyun /* (RW) Eager TID to be processed next */ 259*4882a593Smuzhiyun ur_rcvegrindexhead = 3, 260*4882a593Smuzhiyun /* (RO) Receive Eager Offset Tail */ 261*4882a593Smuzhiyun ur_rcvegroffsettail = 4, 262*4882a593Smuzhiyun /* For internal use only; max register number. */ 263*4882a593Smuzhiyun ur_maxreg, 264*4882a593Smuzhiyun /* (RW) Receive TID flow table */ 265*4882a593Smuzhiyun ur_rcvtidflowtable = 256 266*4882a593Smuzhiyun }; 267*4882a593Smuzhiyun 268*4882a593Smuzhiyun #endif /* _LINIUX__HFI1_USER_H */ 269