1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Rockchip HDCP Host Library driver 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Copyright (C) 2022 Rockchip Electronics Co., Ltd 6*4882a593Smuzhiyun */ 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun #ifndef _DW_HDCP_HOST_LIB_DRIVER_LINUX_IF_H_ 9*4882a593Smuzhiyun #define _DW_HDCP_HOST_LIB_DRIVER_LINUX_IF_H_ 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun #include <linux/ioctl.h> 12*4882a593Smuzhiyun #include <linux/types.h> 13*4882a593Smuzhiyun 14*4882a593Smuzhiyun #define HL_DRIVER_ALLOCATE_DYNAMIC_MEM 0xffffffff 15*4882a593Smuzhiyun /* hl_drv_ioctl numbers */ 16*4882a593Smuzhiyun enum { 17*4882a593Smuzhiyun HL_DRV_NR_MIN = 0x10, 18*4882a593Smuzhiyun HL_DRV_NR_INIT, 19*4882a593Smuzhiyun HL_DRV_NR_MEMINFO, 20*4882a593Smuzhiyun HL_DRV_NR_LOAD_CODE, 21*4882a593Smuzhiyun HL_DRV_NR_READ_DATA, 22*4882a593Smuzhiyun HL_DRV_NR_WRITE_DATA, 23*4882a593Smuzhiyun HL_DRV_NR_MEMSET_DATA, 24*4882a593Smuzhiyun HL_DRV_NR_READ_HPI, 25*4882a593Smuzhiyun HL_DRV_NR_WRITE_HPI, 26*4882a593Smuzhiyun 27*4882a593Smuzhiyun RK_DRV_NR_GET_STATUS, 28*4882a593Smuzhiyun RK_DRV_NR_RESET, 29*4882a593Smuzhiyun 30*4882a593Smuzhiyun HL_DRV_NR_MAX 31*4882a593Smuzhiyun }; 32*4882a593Smuzhiyun 33*4882a593Smuzhiyun /* 34*4882a593Smuzhiyun * HL_DRV_IOC_INIT: associate file descriptor with the indicated memory. This 35*4882a593Smuzhiyun * must be called before any other hl_drv_ioctl on the file descriptor. 36*4882a593Smuzhiyun * 37*4882a593Smuzhiyun * - hpi_base = base address of HPI registers. 38*4882a593Smuzhiyun * - code_base = base address of firmware memory (0 to allocate internally) 39*4882a593Smuzhiyun * - data_base = base address of data memory (0 to allocate internally) 40*4882a593Smuzhiyun * - code_len, data_len = length of firmware and data memory, respectively. 41*4882a593Smuzhiyun */ 42*4882a593Smuzhiyun #define HL_DRV_IOC_INIT _IOW('H', HL_DRV_NR_INIT, struct hl_drv_ioc_meminfo) 43*4882a593Smuzhiyun 44*4882a593Smuzhiyun /* 45*4882a593Smuzhiyun * HL_DRV_IOC_MEMINFO: retrieve memory information from file descriptor. 46*4882a593Smuzhiyun * 47*4882a593Smuzhiyun * Fills out the meminfo struct, returning the values passed to HL_DRV_IOC_INIT 48*4882a593Smuzhiyun * except that the actual base addresses of internal allocations (if any) are 49*4882a593Smuzhiyun * reported. 50*4882a593Smuzhiyun */ 51*4882a593Smuzhiyun #define HL_DRV_IOC_MEMINFO _IOR('H', HL_DRV_NR_MEMINFO, struct hl_drv_ioc_meminfo) 52*4882a593Smuzhiyun 53*4882a593Smuzhiyun struct hl_drv_ioc_meminfo { 54*4882a593Smuzhiyun __u32 hpi_base; 55*4882a593Smuzhiyun __u32 code_base; 56*4882a593Smuzhiyun __u32 code_size; 57*4882a593Smuzhiyun __u32 data_base; 58*4882a593Smuzhiyun __u32 data_size; 59*4882a593Smuzhiyun }; 60*4882a593Smuzhiyun 61*4882a593Smuzhiyun /* 62*4882a593Smuzhiyun * HL_DRV_IOC_LOAD_CODE: write the provided buffer to the firmware memory. 63*4882a593Smuzhiyun * 64*4882a593Smuzhiyun * - len = number of bytes in data buffer 65*4882a593Smuzhiyun * - data = data to write to firmware memory. 66*4882a593Smuzhiyun * 67*4882a593Smuzhiyun * This can only be done once (successfully). Subsequent attempts will 68*4882a593Smuzhiyun * return -EBUSY. 69*4882a593Smuzhiyun */ 70*4882a593Smuzhiyun #define HL_DRV_IOC_LOAD_CODE _IOW('H', HL_DRV_NR_LOAD_CODE, struct hl_drv_ioc_code) 71*4882a593Smuzhiyun 72*4882a593Smuzhiyun struct hl_drv_ioc_code { 73*4882a593Smuzhiyun __u32 len; 74*4882a593Smuzhiyun __u8 data[]; 75*4882a593Smuzhiyun }; 76*4882a593Smuzhiyun 77*4882a593Smuzhiyun /* 78*4882a593Smuzhiyun * HL_DRV_IOC_READ_DATA: copy from data memory. 79*4882a593Smuzhiyun * HL_DRV_IOC_WRITE_DATA: copy to data memory. 80*4882a593Smuzhiyun * 81*4882a593Smuzhiyun * - offset = start copying at this byte offset into the data memory. 82*4882a593Smuzhiyun * - len = number of bytes to copy. 83*4882a593Smuzhiyun * - data = for write, buffer containing data to copy. 84*4882a593Smuzhiyun * for read, buffer to which read data will be written. 85*4882a593Smuzhiyun * 86*4882a593Smuzhiyun */ 87*4882a593Smuzhiyun #define HL_DRV_IOC_READ_DATA _IOWR('H', HL_DRV_NR_READ_DATA, struct hl_drv_ioc_data) 88*4882a593Smuzhiyun #define HL_DRV_IOC_WRITE_DATA _IOW('H', HL_DRV_NR_WRITE_DATA, struct hl_drv_ioc_data) 89*4882a593Smuzhiyun 90*4882a593Smuzhiyun /* 91*4882a593Smuzhiyun * HL_DRV_IOC_MEMSET_DATA: initialize data memory. 92*4882a593Smuzhiyun * 93*4882a593Smuzhiyun * - offset = start initializatoin at this byte offset into the data memory. 94*4882a593Smuzhiyun * - len = number of bytes to set. 95*4882a593Smuzhiyun * - data[0] = byte value to write to all indicated memory locations. 96*4882a593Smuzhiyun */ 97*4882a593Smuzhiyun #define HL_DRV_IOC_MEMSET_DATA _IOW('H', HL_DRV_NR_MEMSET_DATA, struct hl_drv_ioc_data) 98*4882a593Smuzhiyun 99*4882a593Smuzhiyun struct hl_drv_ioc_data { 100*4882a593Smuzhiyun __u32 offset; 101*4882a593Smuzhiyun __u32 len; 102*4882a593Smuzhiyun __u8 data[]; 103*4882a593Smuzhiyun }; 104*4882a593Smuzhiyun 105*4882a593Smuzhiyun /* 106*4882a593Smuzhiyun * HL_DRV_IOC_READ_HPI: read HPI register. 107*4882a593Smuzhiyun * HL_DRV_IOC_WRITE_HPI: write HPI register. 108*4882a593Smuzhiyun * 109*4882a593Smuzhiyun * - offset = byte offset of HPI register to access. 110*4882a593Smuzhiyun * - value = for write, value to write. 111*4882a593Smuzhiyun * for read, location to which result is stored. 112*4882a593Smuzhiyun */ 113*4882a593Smuzhiyun #define HL_DRV_IOC_READ_HPI _IOWR('H', HL_DRV_NR_READ_HPI, struct hl_drv_ioc_hpi_reg) 114*4882a593Smuzhiyun #define HL_DRV_IOC_WRITE_HPI _IOW('H', HL_DRV_NR_WRITE_HPI, struct hl_drv_ioc_hpi_reg) 115*4882a593Smuzhiyun 116*4882a593Smuzhiyun struct hl_drv_ioc_hpi_reg { 117*4882a593Smuzhiyun __u32 offset; 118*4882a593Smuzhiyun __u32 value; 119*4882a593Smuzhiyun }; 120*4882a593Smuzhiyun 121*4882a593Smuzhiyun #define RK_DRV_IOC_GET_STATUS _IOR('H', RK_DRV_NR_GET_STATUS, struct hl_drv_ioc_status) 122*4882a593Smuzhiyun 123*4882a593Smuzhiyun struct hl_drv_ioc_status { 124*4882a593Smuzhiyun __u32 connected_status; 125*4882a593Smuzhiyun __u32 booted_status; 126*4882a593Smuzhiyun }; 127*4882a593Smuzhiyun 128*4882a593Smuzhiyun #define RK_DRV_IOC_RESET _IOR('H', RK_DRV_NR_RESET, __u32) 129*4882a593Smuzhiyun 130*4882a593Smuzhiyun #endif /* _DW_HDCP_HOST_LIB_DRIVER_LINUX_IF_H_ */ 131