1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * Virtio platform device driver 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * Copyright 2011, ARM Ltd. 5*4882a593Smuzhiyun * 6*4882a593Smuzhiyun * Based on Virtio PCI driver by Anthony Liguori, copyright IBM Corp. 2007 7*4882a593Smuzhiyun * 8*4882a593Smuzhiyun * This header is BSD licensed so anyone can use the definitions to implement 9*4882a593Smuzhiyun * compatible drivers/servers. 10*4882a593Smuzhiyun * 11*4882a593Smuzhiyun * Redistribution and use in source and binary forms, with or without 12*4882a593Smuzhiyun * modification, are permitted provided that the following conditions 13*4882a593Smuzhiyun * are met: 14*4882a593Smuzhiyun * 1. Redistributions of source code must retain the above copyright 15*4882a593Smuzhiyun * notice, this list of conditions and the following disclaimer. 16*4882a593Smuzhiyun * 2. Redistributions in binary form must reproduce the above copyright 17*4882a593Smuzhiyun * notice, this list of conditions and the following disclaimer in the 18*4882a593Smuzhiyun * documentation and/or other materials provided with the distribution. 19*4882a593Smuzhiyun * 3. Neither the name of IBM nor the names of its contributors 20*4882a593Smuzhiyun * may be used to endorse or promote products derived from this software 21*4882a593Smuzhiyun * without specific prior written permission. 22*4882a593Smuzhiyun * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ``AS IS'' AND 23*4882a593Smuzhiyun * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 24*4882a593Smuzhiyun * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 25*4882a593Smuzhiyun * ARE DISCLAIMED. IN NO EVENT SHALL IBM OR CONTRIBUTORS BE LIABLE 26*4882a593Smuzhiyun * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 27*4882a593Smuzhiyun * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 28*4882a593Smuzhiyun * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 29*4882a593Smuzhiyun * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 30*4882a593Smuzhiyun * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 31*4882a593Smuzhiyun * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 32*4882a593Smuzhiyun * SUCH DAMAGE. 33*4882a593Smuzhiyun */ 34*4882a593Smuzhiyun 35*4882a593Smuzhiyun #ifndef _LINUX_VIRTIO_MMIO_H 36*4882a593Smuzhiyun #define _LINUX_VIRTIO_MMIO_H 37*4882a593Smuzhiyun 38*4882a593Smuzhiyun /* 39*4882a593Smuzhiyun * Control registers 40*4882a593Smuzhiyun */ 41*4882a593Smuzhiyun 42*4882a593Smuzhiyun /* Magic value ("virt" string) - Read Only */ 43*4882a593Smuzhiyun #define VIRTIO_MMIO_MAGIC_VALUE 0x000 44*4882a593Smuzhiyun 45*4882a593Smuzhiyun /* Virtio device version - Read Only */ 46*4882a593Smuzhiyun #define VIRTIO_MMIO_VERSION 0x004 47*4882a593Smuzhiyun 48*4882a593Smuzhiyun /* Virtio device ID - Read Only */ 49*4882a593Smuzhiyun #define VIRTIO_MMIO_DEVICE_ID 0x008 50*4882a593Smuzhiyun 51*4882a593Smuzhiyun /* Virtio vendor ID - Read Only */ 52*4882a593Smuzhiyun #define VIRTIO_MMIO_VENDOR_ID 0x00c 53*4882a593Smuzhiyun 54*4882a593Smuzhiyun /* Bitmask of the features supported by the device (host) 55*4882a593Smuzhiyun * (32 bits per set) - Read Only */ 56*4882a593Smuzhiyun #define VIRTIO_MMIO_DEVICE_FEATURES 0x010 57*4882a593Smuzhiyun 58*4882a593Smuzhiyun /* Device (host) features set selector - Write Only */ 59*4882a593Smuzhiyun #define VIRTIO_MMIO_DEVICE_FEATURES_SEL 0x014 60*4882a593Smuzhiyun 61*4882a593Smuzhiyun /* Bitmask of features activated by the driver (guest) 62*4882a593Smuzhiyun * (32 bits per set) - Write Only */ 63*4882a593Smuzhiyun #define VIRTIO_MMIO_DRIVER_FEATURES 0x020 64*4882a593Smuzhiyun 65*4882a593Smuzhiyun /* Activated features set selector - Write Only */ 66*4882a593Smuzhiyun #define VIRTIO_MMIO_DRIVER_FEATURES_SEL 0x024 67*4882a593Smuzhiyun 68*4882a593Smuzhiyun 69*4882a593Smuzhiyun #ifndef VIRTIO_MMIO_NO_LEGACY /* LEGACY DEVICES ONLY! */ 70*4882a593Smuzhiyun 71*4882a593Smuzhiyun /* Guest's memory page size in bytes - Write Only */ 72*4882a593Smuzhiyun #define VIRTIO_MMIO_GUEST_PAGE_SIZE 0x028 73*4882a593Smuzhiyun 74*4882a593Smuzhiyun #endif 75*4882a593Smuzhiyun 76*4882a593Smuzhiyun 77*4882a593Smuzhiyun /* Queue selector - Write Only */ 78*4882a593Smuzhiyun #define VIRTIO_MMIO_QUEUE_SEL 0x030 79*4882a593Smuzhiyun 80*4882a593Smuzhiyun /* Maximum size of the currently selected queue - Read Only */ 81*4882a593Smuzhiyun #define VIRTIO_MMIO_QUEUE_NUM_MAX 0x034 82*4882a593Smuzhiyun 83*4882a593Smuzhiyun /* Queue size for the currently selected queue - Write Only */ 84*4882a593Smuzhiyun #define VIRTIO_MMIO_QUEUE_NUM 0x038 85*4882a593Smuzhiyun 86*4882a593Smuzhiyun 87*4882a593Smuzhiyun #ifndef VIRTIO_MMIO_NO_LEGACY /* LEGACY DEVICES ONLY! */ 88*4882a593Smuzhiyun 89*4882a593Smuzhiyun /* Used Ring alignment for the currently selected queue - Write Only */ 90*4882a593Smuzhiyun #define VIRTIO_MMIO_QUEUE_ALIGN 0x03c 91*4882a593Smuzhiyun 92*4882a593Smuzhiyun /* Guest's PFN for the currently selected queue - Read Write */ 93*4882a593Smuzhiyun #define VIRTIO_MMIO_QUEUE_PFN 0x040 94*4882a593Smuzhiyun 95*4882a593Smuzhiyun #endif 96*4882a593Smuzhiyun 97*4882a593Smuzhiyun 98*4882a593Smuzhiyun /* Ready bit for the currently selected queue - Read Write */ 99*4882a593Smuzhiyun #define VIRTIO_MMIO_QUEUE_READY 0x044 100*4882a593Smuzhiyun 101*4882a593Smuzhiyun /* Queue notifier - Write Only */ 102*4882a593Smuzhiyun #define VIRTIO_MMIO_QUEUE_NOTIFY 0x050 103*4882a593Smuzhiyun 104*4882a593Smuzhiyun /* Interrupt status - Read Only */ 105*4882a593Smuzhiyun #define VIRTIO_MMIO_INTERRUPT_STATUS 0x060 106*4882a593Smuzhiyun 107*4882a593Smuzhiyun /* Interrupt acknowledge - Write Only */ 108*4882a593Smuzhiyun #define VIRTIO_MMIO_INTERRUPT_ACK 0x064 109*4882a593Smuzhiyun 110*4882a593Smuzhiyun /* Device status register - Read Write */ 111*4882a593Smuzhiyun #define VIRTIO_MMIO_STATUS 0x070 112*4882a593Smuzhiyun 113*4882a593Smuzhiyun /* Selected queue's Descriptor Table address, 64 bits in two halves */ 114*4882a593Smuzhiyun #define VIRTIO_MMIO_QUEUE_DESC_LOW 0x080 115*4882a593Smuzhiyun #define VIRTIO_MMIO_QUEUE_DESC_HIGH 0x084 116*4882a593Smuzhiyun 117*4882a593Smuzhiyun /* Selected queue's Available Ring address, 64 bits in two halves */ 118*4882a593Smuzhiyun #define VIRTIO_MMIO_QUEUE_AVAIL_LOW 0x090 119*4882a593Smuzhiyun #define VIRTIO_MMIO_QUEUE_AVAIL_HIGH 0x094 120*4882a593Smuzhiyun 121*4882a593Smuzhiyun /* Selected queue's Used Ring address, 64 bits in two halves */ 122*4882a593Smuzhiyun #define VIRTIO_MMIO_QUEUE_USED_LOW 0x0a0 123*4882a593Smuzhiyun #define VIRTIO_MMIO_QUEUE_USED_HIGH 0x0a4 124*4882a593Smuzhiyun 125*4882a593Smuzhiyun /* Shared memory region id */ 126*4882a593Smuzhiyun #define VIRTIO_MMIO_SHM_SEL 0x0ac 127*4882a593Smuzhiyun 128*4882a593Smuzhiyun /* Shared memory region length, 64 bits in two halves */ 129*4882a593Smuzhiyun #define VIRTIO_MMIO_SHM_LEN_LOW 0x0b0 130*4882a593Smuzhiyun #define VIRTIO_MMIO_SHM_LEN_HIGH 0x0b4 131*4882a593Smuzhiyun 132*4882a593Smuzhiyun /* Shared memory region base address, 64 bits in two halves */ 133*4882a593Smuzhiyun #define VIRTIO_MMIO_SHM_BASE_LOW 0x0b8 134*4882a593Smuzhiyun #define VIRTIO_MMIO_SHM_BASE_HIGH 0x0bc 135*4882a593Smuzhiyun 136*4882a593Smuzhiyun /* Configuration atomicity value */ 137*4882a593Smuzhiyun #define VIRTIO_MMIO_CONFIG_GENERATION 0x0fc 138*4882a593Smuzhiyun 139*4882a593Smuzhiyun /* The config space is defined by each driver as 140*4882a593Smuzhiyun * the per-driver configuration space - Read Write */ 141*4882a593Smuzhiyun #define VIRTIO_MMIO_CONFIG 0x100 142*4882a593Smuzhiyun 143*4882a593Smuzhiyun 144*4882a593Smuzhiyun 145*4882a593Smuzhiyun /* 146*4882a593Smuzhiyun * Interrupt flags (re: interrupt status & acknowledge registers) 147*4882a593Smuzhiyun */ 148*4882a593Smuzhiyun 149*4882a593Smuzhiyun #define VIRTIO_MMIO_INT_VRING (1 << 0) 150*4882a593Smuzhiyun #define VIRTIO_MMIO_INT_CONFIG (1 << 1) 151*4882a593Smuzhiyun 152*4882a593Smuzhiyun #endif 153