1*4882a593Smuzhiyun /* SPDX-License-Identifier: BSD-3-Clause */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Virtio-iommu definition v0.12 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Copyright (C) 2019 Arm Ltd. 6*4882a593Smuzhiyun */ 7*4882a593Smuzhiyun #ifndef _UAPI_LINUX_VIRTIO_IOMMU_H 8*4882a593Smuzhiyun #define _UAPI_LINUX_VIRTIO_IOMMU_H 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun #include <linux/types.h> 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun /* Feature bits */ 13*4882a593Smuzhiyun #define VIRTIO_IOMMU_F_INPUT_RANGE 0 14*4882a593Smuzhiyun #define VIRTIO_IOMMU_F_DOMAIN_RANGE 1 15*4882a593Smuzhiyun #define VIRTIO_IOMMU_F_MAP_UNMAP 2 16*4882a593Smuzhiyun #define VIRTIO_IOMMU_F_BYPASS 3 17*4882a593Smuzhiyun #define VIRTIO_IOMMU_F_PROBE 4 18*4882a593Smuzhiyun #define VIRTIO_IOMMU_F_MMIO 5 19*4882a593Smuzhiyun 20*4882a593Smuzhiyun struct virtio_iommu_range_64 { 21*4882a593Smuzhiyun __le64 start; 22*4882a593Smuzhiyun __le64 end; 23*4882a593Smuzhiyun }; 24*4882a593Smuzhiyun 25*4882a593Smuzhiyun struct virtio_iommu_range_32 { 26*4882a593Smuzhiyun __le32 start; 27*4882a593Smuzhiyun __le32 end; 28*4882a593Smuzhiyun }; 29*4882a593Smuzhiyun 30*4882a593Smuzhiyun struct virtio_iommu_config { 31*4882a593Smuzhiyun /* Supported page sizes */ 32*4882a593Smuzhiyun __le64 page_size_mask; 33*4882a593Smuzhiyun /* Supported IOVA range */ 34*4882a593Smuzhiyun struct virtio_iommu_range_64 input_range; 35*4882a593Smuzhiyun /* Max domain ID size */ 36*4882a593Smuzhiyun struct virtio_iommu_range_32 domain_range; 37*4882a593Smuzhiyun /* Probe buffer size */ 38*4882a593Smuzhiyun __le32 probe_size; 39*4882a593Smuzhiyun }; 40*4882a593Smuzhiyun 41*4882a593Smuzhiyun /* Request types */ 42*4882a593Smuzhiyun #define VIRTIO_IOMMU_T_ATTACH 0x01 43*4882a593Smuzhiyun #define VIRTIO_IOMMU_T_DETACH 0x02 44*4882a593Smuzhiyun #define VIRTIO_IOMMU_T_MAP 0x03 45*4882a593Smuzhiyun #define VIRTIO_IOMMU_T_UNMAP 0x04 46*4882a593Smuzhiyun #define VIRTIO_IOMMU_T_PROBE 0x05 47*4882a593Smuzhiyun 48*4882a593Smuzhiyun /* Status types */ 49*4882a593Smuzhiyun #define VIRTIO_IOMMU_S_OK 0x00 50*4882a593Smuzhiyun #define VIRTIO_IOMMU_S_IOERR 0x01 51*4882a593Smuzhiyun #define VIRTIO_IOMMU_S_UNSUPP 0x02 52*4882a593Smuzhiyun #define VIRTIO_IOMMU_S_DEVERR 0x03 53*4882a593Smuzhiyun #define VIRTIO_IOMMU_S_INVAL 0x04 54*4882a593Smuzhiyun #define VIRTIO_IOMMU_S_RANGE 0x05 55*4882a593Smuzhiyun #define VIRTIO_IOMMU_S_NOENT 0x06 56*4882a593Smuzhiyun #define VIRTIO_IOMMU_S_FAULT 0x07 57*4882a593Smuzhiyun #define VIRTIO_IOMMU_S_NOMEM 0x08 58*4882a593Smuzhiyun 59*4882a593Smuzhiyun struct virtio_iommu_req_head { 60*4882a593Smuzhiyun __u8 type; 61*4882a593Smuzhiyun __u8 reserved[3]; 62*4882a593Smuzhiyun }; 63*4882a593Smuzhiyun 64*4882a593Smuzhiyun struct virtio_iommu_req_tail { 65*4882a593Smuzhiyun __u8 status; 66*4882a593Smuzhiyun __u8 reserved[3]; 67*4882a593Smuzhiyun }; 68*4882a593Smuzhiyun 69*4882a593Smuzhiyun struct virtio_iommu_req_attach { 70*4882a593Smuzhiyun struct virtio_iommu_req_head head; 71*4882a593Smuzhiyun __le32 domain; 72*4882a593Smuzhiyun __le32 endpoint; 73*4882a593Smuzhiyun __u8 reserved[8]; 74*4882a593Smuzhiyun struct virtio_iommu_req_tail tail; 75*4882a593Smuzhiyun }; 76*4882a593Smuzhiyun 77*4882a593Smuzhiyun struct virtio_iommu_req_detach { 78*4882a593Smuzhiyun struct virtio_iommu_req_head head; 79*4882a593Smuzhiyun __le32 domain; 80*4882a593Smuzhiyun __le32 endpoint; 81*4882a593Smuzhiyun __u8 reserved[8]; 82*4882a593Smuzhiyun struct virtio_iommu_req_tail tail; 83*4882a593Smuzhiyun }; 84*4882a593Smuzhiyun 85*4882a593Smuzhiyun #define VIRTIO_IOMMU_MAP_F_READ (1 << 0) 86*4882a593Smuzhiyun #define VIRTIO_IOMMU_MAP_F_WRITE (1 << 1) 87*4882a593Smuzhiyun #define VIRTIO_IOMMU_MAP_F_MMIO (1 << 2) 88*4882a593Smuzhiyun 89*4882a593Smuzhiyun #define VIRTIO_IOMMU_MAP_F_MASK (VIRTIO_IOMMU_MAP_F_READ | \ 90*4882a593Smuzhiyun VIRTIO_IOMMU_MAP_F_WRITE | \ 91*4882a593Smuzhiyun VIRTIO_IOMMU_MAP_F_MMIO) 92*4882a593Smuzhiyun 93*4882a593Smuzhiyun struct virtio_iommu_req_map { 94*4882a593Smuzhiyun struct virtio_iommu_req_head head; 95*4882a593Smuzhiyun __le32 domain; 96*4882a593Smuzhiyun __le64 virt_start; 97*4882a593Smuzhiyun __le64 virt_end; 98*4882a593Smuzhiyun __le64 phys_start; 99*4882a593Smuzhiyun __le32 flags; 100*4882a593Smuzhiyun struct virtio_iommu_req_tail tail; 101*4882a593Smuzhiyun }; 102*4882a593Smuzhiyun 103*4882a593Smuzhiyun struct virtio_iommu_req_unmap { 104*4882a593Smuzhiyun struct virtio_iommu_req_head head; 105*4882a593Smuzhiyun __le32 domain; 106*4882a593Smuzhiyun __le64 virt_start; 107*4882a593Smuzhiyun __le64 virt_end; 108*4882a593Smuzhiyun __u8 reserved[4]; 109*4882a593Smuzhiyun struct virtio_iommu_req_tail tail; 110*4882a593Smuzhiyun }; 111*4882a593Smuzhiyun 112*4882a593Smuzhiyun #define VIRTIO_IOMMU_PROBE_T_NONE 0 113*4882a593Smuzhiyun #define VIRTIO_IOMMU_PROBE_T_RESV_MEM 1 114*4882a593Smuzhiyun 115*4882a593Smuzhiyun #define VIRTIO_IOMMU_PROBE_T_MASK 0xfff 116*4882a593Smuzhiyun 117*4882a593Smuzhiyun struct virtio_iommu_probe_property { 118*4882a593Smuzhiyun __le16 type; 119*4882a593Smuzhiyun __le16 length; 120*4882a593Smuzhiyun }; 121*4882a593Smuzhiyun 122*4882a593Smuzhiyun #define VIRTIO_IOMMU_RESV_MEM_T_RESERVED 0 123*4882a593Smuzhiyun #define VIRTIO_IOMMU_RESV_MEM_T_MSI 1 124*4882a593Smuzhiyun 125*4882a593Smuzhiyun struct virtio_iommu_probe_resv_mem { 126*4882a593Smuzhiyun struct virtio_iommu_probe_property head; 127*4882a593Smuzhiyun __u8 subtype; 128*4882a593Smuzhiyun __u8 reserved[3]; 129*4882a593Smuzhiyun __le64 start; 130*4882a593Smuzhiyun __le64 end; 131*4882a593Smuzhiyun }; 132*4882a593Smuzhiyun 133*4882a593Smuzhiyun struct virtio_iommu_req_probe { 134*4882a593Smuzhiyun struct virtio_iommu_req_head head; 135*4882a593Smuzhiyun __le32 endpoint; 136*4882a593Smuzhiyun __u8 reserved[64]; 137*4882a593Smuzhiyun 138*4882a593Smuzhiyun __u8 properties[]; 139*4882a593Smuzhiyun 140*4882a593Smuzhiyun /* 141*4882a593Smuzhiyun * Tail follows the variable-length properties array. No padding, 142*4882a593Smuzhiyun * property lengths are all aligned on 8 bytes. 143*4882a593Smuzhiyun */ 144*4882a593Smuzhiyun }; 145*4882a593Smuzhiyun 146*4882a593Smuzhiyun /* Fault types */ 147*4882a593Smuzhiyun #define VIRTIO_IOMMU_FAULT_R_UNKNOWN 0 148*4882a593Smuzhiyun #define VIRTIO_IOMMU_FAULT_R_DOMAIN 1 149*4882a593Smuzhiyun #define VIRTIO_IOMMU_FAULT_R_MAPPING 2 150*4882a593Smuzhiyun 151*4882a593Smuzhiyun #define VIRTIO_IOMMU_FAULT_F_READ (1 << 0) 152*4882a593Smuzhiyun #define VIRTIO_IOMMU_FAULT_F_WRITE (1 << 1) 153*4882a593Smuzhiyun #define VIRTIO_IOMMU_FAULT_F_EXEC (1 << 2) 154*4882a593Smuzhiyun #define VIRTIO_IOMMU_FAULT_F_ADDRESS (1 << 8) 155*4882a593Smuzhiyun 156*4882a593Smuzhiyun struct virtio_iommu_fault { 157*4882a593Smuzhiyun __u8 reason; 158*4882a593Smuzhiyun __u8 reserved[3]; 159*4882a593Smuzhiyun __le32 flags; 160*4882a593Smuzhiyun __le32 endpoint; 161*4882a593Smuzhiyun __u8 reserved2[4]; 162*4882a593Smuzhiyun __le64 address; 163*4882a593Smuzhiyun }; 164*4882a593Smuzhiyun 165*4882a593Smuzhiyun #endif 166