1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */ 2*4882a593Smuzhiyun /* $Id: scc.h,v 1.29 1997/04/02 14:56:45 jreuter Exp jreuter $ */ 3*4882a593Smuzhiyun 4*4882a593Smuzhiyun #ifndef _UAPI_SCC_H 5*4882a593Smuzhiyun #define _UAPI_SCC_H 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun #include <linux/sockios.h> 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun /* selection of hardware types */ 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun #define PA0HZP 0x00 /* hardware type for PA0HZP SCC card and compatible */ 12*4882a593Smuzhiyun #define EAGLE 0x01 /* hardware type for EAGLE card */ 13*4882a593Smuzhiyun #define PC100 0x02 /* hardware type for PC100 card */ 14*4882a593Smuzhiyun #define PRIMUS 0x04 /* hardware type for PRIMUS-PC (DG9BL) card */ 15*4882a593Smuzhiyun #define DRSI 0x08 /* hardware type for DRSI PC*Packet card */ 16*4882a593Smuzhiyun #define BAYCOM 0x10 /* hardware type for BayCom (U)SCC */ 17*4882a593Smuzhiyun 18*4882a593Smuzhiyun /* DEV ioctl() commands */ 19*4882a593Smuzhiyun 20*4882a593Smuzhiyun enum SCC_ioctl_cmds { 21*4882a593Smuzhiyun SIOCSCCRESERVED = SIOCDEVPRIVATE, 22*4882a593Smuzhiyun SIOCSCCCFG, 23*4882a593Smuzhiyun SIOCSCCINI, 24*4882a593Smuzhiyun SIOCSCCCHANINI, 25*4882a593Smuzhiyun SIOCSCCSMEM, 26*4882a593Smuzhiyun SIOCSCCGKISS, 27*4882a593Smuzhiyun SIOCSCCSKISS, 28*4882a593Smuzhiyun SIOCSCCGSTAT, 29*4882a593Smuzhiyun SIOCSCCCAL 30*4882a593Smuzhiyun }; 31*4882a593Smuzhiyun 32*4882a593Smuzhiyun /* Device parameter control (from WAMPES) */ 33*4882a593Smuzhiyun 34*4882a593Smuzhiyun enum L1_params { 35*4882a593Smuzhiyun PARAM_DATA, 36*4882a593Smuzhiyun PARAM_TXDELAY, 37*4882a593Smuzhiyun PARAM_PERSIST, 38*4882a593Smuzhiyun PARAM_SLOTTIME, 39*4882a593Smuzhiyun PARAM_TXTAIL, 40*4882a593Smuzhiyun PARAM_FULLDUP, 41*4882a593Smuzhiyun PARAM_SOFTDCD, /* was: PARAM_HW */ 42*4882a593Smuzhiyun PARAM_MUTE, /* ??? */ 43*4882a593Smuzhiyun PARAM_DTR, 44*4882a593Smuzhiyun PARAM_RTS, 45*4882a593Smuzhiyun PARAM_SPEED, 46*4882a593Smuzhiyun PARAM_ENDDELAY, /* ??? */ 47*4882a593Smuzhiyun PARAM_GROUP, 48*4882a593Smuzhiyun PARAM_IDLE, 49*4882a593Smuzhiyun PARAM_MIN, 50*4882a593Smuzhiyun PARAM_MAXKEY, 51*4882a593Smuzhiyun PARAM_WAIT, 52*4882a593Smuzhiyun PARAM_MAXDEFER, 53*4882a593Smuzhiyun PARAM_TX, 54*4882a593Smuzhiyun PARAM_HWEVENT = 31, 55*4882a593Smuzhiyun PARAM_RETURN = 255 /* reset kiss mode */ 56*4882a593Smuzhiyun }; 57*4882a593Smuzhiyun 58*4882a593Smuzhiyun /* fulldup parameter */ 59*4882a593Smuzhiyun 60*4882a593Smuzhiyun enum FULLDUP_modes { 61*4882a593Smuzhiyun KISS_DUPLEX_HALF, /* normal CSMA operation */ 62*4882a593Smuzhiyun KISS_DUPLEX_FULL, /* fullduplex, key down trx after transmission */ 63*4882a593Smuzhiyun KISS_DUPLEX_LINK, /* fullduplex, key down trx after 'idletime' sec */ 64*4882a593Smuzhiyun KISS_DUPLEX_OPTIMA /* fullduplex, let the protocol layer control the hw */ 65*4882a593Smuzhiyun }; 66*4882a593Smuzhiyun 67*4882a593Smuzhiyun /* misc. parameters */ 68*4882a593Smuzhiyun 69*4882a593Smuzhiyun #define TIMER_OFF 65535U /* to switch off timers */ 70*4882a593Smuzhiyun #define NO_SUCH_PARAM 65534U /* param not implemented */ 71*4882a593Smuzhiyun 72*4882a593Smuzhiyun /* HWEVENT parameter */ 73*4882a593Smuzhiyun 74*4882a593Smuzhiyun enum HWEVENT_opts { 75*4882a593Smuzhiyun HWEV_DCD_ON, 76*4882a593Smuzhiyun HWEV_DCD_OFF, 77*4882a593Smuzhiyun HWEV_ALL_SENT 78*4882a593Smuzhiyun }; 79*4882a593Smuzhiyun 80*4882a593Smuzhiyun /* channel grouping */ 81*4882a593Smuzhiyun 82*4882a593Smuzhiyun #define RXGROUP 0100 /* if set, only tx when all channels clear */ 83*4882a593Smuzhiyun #define TXGROUP 0200 /* if set, don't transmit simultaneously */ 84*4882a593Smuzhiyun 85*4882a593Smuzhiyun /* Tx/Rx clock sources */ 86*4882a593Smuzhiyun 87*4882a593Smuzhiyun enum CLOCK_sources { 88*4882a593Smuzhiyun CLK_DPLL, /* normal halfduplex operation */ 89*4882a593Smuzhiyun CLK_EXTERNAL, /* external clocking (G3RUH/DF9IC modems) */ 90*4882a593Smuzhiyun CLK_DIVIDER, /* Rx = DPLL, Tx = divider (fullduplex with */ 91*4882a593Smuzhiyun /* modems without clock regeneration */ 92*4882a593Smuzhiyun CLK_BRG /* experimental fullduplex mode with DPLL/BRG for */ 93*4882a593Smuzhiyun /* MODEMs without clock recovery */ 94*4882a593Smuzhiyun }; 95*4882a593Smuzhiyun 96*4882a593Smuzhiyun /* Tx state */ 97*4882a593Smuzhiyun 98*4882a593Smuzhiyun enum TX_state { 99*4882a593Smuzhiyun TXS_IDLE, /* Transmitter off, no data pending */ 100*4882a593Smuzhiyun TXS_BUSY, /* waiting for permission to send / tailtime */ 101*4882a593Smuzhiyun TXS_ACTIVE, /* Transmitter on, sending data */ 102*4882a593Smuzhiyun TXS_NEWFRAME, /* reset CRC and send (next) frame */ 103*4882a593Smuzhiyun TXS_IDLE2, /* Transmitter on, no data pending */ 104*4882a593Smuzhiyun TXS_WAIT, /* Waiting for Mintime to expire */ 105*4882a593Smuzhiyun TXS_TIMEOUT /* We had a transmission timeout */ 106*4882a593Smuzhiyun }; 107*4882a593Smuzhiyun 108*4882a593Smuzhiyun typedef unsigned long io_port; /* type definition for an 'io port address' */ 109*4882a593Smuzhiyun 110*4882a593Smuzhiyun /* SCC statistical information */ 111*4882a593Smuzhiyun 112*4882a593Smuzhiyun struct scc_stat { 113*4882a593Smuzhiyun long rxints; /* Receiver interrupts */ 114*4882a593Smuzhiyun long txints; /* Transmitter interrupts */ 115*4882a593Smuzhiyun long exints; /* External/status interrupts */ 116*4882a593Smuzhiyun long spints; /* Special receiver interrupts */ 117*4882a593Smuzhiyun 118*4882a593Smuzhiyun long txframes; /* Packets sent */ 119*4882a593Smuzhiyun long rxframes; /* Number of Frames Actually Received */ 120*4882a593Smuzhiyun long rxerrs; /* CRC Errors */ 121*4882a593Smuzhiyun long txerrs; /* KISS errors */ 122*4882a593Smuzhiyun 123*4882a593Smuzhiyun unsigned int nospace; /* "Out of buffers" */ 124*4882a593Smuzhiyun unsigned int rx_over; /* Receiver Overruns */ 125*4882a593Smuzhiyun unsigned int tx_under; /* Transmitter Underruns */ 126*4882a593Smuzhiyun 127*4882a593Smuzhiyun unsigned int tx_state; /* Transmitter state */ 128*4882a593Smuzhiyun int tx_queued; /* tx frames enqueued */ 129*4882a593Smuzhiyun 130*4882a593Smuzhiyun unsigned int maxqueue; /* allocated tx_buffers */ 131*4882a593Smuzhiyun unsigned int bufsize; /* used buffersize */ 132*4882a593Smuzhiyun }; 133*4882a593Smuzhiyun 134*4882a593Smuzhiyun struct scc_modem { 135*4882a593Smuzhiyun long speed; /* Line speed, bps */ 136*4882a593Smuzhiyun char clocksrc; /* 0 = DPLL, 1 = external, 2 = divider */ 137*4882a593Smuzhiyun char nrz; /* NRZ instead of NRZI */ 138*4882a593Smuzhiyun }; 139*4882a593Smuzhiyun 140*4882a593Smuzhiyun struct scc_kiss_cmd { 141*4882a593Smuzhiyun int command; /* one of the KISS-Commands defined above */ 142*4882a593Smuzhiyun unsigned param; /* KISS-Param */ 143*4882a593Smuzhiyun }; 144*4882a593Smuzhiyun 145*4882a593Smuzhiyun struct scc_hw_config { 146*4882a593Smuzhiyun io_port data_a; /* data port channel A */ 147*4882a593Smuzhiyun io_port ctrl_a; /* control port channel A */ 148*4882a593Smuzhiyun io_port data_b; /* data port channel B */ 149*4882a593Smuzhiyun io_port ctrl_b; /* control port channel B */ 150*4882a593Smuzhiyun io_port vector_latch; /* INTACK-Latch (#) */ 151*4882a593Smuzhiyun io_port special; /* special function port */ 152*4882a593Smuzhiyun 153*4882a593Smuzhiyun int irq; /* irq */ 154*4882a593Smuzhiyun long clock; /* clock */ 155*4882a593Smuzhiyun char option; /* command for function port */ 156*4882a593Smuzhiyun 157*4882a593Smuzhiyun char brand; /* hardware type */ 158*4882a593Smuzhiyun char escc; /* use ext. features of a 8580/85180/85280 */ 159*4882a593Smuzhiyun }; 160*4882a593Smuzhiyun 161*4882a593Smuzhiyun /* (#) only one INTACK latch allowed. */ 162*4882a593Smuzhiyun 163*4882a593Smuzhiyun 164*4882a593Smuzhiyun struct scc_mem_config { 165*4882a593Smuzhiyun unsigned int dummy; 166*4882a593Smuzhiyun unsigned int bufsize; 167*4882a593Smuzhiyun }; 168*4882a593Smuzhiyun 169*4882a593Smuzhiyun struct scc_calibrate { 170*4882a593Smuzhiyun unsigned int time; 171*4882a593Smuzhiyun unsigned char pattern; 172*4882a593Smuzhiyun }; 173*4882a593Smuzhiyun 174*4882a593Smuzhiyun #endif /* _UAPI_SCC_H */ 175