1*4882a593Smuzhiyun /* SPDX-License-Identifier: ((GPL-2.0+ WITH Linux-syscall-note) OR MIT) */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Rockchip preisp driver 4*4882a593Smuzhiyun * Copyright (C) 2018 Rockchip Electronics Co., Ltd. 5*4882a593Smuzhiyun */ 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun #ifndef _UAPI_RKPREISP_H 8*4882a593Smuzhiyun #define _UAPI_RKPREISP_H 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun #include <linux/types.h> 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun #define PREISP_FW_NAME_LEN 128 13*4882a593Smuzhiyun 14*4882a593Smuzhiyun #define PREISP_LSCTBL_SIZE 289 15*4882a593Smuzhiyun 16*4882a593Smuzhiyun #define PREISP_CMD_SET_HDRAE_EXP \ 17*4882a593Smuzhiyun _IOW('V', BASE_VIDIOC_PRIVATE + 0, struct preisp_hdrae_exp_s) 18*4882a593Smuzhiyun 19*4882a593Smuzhiyun #define PREISP_CMD_SAVE_HDRAE_PARAM \ 20*4882a593Smuzhiyun _IOW('V', BASE_VIDIOC_PRIVATE + 1, struct preisp_hdrae_para_s) 21*4882a593Smuzhiyun 22*4882a593Smuzhiyun #define PREISP_DISP_SET_FRAME_OUTPUT \ 23*4882a593Smuzhiyun _IOW('V', BASE_VIDIOC_PRIVATE + 4, int) 24*4882a593Smuzhiyun 25*4882a593Smuzhiyun #define PREISP_DISP_SET_FRAME_FORMAT \ 26*4882a593Smuzhiyun _IOW('V', BASE_VIDIOC_PRIVATE + 5, unsigned int) 27*4882a593Smuzhiyun 28*4882a593Smuzhiyun #define PREISP_DISP_SET_FRAME_TYPE \ 29*4882a593Smuzhiyun _IOW('V', BASE_VIDIOC_PRIVATE + 6, unsigned int) 30*4882a593Smuzhiyun 31*4882a593Smuzhiyun #define PREISP_DISP_SET_PRO_TIME \ 32*4882a593Smuzhiyun _IOW('V', BASE_VIDIOC_PRIVATE + 7, unsigned int) 33*4882a593Smuzhiyun 34*4882a593Smuzhiyun #define PREISP_DISP_SET_PRO_CURRENT \ 35*4882a593Smuzhiyun _IOW('V', BASE_VIDIOC_PRIVATE + 8, unsigned int) 36*4882a593Smuzhiyun 37*4882a593Smuzhiyun #define PREISP_DISP_SET_DENOISE \ 38*4882a593Smuzhiyun _IOW('V', BASE_VIDIOC_PRIVATE + 9, unsigned int[2]) 39*4882a593Smuzhiyun 40*4882a593Smuzhiyun #define PREISP_DISP_WRITE_EEPROM \ 41*4882a593Smuzhiyun _IO('V', BASE_VIDIOC_PRIVATE + 10) 42*4882a593Smuzhiyun 43*4882a593Smuzhiyun #define PREISP_DISP_READ_EEPROM \ 44*4882a593Smuzhiyun _IO('V', BASE_VIDIOC_PRIVATE + 11) 45*4882a593Smuzhiyun 46*4882a593Smuzhiyun #define PREISP_DISP_SET_LED_ON_OFF \ 47*4882a593Smuzhiyun _IOW('V', BASE_VIDIOC_PRIVATE + 12, unsigned int) 48*4882a593Smuzhiyun 49*4882a593Smuzhiyun #define PREISP_POWER_ON _IO('p', 1) 50*4882a593Smuzhiyun #define PREISP_POWER_OFF _IO('p', 2) 51*4882a593Smuzhiyun #define PREISP_REQUEST_SLEEP _IOW('p', 3, __s32) 52*4882a593Smuzhiyun #define PREISP_WAKEUP _IO('p', 4) 53*4882a593Smuzhiyun #define PREISP_DOWNLOAD_FW _IOW('p', 5, char[PREISP_FW_NAME_LEN]) 54*4882a593Smuzhiyun #define PREISP_WRITE _IOW('p', 6, struct preisp_apb_pkt) 55*4882a593Smuzhiyun #define PREISP_READ _IOR('p', 7, struct preisp_apb_pkt) 56*4882a593Smuzhiyun #define PREISP_ST_QUERY _IOR('p', 8, __s32) 57*4882a593Smuzhiyun #define PREISP_IRQ_REQUEST _IOW('p', 9, __s32) 58*4882a593Smuzhiyun #define PREISP_SEND_MSG _IOW('p', 11, __s32) 59*4882a593Smuzhiyun #define PREISP_QUERY_MSG _IOR('p', 12, __s32) 60*4882a593Smuzhiyun #define PREISP_RECV_MSG _IOR('p', 13, __s32) 61*4882a593Smuzhiyun #define PREISP_CLIENT_CONNECT _IOW('p', 15, __s32) 62*4882a593Smuzhiyun #define PREISP_CLIENT_DISCONNECT _IO('p', 16) 63*4882a593Smuzhiyun 64*4882a593Smuzhiyun struct preisp_apb_pkt { 65*4882a593Smuzhiyun __s32 data_len; 66*4882a593Smuzhiyun __s32 addr; 67*4882a593Smuzhiyun __s32 *data; 68*4882a593Smuzhiyun }; 69*4882a593Smuzhiyun 70*4882a593Smuzhiyun /** 71*4882a593Smuzhiyun * struct preisp_hdrae_para_s - awb and lsc para for preisp 72*4882a593Smuzhiyun * 73*4882a593Smuzhiyun * @r_gain: awb r gain 74*4882a593Smuzhiyun * @b_gain: awb b gain 75*4882a593Smuzhiyun * @gr_gain: awb gr gain 76*4882a593Smuzhiyun * @gb_gain: awb gb gain 77*4882a593Smuzhiyun * @lsc_table: lsc data of gr 78*4882a593Smuzhiyun */ 79*4882a593Smuzhiyun struct preisp_hdrae_para_s { 80*4882a593Smuzhiyun unsigned short r_gain; 81*4882a593Smuzhiyun unsigned short b_gain; 82*4882a593Smuzhiyun unsigned short gr_gain; 83*4882a593Smuzhiyun unsigned short gb_gain; 84*4882a593Smuzhiyun int lsc_table[PREISP_LSCTBL_SIZE]; 85*4882a593Smuzhiyun }; 86*4882a593Smuzhiyun 87*4882a593Smuzhiyun /* 88*4882a593Smuzhiyun * enum cg_mode_e conversion gain 89*4882a593Smuzhiyun * 90*4882a593Smuzhiyun */ 91*4882a593Smuzhiyun enum cg_mode_e { 92*4882a593Smuzhiyun GAIN_MODE_LCG, 93*4882a593Smuzhiyun GAIN_MODE_HCG, 94*4882a593Smuzhiyun }; 95*4882a593Smuzhiyun 96*4882a593Smuzhiyun /** 97*4882a593Smuzhiyun * struct preisp_hdrae_exp_s - hdrae exposure 98*4882a593Smuzhiyun * 99*4882a593Smuzhiyun */ 100*4882a593Smuzhiyun struct preisp_hdrae_exp_s { 101*4882a593Smuzhiyun unsigned int long_exp_reg; 102*4882a593Smuzhiyun unsigned int long_gain_reg; 103*4882a593Smuzhiyun unsigned int middle_exp_reg; 104*4882a593Smuzhiyun unsigned int middle_gain_reg; 105*4882a593Smuzhiyun unsigned int short_exp_reg; 106*4882a593Smuzhiyun unsigned int short_gain_reg; 107*4882a593Smuzhiyun unsigned int long_exp_val; 108*4882a593Smuzhiyun unsigned int long_gain_val; 109*4882a593Smuzhiyun unsigned int middle_exp_val; 110*4882a593Smuzhiyun unsigned int middle_gain_val; 111*4882a593Smuzhiyun unsigned int short_exp_val; 112*4882a593Smuzhiyun unsigned int short_gain_val; 113*4882a593Smuzhiyun unsigned char long_cg_mode; 114*4882a593Smuzhiyun unsigned char middle_cg_mode; 115*4882a593Smuzhiyun unsigned char short_cg_mode; 116*4882a593Smuzhiyun }; 117*4882a593Smuzhiyun 118*4882a593Smuzhiyun #endif /* _UAPI_RKPREISP_H */ 119